[mirror_ubuntu-artful-kernel.git] / arch / mips / ath79 / clock.c

/*
 *  Atheros AR71XX/AR724X/AR913X common routines
 *
 *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
 *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
 *
 *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License version 2 as published
 *  by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>

#include <asm/div64.h>

#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include "common.h"

#define AR71XX_BASE_FREQ	40000000
#define AR724X_BASE_FREQ	5000000
#define AR913X_BASE_FREQ	5000000

static struct clk *clks[3];
static struct clk_onecell_data clk_data = {
	.clks = clks,
	.clk_num = ARRAY_SIZE(clks),
};

static struct clk *__init ath79_add_sys_clkdev(
	const char *id, unsigned long rate)
{
	struct clk *clk;
	int err;

	clk = clk_register_fixed_rate(NULL, id, NULL, CLK_IS_ROOT, rate);
	if (!clk)
		panic("failed to allocate %s clock structure", id);

	err = clk_register_clkdev(clk, id, NULL);
	if (err)
		panic("unable to register %s clock device", id);

	return clk;
}

static void __init ar71xx_clocks_init(void)
{
	unsigned long ref_rate;
	unsigned long cpu_rate;
	unsigned long ddr_rate;
	unsigned long ahb_rate;
	u32 pll;
	u32 freq;
	u32 div;

	ref_rate = AR71XX_BASE_FREQ;

	pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);

	div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;
	freq = div * ref_rate;

	div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
	cpu_rate = freq / div;

	div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
	ddr_rate = freq / div;

	div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
	ahb_rate = cpu_rate / div;

	ath79_add_sys_clkdev("ref", ref_rate);
	clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
	clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
	clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);

	clk_add_alias("wdt", NULL, "ahb", NULL);
	clk_add_alias("uart", NULL, "ahb", NULL);
}

static void __init ar724x_clocks_init(void)
{
	unsigned long ref_rate;
	unsigned long cpu_rate;
	unsigned long ddr_rate;
	unsigned long ahb_rate;
	u32 pll;
	u32 freq;
	u32 div;

	ref_rate = AR724X_BASE_FREQ;
	pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG);

	div = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);
	freq = div * ref_rate;

	div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
	freq *= div;

	cpu_rate = freq;

	div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
	ddr_rate = freq / div;

	div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
	ahb_rate = cpu_rate / div;

	ath79_add_sys_clkdev("ref", ref_rate);
	clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
	clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
	clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);

	clk_add_alias("wdt", NULL, "ahb", NULL);
	clk_add_alias("uart", NULL, "ahb", NULL);
}

static void __init ar913x_clocks_init(void)
{
	unsigned long ref_rate;
	unsigned long cpu_rate;
	unsigned long ddr_rate;
	unsigned long ahb_rate;
	u32 pll;
	u32 freq;
	u32 div;

	ref_rate = AR913X_BASE_FREQ;
	pll = ath79_pll_rr(AR913X_PLL_REG_CPU_CONFIG);

	div = ((pll >> AR913X_PLL_FB_SHIFT) & AR913X_PLL_FB_MASK);
	freq = div * ref_rate;

	cpu_rate = freq;

	div = ((pll >> AR913X_DDR_DIV_SHIFT) & AR913X_DDR_DIV_MASK) + 1;
	ddr_rate = freq / div;

	div = (((pll >> AR913X_AHB_DIV_SHIFT) & AR913X_AHB_DIV_MASK) + 1) * 2;
	ahb_rate = cpu_rate / div;

	ath79_add_sys_clkdev("ref", ref_rate);
	clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
	clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
	clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);

	clk_add_alias("wdt", NULL, "ahb", NULL);
	clk_add_alias("uart", NULL, "ahb", NULL);
}

static void __init ar933x_clocks_init(void)
{
	unsigned long ref_rate;
	unsigned long cpu_rate;
	unsigned long ddr_rate;
	unsigned long ahb_rate;
	u32 clock_ctrl;
	u32 cpu_config;
	u32 freq;
	u32 t;

	t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
	if (t & AR933X_BOOTSTRAP_REF_CLK_40)
		ref_rate = (40 * 1000 * 1000);
	else
		ref_rate = (25 * 1000 * 1000);

	clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG);
	if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
		cpu_rate = ref_rate;
		ahb_rate = ref_rate;
		ddr_rate = ref_rate;
	} else {
		cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG);

		t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
		    AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
		freq = ref_rate / t;

		t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
		    AR933X_PLL_CPU_CONFIG_NINT_MASK;
		freq *= t;

		t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
		    AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
		if (t == 0)
			t = 1;

		freq >>= t;

		t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
		     AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
		cpu_rate = freq / t;

		t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
		      AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
		ddr_rate = freq / t;

		t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
		     AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
		ahb_rate = freq / t;
	}

	ath79_add_sys_clkdev("ref", ref_rate);
	clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
	clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
	clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);

	clk_add_alias("wdt", NULL, "ahb", NULL);
	clk_add_alias("uart", NULL, "ref", NULL);
}

static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
				      u32 frac, u32 out_div)
{
	u64 t;
	u32 ret;

	t = ref;
	t *= nint;
	do_div(t, ref_div);
	ret = t;

	t = ref;
	t *= nfrac;
	do_div(t, ref_div * frac);
	ret += t;

	ret /= (1 << out_div);
	return ret;
}

static void __init ar934x_clocks_init(void)
{
	unsigned long ref_rate;
	unsigned long cpu_rate;
	unsigned long ddr_rate;
	unsigned long ahb_rate;
	u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
	u32 cpu_pll, ddr_pll;
	u32 bootstrap;
	void __iomem *dpll_base;

	dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE);

	bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
	if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
		ref_rate = 40 * 1000 * 1000;
	else
		ref_rate = 25 * 1000 * 1000;

	pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
	if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
		out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
			  AR934X_SRIF_DPLL2_OUTDIV_MASK;
		pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG);
		nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
		       AR934X_SRIF_DPLL1_NINT_MASK;
		nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
		ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
			  AR934X_SRIF_DPLL1_REFDIV_MASK;
		frac = 1 << 18;
	} else {
		pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
		out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
			AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
		ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
			  AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
		nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
		       AR934X_PLL_CPU_CONFIG_NINT_MASK;
		nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
			AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
		frac = 1 << 6;
	}

	cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
				      nfrac, frac, out_div);

	pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);
	if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
		out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
			  AR934X_SRIF_DPLL2_OUTDIV_MASK;
		pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG);
		nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
		       AR934X_SRIF_DPLL1_NINT_MASK;
		nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
		ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
			  AR934X_SRIF_DPLL1_REFDIV_MASK;
		frac = 1 << 18;
	} else {
		pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
		out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
			  AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
		ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
			   AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
		nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
		       AR934X_PLL_DDR_CONFIG_NINT_MASK;
		nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
			AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
		frac = 1 << 10;
	}

	ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
				      nfrac, frac, out_div);

	clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);

	postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
		  AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;

	if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
		cpu_rate = ref_rate;
	else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
		cpu_rate = cpu_pll / (postdiv + 1);
	else
		cpu_rate = ddr_pll / (postdiv + 1);

	postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
		  AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;

	if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
		ddr_rate = ref_rate;
	else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
		ddr_rate = ddr_pll / (postdiv + 1);
	else
		ddr_rate = cpu_pll / (postdiv + 1);

	postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
		  AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;

	if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
		ahb_rate = ref_rate;
	else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
		ahb_rate = ddr_pll / (postdiv + 1);
	else
		ahb_rate = cpu_pll / (postdiv + 1);

	ath79_add_sys_clkdev("ref", ref_rate);
	clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
	clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
	clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);

	clk_add_alias("wdt", NULL, "ref", NULL);
	clk_add_alias("uart", NULL, "ref", NULL);

	iounmap(dpll_base);
}

static void __init qca955x_clocks_init(void)
{
	unsigned long ref_rate;
	unsigned long cpu_rate;
	unsigned long ddr_rate;
	unsigned long ahb_rate;
	u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
	u32 cpu_pll, ddr_pll;
	u32 bootstrap;

	bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
	if (bootstrap &	QCA955X_BOOTSTRAP_REF_CLK_40)
		ref_rate = 40 * 1000 * 1000;
	else
		ref_rate = 25 * 1000 * 1000;

	pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
	out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
		  QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
	ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
		  QCA955X_PLL_CPU_CONFIG_REFDIV_MASK;
	nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
	       QCA955X_PLL_CPU_CONFIG_NINT_MASK;
	frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
	       QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;

	cpu_pll = nint * ref_rate / ref_div;
	cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
	cpu_pll /= (1 << out_div);

	pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
	out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
		  QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
	ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
		  QCA955X_PLL_DDR_CONFIG_REFDIV_MASK;
	nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
	       QCA955X_PLL_DDR_CONFIG_NINT_MASK;
	frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
	       QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;

	ddr_pll = nint * ref_rate / ref_div;
	ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
	ddr_pll /= (1 << out_div);

	clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);

	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
		  QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;

	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
		cpu_rate = ref_rate;
	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
		cpu_rate = ddr_pll / (postdiv + 1);
	else
		cpu_rate = cpu_pll / (postdiv + 1);

	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
		  QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;

	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
		ddr_rate = ref_rate;
	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
		ddr_rate = cpu_pll / (postdiv + 1);
	else
		ddr_rate = ddr_pll / (postdiv + 1);

	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
		  QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;

	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
		ahb_rate = ref_rate;
	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
		ahb_rate = ddr_pll / (postdiv + 1);
	else
		ahb_rate = cpu_pll / (postdiv + 1);

	ath79_add_sys_clkdev("ref", ref_rate);
	clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
	clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
	clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);

	clk_add_alias("wdt", NULL, "ref", NULL);
	clk_add_alias("uart", NULL, "ref", NULL);
}

void __init ath79_clocks_init(void)
{
	if (soc_is_ar71xx())
		ar71xx_clocks_init();
	else if (soc_is_ar724x())
		ar724x_clocks_init();
	else if (soc_is_ar913x())
		ar913x_clocks_init();
	else if (soc_is_ar933x())
		ar933x_clocks_init();
	else if (soc_is_ar934x())
		ar934x_clocks_init();
	else if (soc_is_qca955x())
		qca955x_clocks_init();
	else
		BUG();

	of_clk_init(NULL);
}

unsigned long __init
ath79_get_sys_clk_rate(const char *id)
{
	struct clk *clk;
	unsigned long rate;

	clk = clk_get(NULL, id);
	if (IS_ERR(clk))
		panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk));

	rate = clk_get_rate(clk);
	clk_put(clk);

	return rate;
}

#ifdef CONFIG_OF
static void __init ath79_clocks_init_dt(struct device_node *np)
{
	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
}

CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt);
CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt);
CLK_OF_DECLARE(ar9130, "qca,ar9130-pll", ath79_clocks_init_dt);
CLK_OF_DECLARE(ar9330, "qca,ar9330-pll", ath79_clocks_init_dt);
CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt);
CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt);
#endif
Commit	Line	Data
d4a67d9d GJ	1	/*
	2	* Atheros AR71XX/AR724X/AR913X common routines
	3	*
8889612b	4	* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
d4a67d9d GJ	5	* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
d4a67d9d GJ	6	*
8889612b GJ	7	* Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
8889612b GJ	8	*
d4a67d9d GJ	9	* This program is free software; you can redistribute it and/or modify it
	10	* under the terms of the GNU General Public License version 2 as published
	11	* by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/module.h>
	16	#include <linux/init.h>
	17	#include <linux/err.h>
	18	#include <linux/clk.h>
2c4f1ac5	19	#include <linux/clkdev.h>
411520af	20	#include <linux/clk-provider.h>
d4a67d9d	21
97541ccf GJ	22	#include <asm/div64.h>
97541ccf GJ	23
d4a67d9d GJ	24	#include <asm/mach-ath79/ath79.h>
	25	#include <asm/mach-ath79/ar71xx_regs.h>
	26	#include "common.h"
	27
	28	#define AR71XX_BASE_FREQ 40000000
	29	#define AR724X_BASE_FREQ 5000000
	30	#define AR913X_BASE_FREQ 5000000
	31
6451af02 AB	32	static struct clk *clks[3];
	33	static struct clk_onecell_data clk_data = {
	34	.clks = clks,
	35	.clk_num = ARRAY_SIZE(clks),
	36	};
	37
	38	static struct clk *__init ath79_add_sys_clkdev(
	39	const char *id, unsigned long rate)
2c4f1ac5 GJ	40	{
	41	struct clk *clk;
	42	int err;
	43
411520af	44	clk = clk_register_fixed_rate(NULL, id, NULL, CLK_IS_ROOT, rate);
2c4f1ac5 GJ	45	if (!clk)
	46	panic("failed to allocate %s clock structure", id);
	47
2c4f1ac5 GJ	48	err = clk_register_clkdev(clk, id, NULL);
	49	if (err)
	50	panic("unable to register %s clock device", id);
6451af02 AB	51
6451af02 AB	52	return clk;
2c4f1ac5	53	}
d4a67d9d GJ	54
	55	static void __init ar71xx_clocks_init(void)
	56	{
6612a688 GJ	57	unsigned long ref_rate;
	58	unsigned long cpu_rate;
	59	unsigned long ddr_rate;
	60	unsigned long ahb_rate;
d4a67d9d GJ	61	u32 pll;
	62	u32 freq;
	63	u32 div;
	64
6612a688	65	ref_rate = AR71XX_BASE_FREQ;
d4a67d9d GJ	66
	67	pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
	68
626a0695	69	div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;
6612a688	70	freq = div * ref_rate;
d4a67d9d GJ	71
d4a67d9d GJ	72	div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
6612a688	73	cpu_rate = freq / div;
d4a67d9d GJ	74
d4a67d9d GJ	75	div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
6612a688	76	ddr_rate = freq / div;
d4a67d9d GJ	77
d4a67d9d GJ	78	div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
6612a688 GJ	79	ahb_rate = cpu_rate / div;
6612a688 GJ	80
2c4f1ac5	81	ath79_add_sys_clkdev("ref", ref_rate);
6451af02 AB	82	clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
	83	clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
	84	clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
d4a67d9d	85
2c4f1ac5 GJ	86	clk_add_alias("wdt", NULL, "ahb", NULL);
2c4f1ac5 GJ	87	clk_add_alias("uart", NULL, "ahb", NULL);
d4a67d9d GJ	88	}
	89
	90	static void __init ar724x_clocks_init(void)
	91	{
6612a688 GJ	92	unsigned long ref_rate;
	93	unsigned long cpu_rate;
	94	unsigned long ddr_rate;
	95	unsigned long ahb_rate;
d4a67d9d GJ	96	u32 pll;
	97	u32 freq;
	98	u32 div;
	99
6612a688	100	ref_rate = AR724X_BASE_FREQ;
d4a67d9d GJ	101	pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
d4a67d9d GJ	102
626a0695	103	div = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);
6612a688	104	freq = div * ref_rate;
d4a67d9d GJ	105
	106	div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
	107	freq *= div;
	108
6612a688	109	cpu_rate = freq;
d4a67d9d GJ	110
d4a67d9d GJ	111	div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
6612a688	112	ddr_rate = freq / div;
d4a67d9d GJ	113
d4a67d9d GJ	114	div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
6612a688 GJ	115	ahb_rate = cpu_rate / div;
6612a688 GJ	116
2c4f1ac5	117	ath79_add_sys_clkdev("ref", ref_rate);
6451af02 AB	118	clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
	119	clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
	120	clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
d4a67d9d	121
2c4f1ac5 GJ	122	clk_add_alias("wdt", NULL, "ahb", NULL);
2c4f1ac5 GJ	123	clk_add_alias("uart", NULL, "ahb", NULL);
d4a67d9d GJ	124	}
	125
	126	static void __init ar913x_clocks_init(void)
	127	{
6612a688 GJ	128	unsigned long ref_rate;
	129	unsigned long cpu_rate;
	130	unsigned long ddr_rate;
	131	unsigned long ahb_rate;
d4a67d9d GJ	132	u32 pll;
	133	u32 freq;
	134	u32 div;
	135
6612a688	136	ref_rate = AR913X_BASE_FREQ;
d4a67d9d GJ	137	pll = ath79_pll_rr(AR913X_PLL_REG_CPU_CONFIG);
d4a67d9d GJ	138
626a0695	139	div = ((pll >> AR913X_PLL_FB_SHIFT) & AR913X_PLL_FB_MASK);
6612a688	140	freq = div * ref_rate;
d4a67d9d	141
6612a688	142	cpu_rate = freq;
d4a67d9d GJ	143
d4a67d9d GJ	144	div = ((pll >> AR913X_DDR_DIV_SHIFT) & AR913X_DDR_DIV_MASK) + 1;
6612a688	145	ddr_rate = freq / div;
d4a67d9d GJ	146
d4a67d9d GJ	147	div = (((pll >> AR913X_AHB_DIV_SHIFT) & AR913X_AHB_DIV_MASK) + 1) * 2;
6612a688 GJ	148	ahb_rate = cpu_rate / div;
6612a688 GJ	149
2c4f1ac5	150	ath79_add_sys_clkdev("ref", ref_rate);
6451af02 AB	151	clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
	152	clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
	153	clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
d4a67d9d	154
2c4f1ac5 GJ	155	clk_add_alias("wdt", NULL, "ahb", NULL);
2c4f1ac5 GJ	156	clk_add_alias("uart", NULL, "ahb", NULL);
d4a67d9d GJ	157	}
d4a67d9d GJ	158
04225e1d GJ	159	static void __init ar933x_clocks_init(void)
04225e1d GJ	160	{
6612a688 GJ	161	unsigned long ref_rate;
	162	unsigned long cpu_rate;
	163	unsigned long ddr_rate;
	164	unsigned long ahb_rate;
04225e1d GJ	165	u32 clock_ctrl;
	166	u32 cpu_config;
	167	u32 freq;
	168	u32 t;
	169
	170	t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
	171	if (t & AR933X_BOOTSTRAP_REF_CLK_40)
6612a688	172	ref_rate = (40 * 1000 * 1000);
04225e1d	173	else
6612a688	174	ref_rate = (25 * 1000 * 1000);
04225e1d GJ	175
	176	clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG);
	177	if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
6612a688 GJ	178	cpu_rate = ref_rate;
	179	ahb_rate = ref_rate;
	180	ddr_rate = ref_rate;
04225e1d GJ	181	} else {
	182	cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG);
	183
	184	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
	185	AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
6612a688	186	freq = ref_rate / t;
04225e1d GJ	187
	188	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
	189	AR933X_PLL_CPU_CONFIG_NINT_MASK;
	190	freq *= t;
	191
	192	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
	193	AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
	194	if (t == 0)
	195	t = 1;
	196
	197	freq >>= t;
	198
	199	t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
	200	AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
6612a688	201	cpu_rate = freq / t;
04225e1d GJ	202
	203	t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
	204	AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
6612a688	205	ddr_rate = freq / t;
04225e1d GJ	206
	207	t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
	208	AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
6612a688	209	ahb_rate = freq / t;
04225e1d GJ	210	}
04225e1d GJ	211
2c4f1ac5	212	ath79_add_sys_clkdev("ref", ref_rate);
6451af02 AB	213	clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
	214	clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
	215	clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
6612a688	216
2c4f1ac5 GJ	217	clk_add_alias("wdt", NULL, "ahb", NULL);
2c4f1ac5 GJ	218	clk_add_alias("uart", NULL, "ref", NULL);
04225e1d GJ	219	}
04225e1d GJ	220
97541ccf GJ	221	static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
	222	u32 frac, u32 out_div)
	223	{
	224	u64 t;
	225	u32 ret;
	226
837f036c	227	t = ref;
97541ccf GJ	228	t *= nint;
	229	do_div(t, ref_div);
	230	ret = t;
	231
837f036c	232	t = ref;
97541ccf GJ	233	t *= nfrac;
	234	do_div(t, ref_div * frac);
	235	ret += t;
	236
	237	ret /= (1 << out_div);
	238	return ret;
	239	}
	240
8889612b GJ	241	static void __init ar934x_clocks_init(void)
8889612b GJ	242	{
6612a688 GJ	243	unsigned long ref_rate;
	244	unsigned long cpu_rate;
	245	unsigned long ddr_rate;
	246	unsigned long ahb_rate;
97541ccf	247	u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
8889612b GJ	248	u32 cpu_pll, ddr_pll;
8889612b GJ	249	u32 bootstrap;
97541ccf GJ	250	void __iomem *dpll_base;
	251
	252	dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE);
8889612b GJ	253
8889612b GJ	254	bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
70342287	255	if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
6612a688	256	ref_rate = 40 * 1000 * 1000;
8889612b	257	else
6612a688	258	ref_rate = 25 * 1000 * 1000;
8889612b	259
97541ccf GJ	260	pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
	261	if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
	262	out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
	263	AR934X_SRIF_DPLL2_OUTDIV_MASK;
	264	pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG);
	265	nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
	266	AR934X_SRIF_DPLL1_NINT_MASK;
	267	nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
	268	ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
	269	AR934X_SRIF_DPLL1_REFDIV_MASK;
	270	frac = 1 << 18;
	271	} else {
	272	pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
	273	out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
	274	AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
	275	ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
	276	AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
	277	nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
	278	AR934X_PLL_CPU_CONFIG_NINT_MASK;
	279	nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
	280	AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
	281	frac = 1 << 6;
	282	}
	283
6612a688	284	cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
97541ccf GJ	285	nfrac, frac, out_div);
	286
	287	pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);
	288	if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
	289	out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
	290	AR934X_SRIF_DPLL2_OUTDIV_MASK;
	291	pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG);
	292	nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
	293	AR934X_SRIF_DPLL1_NINT_MASK;
	294	nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
	295	ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
	296	AR934X_SRIF_DPLL1_REFDIV_MASK;
	297	frac = 1 << 18;
	298	} else {
	299	pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
	300	out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
	301	AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
	302	ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
	303	AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
	304	nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
	305	AR934X_PLL_DDR_CONFIG_NINT_MASK;
	306	nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
	307	AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
	308	frac = 1 << 10;
	309	}
	310
6612a688	311	ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
97541ccf	312	nfrac, frac, out_div);
8889612b GJ	313
	314	clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
	315
	316	postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
	317	AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
	318
	319	if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
6612a688	320	cpu_rate = ref_rate;
8889612b	321	else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
6612a688	322	cpu_rate = cpu_pll / (postdiv + 1);
8889612b	323	else
6612a688	324	cpu_rate = ddr_pll / (postdiv + 1);
8889612b GJ	325
	326	postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
	327	AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
	328
	329	if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
6612a688	330	ddr_rate = ref_rate;
8889612b	331	else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
6612a688	332	ddr_rate = ddr_pll / (postdiv + 1);
8889612b	333	else
6612a688	334	ddr_rate = cpu_pll / (postdiv + 1);
8889612b GJ	335
	336	postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
	337	AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
	338
	339	if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
6612a688	340	ahb_rate = ref_rate;
8889612b	341	else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
6612a688	342	ahb_rate = ddr_pll / (postdiv + 1);
8889612b	343	else
6612a688 GJ	344	ahb_rate = cpu_pll / (postdiv + 1);
6612a688 GJ	345
2c4f1ac5	346	ath79_add_sys_clkdev("ref", ref_rate);
6451af02 AB	347	clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
	348	clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
	349	clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
8889612b	350
2c4f1ac5 GJ	351	clk_add_alias("wdt", NULL, "ref", NULL);
2c4f1ac5 GJ	352	clk_add_alias("uart", NULL, "ref", NULL);
97541ccf GJ	353
97541ccf GJ	354	iounmap(dpll_base);
8889612b GJ	355	}
8889612b GJ	356
41583c05 GJ	357	static void __init qca955x_clocks_init(void)
41583c05 GJ	358	{
6612a688 GJ	359	unsigned long ref_rate;
	360	unsigned long cpu_rate;
	361	unsigned long ddr_rate;
	362	unsigned long ahb_rate;
41583c05 GJ	363	u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
	364	u32 cpu_pll, ddr_pll;
	365	u32 bootstrap;
	366
	367	bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
	368	if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40)
6612a688	369	ref_rate = 40 * 1000 * 1000;
41583c05	370	else
6612a688	371	ref_rate = 25 * 1000 * 1000;
41583c05 GJ	372
	373	pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
	374	out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
	375	QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
	376	ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
	377	QCA955X_PLL_CPU_CONFIG_REFDIV_MASK;
	378	nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
	379	QCA955X_PLL_CPU_CONFIG_NINT_MASK;
	380	frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
	381	QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
	382
6612a688 GJ	383	cpu_pll = nint * ref_rate / ref_div;
6612a688 GJ	384	cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
41583c05 GJ	385	cpu_pll /= (1 << out_div);
	386
	387	pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
	388	out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
	389	QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
	390	ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
	391	QCA955X_PLL_DDR_CONFIG_REFDIV_MASK;
	392	nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
	393	QCA955X_PLL_DDR_CONFIG_NINT_MASK;
	394	frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
	395	QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
	396
6612a688 GJ	397	ddr_pll = nint * ref_rate / ref_div;
6612a688 GJ	398	ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
41583c05 GJ	399	ddr_pll /= (1 << out_div);
	400
	401	clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
	402
	403	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
	404	QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
	405
	406	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
6612a688	407	cpu_rate = ref_rate;
41583c05	408	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
6612a688	409	cpu_rate = ddr_pll / (postdiv + 1);
41583c05	410	else
6612a688	411	cpu_rate = cpu_pll / (postdiv + 1);
41583c05 GJ	412
	413	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
	414	QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
	415
	416	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
6612a688	417	ddr_rate = ref_rate;
41583c05	418	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
6612a688	419	ddr_rate = cpu_pll / (postdiv + 1);
41583c05	420	else
6612a688	421	ddr_rate = ddr_pll / (postdiv + 1);
41583c05 GJ	422
	423	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
	424	QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
	425
	426	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
6612a688	427	ahb_rate = ref_rate;
41583c05	428	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
6612a688	429	ahb_rate = ddr_pll / (postdiv + 1);
41583c05	430	else
6612a688 GJ	431	ahb_rate = cpu_pll / (postdiv + 1);
6612a688 GJ	432
2c4f1ac5	433	ath79_add_sys_clkdev("ref", ref_rate);
6451af02 AB	434	clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
	435	clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
	436	clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
41583c05	437
2c4f1ac5 GJ	438	clk_add_alias("wdt", NULL, "ref", NULL);
2c4f1ac5 GJ	439	clk_add_alias("uart", NULL, "ref", NULL);
41583c05 GJ	440	}
41583c05 GJ	441
d4a67d9d GJ	442	void __init ath79_clocks_init(void)
	443	{
	444	if (soc_is_ar71xx())
	445	ar71xx_clocks_init();
	446	else if (soc_is_ar724x())
	447	ar724x_clocks_init();
	448	else if (soc_is_ar913x())
	449	ar913x_clocks_init();
04225e1d GJ	450	else if (soc_is_ar933x())
04225e1d GJ	451	ar933x_clocks_init();
8889612b GJ	452	else if (soc_is_ar934x())
8889612b GJ	453	ar934x_clocks_init();
41583c05 GJ	454	else if (soc_is_qca955x())
41583c05 GJ	455	qca955x_clocks_init();
d4a67d9d GJ	456	else
d4a67d9d GJ	457	BUG();
6451af02 AB	458
6451af02 AB	459	of_clk_init(NULL);
d4a67d9d GJ	460	}
d4a67d9d GJ	461
23107802 GJ	462	unsigned long __init
	463	ath79_get_sys_clk_rate(const char *id)
	464	{
	465	struct clk *clk;
	466	unsigned long rate;
	467
	468	clk = clk_get(NULL, id);
	469	if (IS_ERR(clk))
	470	panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk));
	471
	472	rate = clk_get_rate(clk);
	473	clk_put(clk);
	474
	475	return rate;
	476	}
6451af02 AB	477
	478	#ifdef CONFIG_OF
	479	static void __init ath79_clocks_init_dt(struct device_node *np)
	480	{
	481	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
	482	}
	483
	484	CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt);
	485	CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt);
	486	CLK_OF_DECLARE(ar9130, "qca,ar9130-pll", ath79_clocks_init_dt);
	487	CLK_OF_DECLARE(ar9330, "qca,ar9330-pll", ath79_clocks_init_dt);
	488	CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt);
	489	CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt);
	490	#endif