[mirror_ubuntu-focal-kernel.git] / arch / mips / ath79 / clock.c

/*
 *  Atheros AR71XX/AR724X/AR913X common routines
 *
 *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
 *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
 *
 *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License version 2 as published
 *  by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <dt-bindings/clock/ath79-clk.h>

#include <asm/div64.h>

#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include "common.h"
#include "machtypes.h"

#define AR71XX_BASE_FREQ	40000000
#define AR724X_BASE_FREQ	40000000

static struct clk *clks[ATH79_CLK_END];
static struct clk_onecell_data clk_data = {
	.clks = clks,
	.clk_num = ARRAY_SIZE(clks),
};

static struct clk *__init ath79_add_sys_clkdev(
	const char *id, unsigned long rate)
{
	struct clk *clk;
	int err;

	clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate);
	if (IS_ERR(clk))
		panic("failed to allocate %s clock structure", id);

	err = clk_register_clkdev(clk, id, NULL);
	if (err)
		panic("unable to register %s clock device", id);

	return clk;
}

static void __init ar71xx_clocks_init(void)
{
	unsigned long ref_rate;
	unsigned long cpu_rate;
	unsigned long ddr_rate;
	unsigned long ahb_rate;
	u32 pll;
	u32 freq;
	u32 div;

	ref_rate = AR71XX_BASE_FREQ;

	pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);

	div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;
	freq = div * ref_rate;

	div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
	cpu_rate = freq / div;

	div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
	ddr_rate = freq / div;

	div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
	ahb_rate = cpu_rate / div;

	ath79_add_sys_clkdev("ref", ref_rate);
	clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
	clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
	clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);

	clk_add_alias("wdt", NULL, "ahb", NULL);
	clk_add_alias("uart", NULL, "ahb", NULL);
}

static struct clk * __init ath79_reg_ffclk(const char *name,
		const char *parent_name, unsigned int mult, unsigned int div)
{
	struct clk *clk;

	clk = clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
	if (IS_ERR(clk))
		panic("failed to allocate %s clock structure", name);

	return clk;
}

static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
{
	u32 pll;
	u32 mult, div, ddr_div, ahb_div;

	pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG);

	mult = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);
	div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2;

	ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
	ahb_div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;

	clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref", mult, div);
	clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref", mult, div * ddr_div);
	clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref", mult, div * ahb_div);
}

static void __init ar724x_clocks_init(void)
{
	struct clk *ref_clk;

	ref_clk = ath79_add_sys_clkdev("ref", AR724X_BASE_FREQ);

	ar724x_clk_init(ref_clk, ath79_pll_base);

	/* just make happy plat_time_init() from arch/mips/ath79/setup.c */
	clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
	clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
	clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);

	clk_add_alias("wdt", NULL, "ahb", NULL);
	clk_add_alias("uart", NULL, "ahb", NULL);
}

static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
{
	u32 clock_ctrl;
	u32 ref_div;
	u32 ninit_mul;
	u32 out_div;

	u32 cpu_div;
	u32 ddr_div;
	u32 ahb_div;

	clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG);
	if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
		ref_div = 1;
		ninit_mul = 1;
		out_div = 1;

		cpu_div = 1;
		ddr_div = 1;
		ahb_div = 1;
	} else {
		u32 cpu_config;
		u32 t;

		cpu_config = __raw_readl(pll_base + AR933X_PLL_CPU_CONFIG_REG);

		t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
		    AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
		ref_div = t;

		ninit_mul = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
		    AR933X_PLL_CPU_CONFIG_NINT_MASK;

		t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
		    AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
		if (t == 0)
			t = 1;

		out_div = (1 << t);

		cpu_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
		     AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;

		ddr_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
		      AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;

		ahb_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
		     AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
	}

	clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref",
					ninit_mul, ref_div * out_div * cpu_div);
	clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref",
					ninit_mul, ref_div * out_div * ddr_div);
	clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref",
					ninit_mul, ref_div * out_div * ahb_div);
}

static void __init ar933x_clocks_init(void)
{
	struct clk *ref_clk;
	unsigned long ref_rate;
	u32 t;

	t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
	if (t & AR933X_BOOTSTRAP_REF_CLK_40)
		ref_rate = (40 * 1000 * 1000);
	else
		ref_rate = (25 * 1000 * 1000);

	ref_clk = ath79_add_sys_clkdev("ref", ref_rate);

	ar9330_clk_init(ref_clk, ath79_pll_base);

	/* just make happy plat_time_init() from arch/mips/ath79/setup.c */
	clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
	clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
	clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);

	clk_add_alias("wdt", NULL, "ahb", NULL);
	clk_add_alias("uart", NULL, "ref", NULL);
}

static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
				      u32 frac, u32 out_div)
{
	u64 t;
	u32 ret;

	t = ref;
	t *= nint;
	do_div(t, ref_div);
	ret = t;

	t = ref;
	t *= nfrac;
	do_div(t, ref_div * frac);
	ret += t;

	ret /= (1 << out_div);
	return ret;
}

static void __init ar934x_clocks_init(void)
{
	unsigned long ref_rate;
	unsigned long cpu_rate;
	unsigned long ddr_rate;
	unsigned long ahb_rate;
	u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
	u32 cpu_pll, ddr_pll;
	u32 bootstrap;
	void __iomem *dpll_base;

	dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE);

	bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
	if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
		ref_rate = 40 * 1000 * 1000;
	else
		ref_rate = 25 * 1000 * 1000;

	pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
	if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
		out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
			  AR934X_SRIF_DPLL2_OUTDIV_MASK;
		pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG);
		nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
		       AR934X_SRIF_DPLL1_NINT_MASK;
		nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
		ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
			  AR934X_SRIF_DPLL1_REFDIV_MASK;
		frac = 1 << 18;
	} else {
		pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
		out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
			AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
		ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
			  AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
		nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
		       AR934X_PLL_CPU_CONFIG_NINT_MASK;
		nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
			AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
		frac = 1 << 6;
	}

	cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
				      nfrac, frac, out_div);

	pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);
	if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
		out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
			  AR934X_SRIF_DPLL2_OUTDIV_MASK;
		pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG);
		nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
		       AR934X_SRIF_DPLL1_NINT_MASK;
		nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
		ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
			  AR934X_SRIF_DPLL1_REFDIV_MASK;
		frac = 1 << 18;
	} else {
		pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
		out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
			  AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
		ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
			   AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
		nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
		       AR934X_PLL_DDR_CONFIG_NINT_MASK;
		nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
			AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
		frac = 1 << 10;
	}

	ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
				      nfrac, frac, out_div);

	clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);

	postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
		  AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;

	if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
		cpu_rate = ref_rate;
	else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
		cpu_rate = cpu_pll / (postdiv + 1);
	else
		cpu_rate = ddr_pll / (postdiv + 1);

	postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
		  AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;

	if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
		ddr_rate = ref_rate;
	else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
		ddr_rate = ddr_pll / (postdiv + 1);
	else
		ddr_rate = cpu_pll / (postdiv + 1);

	postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
		  AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;

	if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
		ahb_rate = ref_rate;
	else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
		ahb_rate = ddr_pll / (postdiv + 1);
	else
		ahb_rate = cpu_pll / (postdiv + 1);

	ath79_add_sys_clkdev("ref", ref_rate);
	clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
	clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
	clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);

	clk_add_alias("wdt", NULL, "ref", NULL);
	clk_add_alias("uart", NULL, "ref", NULL);

	iounmap(dpll_base);
}

static void __init qca955x_clocks_init(void)
{
	unsigned long ref_rate;
	unsigned long cpu_rate;
	unsigned long ddr_rate;
	unsigned long ahb_rate;
	u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
	u32 cpu_pll, ddr_pll;
	u32 bootstrap;

	bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
	if (bootstrap &	QCA955X_BOOTSTRAP_REF_CLK_40)
		ref_rate = 40 * 1000 * 1000;
	else
		ref_rate = 25 * 1000 * 1000;

	pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
	out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
		  QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
	ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
		  QCA955X_PLL_CPU_CONFIG_REFDIV_MASK;
	nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
	       QCA955X_PLL_CPU_CONFIG_NINT_MASK;
	frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
	       QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;

	cpu_pll = nint * ref_rate / ref_div;
	cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
	cpu_pll /= (1 << out_div);

	pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
	out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
		  QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
	ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
		  QCA955X_PLL_DDR_CONFIG_REFDIV_MASK;
	nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
	       QCA955X_PLL_DDR_CONFIG_NINT_MASK;
	frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
	       QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;

	ddr_pll = nint * ref_rate / ref_div;
	ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
	ddr_pll /= (1 << out_div);

	clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);

	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
		  QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;

	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
		cpu_rate = ref_rate;
	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
		cpu_rate = ddr_pll / (postdiv + 1);
	else
		cpu_rate = cpu_pll / (postdiv + 1);

	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
		  QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;

	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
		ddr_rate = ref_rate;
	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
		ddr_rate = cpu_pll / (postdiv + 1);
	else
		ddr_rate = ddr_pll / (postdiv + 1);

	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
		  QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;

	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
		ahb_rate = ref_rate;
	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
		ahb_rate = ddr_pll / (postdiv + 1);
	else
		ahb_rate = cpu_pll / (postdiv + 1);

	ath79_add_sys_clkdev("ref", ref_rate);
	clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
	clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
	clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);

	clk_add_alias("wdt", NULL, "ref", NULL);
	clk_add_alias("uart", NULL, "ref", NULL);
}

void __init ath79_clocks_init(void)
{
	if (soc_is_ar71xx())
		ar71xx_clocks_init();
	else if (soc_is_ar724x() || soc_is_ar913x())
		ar724x_clocks_init();
	else if (soc_is_ar933x())
		ar933x_clocks_init();
	else if (soc_is_ar934x())
		ar934x_clocks_init();
	else if (soc_is_qca955x())
		qca955x_clocks_init();
	else
		BUG();
}

unsigned long __init
ath79_get_sys_clk_rate(const char *id)
{
	struct clk *clk;
	unsigned long rate;

	clk = clk_get(NULL, id);
	if (IS_ERR(clk))
		panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk));

	rate = clk_get_rate(clk);
	clk_put(clk);

	return rate;
}

#ifdef CONFIG_OF
static void __init ath79_clocks_init_dt(struct device_node *np)
{
	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
}

CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt);
CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt);
CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt);
CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt);

static void __init ath79_clocks_init_dt_ng(struct device_node *np)
{
	struct clk *ref_clk;
	void __iomem *pll_base;

	ref_clk = of_clk_get(np, 0);
	if (IS_ERR(ref_clk)) {
		pr_err("%pOF: of_clk_get failed\n", np);
		goto err;
	}

	pll_base = of_iomap(np, 0);
	if (!pll_base) {
		pr_err("%pOF: can't map pll registers\n", np);
		goto err_clk;
	}

	if (of_device_is_compatible(np, "qca,ar9130-pll"))
		ar724x_clk_init(ref_clk, pll_base);
	else if (of_device_is_compatible(np, "qca,ar9330-pll"))
		ar9330_clk_init(ref_clk, pll_base);
	else {
		pr_err("%pOF: could not find any appropriate clk_init()\n", np);
		goto err_iounmap;
	}

	if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
		pr_err("%pOF: could not register clk provider\n", np);
		goto err_iounmap;
	}

	return;

err_iounmap:
	iounmap(pll_base);

err_clk:
	clk_put(ref_clk);

err:
	return;
}
CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng);
CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt_ng);
#endif
Commit	Line	Data
d4a67d9d GJ	1	/*
	2	* Atheros AR71XX/AR724X/AR913X common routines
	3	*
8889612b	4	* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
d4a67d9d GJ	5	* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
d4a67d9d GJ	6	*
8889612b GJ	7	* Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
8889612b GJ	8	*
d4a67d9d GJ	9	* This program is free software; you can redistribute it and/or modify it
	10	* under the terms of the GNU General Public License version 2 as published
	11	* by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/kernel.h>
d4a67d9d GJ	15	#include <linux/init.h>
	16	#include <linux/err.h>
	17	#include <linux/clk.h>
2c4f1ac5	18	#include <linux/clkdev.h>
411520af	19	#include <linux/clk-provider.h>
3bdf1071 AP	20	#include <linux/of.h>
3bdf1071 AP	21	#include <linux/of_address.h>
af5ad0de	22	#include <dt-bindings/clock/ath79-clk.h>
d4a67d9d	23
97541ccf GJ	24	#include <asm/div64.h>
97541ccf GJ	25
d4a67d9d GJ	26	#include <asm/mach-ath79/ath79.h>
	27	#include <asm/mach-ath79/ar71xx_regs.h>
	28	#include "common.h"
3bdf1071	29	#include "machtypes.h"
d4a67d9d GJ	30
d4a67d9d GJ	31	#define AR71XX_BASE_FREQ 40000000
c338d59d	32	#define AR724X_BASE_FREQ 40000000
d4a67d9d	33
af5ad0de	34	static struct clk *clks[ATH79_CLK_END];
6451af02 AB	35	static struct clk_onecell_data clk_data = {
	36	.clks = clks,
	37	.clk_num = ARRAY_SIZE(clks),
	38	};
	39
	40	static struct clk *__init ath79_add_sys_clkdev(
	41	const char *id, unsigned long rate)
2c4f1ac5 GJ	42	{
	43	struct clk *clk;
	44	int err;
	45
9c938a0d	46	clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate);
20d6f0c3	47	if (IS_ERR(clk))
2c4f1ac5 GJ	48	panic("failed to allocate %s clock structure", id);
2c4f1ac5 GJ	49
2c4f1ac5 GJ	50	err = clk_register_clkdev(clk, id, NULL);
	51	if (err)
	52	panic("unable to register %s clock device", id);
6451af02 AB	53
6451af02 AB	54	return clk;
2c4f1ac5	55	}
d4a67d9d GJ	56
	57	static void __init ar71xx_clocks_init(void)
	58	{
6612a688 GJ	59	unsigned long ref_rate;
	60	unsigned long cpu_rate;
	61	unsigned long ddr_rate;
	62	unsigned long ahb_rate;
d4a67d9d GJ	63	u32 pll;
	64	u32 freq;
	65	u32 div;
	66
6612a688	67	ref_rate = AR71XX_BASE_FREQ;
d4a67d9d GJ	68
	69	pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
	70
626a0695	71	div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;
6612a688	72	freq = div * ref_rate;
d4a67d9d GJ	73
d4a67d9d GJ	74	div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
6612a688	75	cpu_rate = freq / div;
d4a67d9d GJ	76
d4a67d9d GJ	77	div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
6612a688	78	ddr_rate = freq / div;
d4a67d9d GJ	79
d4a67d9d GJ	80	div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
6612a688 GJ	81	ahb_rate = cpu_rate / div;
6612a688 GJ	82
2c4f1ac5	83	ath79_add_sys_clkdev("ref", ref_rate);
af5ad0de AP	84	clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
	85	clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
	86	clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
d4a67d9d	87
2c4f1ac5 GJ	88	clk_add_alias("wdt", NULL, "ahb", NULL);
2c4f1ac5 GJ	89	clk_add_alias("uart", NULL, "ahb", NULL);
d4a67d9d GJ	90	}
d4a67d9d GJ	91
3bdf1071 AP	92	static struct clk * __init ath79_reg_ffclk(const char *name,
3bdf1071 AP	93	const char *parent_name, unsigned int mult, unsigned int div)
d4a67d9d	94	{
3bdf1071	95	struct clk *clk;
d4a67d9d	96
3bdf1071	97	clk = clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
e3b23148	98	if (IS_ERR(clk))
3bdf1071	99	panic("failed to allocate %s clock structure", name);
d4a67d9d	100
3bdf1071 AP	101	return clk;
	102	}
	103
	104	static void __init ar724x_clk_init(struct clk ref_clk, void __iomem pll_base)
	105	{
	106	u32 pll;
	107	u32 mult, div, ddr_div, ahb_div;
d4a67d9d	108
3bdf1071 AP	109	pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG);
	110
	111	mult = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);
c338d59d	112	div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2;
d4a67d9d	113
3bdf1071 AP	114	ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
3bdf1071 AP	115	ahb_div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
d4a67d9d	116
3bdf1071 AP	117	clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref", mult, div);
	118	clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref", mult, div * ddr_div);
	119	clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref", mult, div * ahb_div);
	120	}
d4a67d9d	121
3bdf1071 AP	122	static void __init ar724x_clocks_init(void)
	123	{
	124	struct clk *ref_clk;
6612a688	125
3bdf1071 AP	126	ref_clk = ath79_add_sys_clkdev("ref", AR724X_BASE_FREQ);
	127
	128	ar724x_clk_init(ref_clk, ath79_pll_base);
	129
	130	/* just make happy plat_time_init() from arch/mips/ath79/setup.c */
	131	clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
	132	clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
	133	clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);
d4a67d9d	134
2c4f1ac5 GJ	135	clk_add_alias("wdt", NULL, "ahb", NULL);
2c4f1ac5 GJ	136	clk_add_alias("uart", NULL, "ahb", NULL);
d4a67d9d GJ	137	}
d4a67d9d GJ	138
5ae5c452	139	static void __init ar9330_clk_init(struct clk ref_clk, void __iomem pll_base)
04225e1d GJ	140	{
04225e1d GJ	141	u32 clock_ctrl;
5ae5c452 AP	142	u32 ref_div;
	143	u32 ninit_mul;
	144	u32 out_div;
04225e1d	145
5ae5c452 AP	146	u32 cpu_div;
	147	u32 ddr_div;
	148	u32 ahb_div;
04225e1d	149
5ae5c452	150	clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG);
04225e1d	151	if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
5ae5c452 AP	152	ref_div = 1;
	153	ninit_mul = 1;
	154	out_div = 1;
	155
	156	cpu_div = 1;
	157	ddr_div = 1;
	158	ahb_div = 1;
04225e1d	159	} else {
5ae5c452 AP	160	u32 cpu_config;
	161	u32 t;
	162
	163	cpu_config = __raw_readl(pll_base + AR933X_PLL_CPU_CONFIG_REG);
04225e1d GJ	164
	165	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
	166	AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
5ae5c452	167	ref_div = t;
04225e1d	168
5ae5c452	169	ninit_mul = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
04225e1d	170	AR933X_PLL_CPU_CONFIG_NINT_MASK;
04225e1d GJ	171
	172	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
	173	AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
	174	if (t == 0)
	175	t = 1;
	176
5ae5c452	177	out_div = (1 << t);
04225e1d	178
5ae5c452	179	cpu_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
04225e1d	180	AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
04225e1d	181
5ae5c452	182	ddr_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
04225e1d	183	AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
04225e1d	184
5ae5c452	185	ahb_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
04225e1d	186	AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
04225e1d GJ	187	}
04225e1d GJ	188
5ae5c452 AP	189	clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref",
	190	ninit_mul, ref_div * out_div * cpu_div);
	191	clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref",
	192	ninit_mul, ref_div * out_div * ddr_div);
	193	clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref",
	194	ninit_mul, ref_div * out_div * ahb_div);
	195	}
	196
	197	static void __init ar933x_clocks_init(void)
	198	{
	199	struct clk *ref_clk;
	200	unsigned long ref_rate;
	201	u32 t;
	202
	203	t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
	204	if (t & AR933X_BOOTSTRAP_REF_CLK_40)
	205	ref_rate = (40 * 1000 * 1000);
	206	else
	207	ref_rate = (25 * 1000 * 1000);
	208
	209	ref_clk = ath79_add_sys_clkdev("ref", ref_rate);
	210
	211	ar9330_clk_init(ref_clk, ath79_pll_base);
	212
	213	/* just make happy plat_time_init() from arch/mips/ath79/setup.c */
	214	clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
	215	clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
	216	clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);
6612a688	217
2c4f1ac5 GJ	218	clk_add_alias("wdt", NULL, "ahb", NULL);
2c4f1ac5 GJ	219	clk_add_alias("uart", NULL, "ref", NULL);
04225e1d GJ	220	}
04225e1d GJ	221
97541ccf GJ	222	static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
	223	u32 frac, u32 out_div)
	224	{
	225	u64 t;
	226	u32 ret;
	227
837f036c	228	t = ref;
97541ccf GJ	229	t *= nint;
	230	do_div(t, ref_div);
	231	ret = t;
	232
837f036c	233	t = ref;
97541ccf GJ	234	t *= nfrac;
	235	do_div(t, ref_div * frac);
	236	ret += t;
	237
	238	ret /= (1 << out_div);
	239	return ret;
	240	}
	241
8889612b GJ	242	static void __init ar934x_clocks_init(void)
8889612b GJ	243	{
6612a688 GJ	244	unsigned long ref_rate;
	245	unsigned long cpu_rate;
	246	unsigned long ddr_rate;
	247	unsigned long ahb_rate;
97541ccf	248	u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
8889612b GJ	249	u32 cpu_pll, ddr_pll;
8889612b GJ	250	u32 bootstrap;
97541ccf GJ	251	void __iomem *dpll_base;
	252
	253	dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE);
8889612b GJ	254
8889612b GJ	255	bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
70342287	256	if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
6612a688	257	ref_rate = 40 * 1000 * 1000;
8889612b	258	else
6612a688	259	ref_rate = 25 * 1000 * 1000;
8889612b	260
97541ccf GJ	261	pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
	262	if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
	263	out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
	264	AR934X_SRIF_DPLL2_OUTDIV_MASK;
	265	pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG);
	266	nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
	267	AR934X_SRIF_DPLL1_NINT_MASK;
	268	nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
	269	ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
	270	AR934X_SRIF_DPLL1_REFDIV_MASK;
	271	frac = 1 << 18;
	272	} else {
	273	pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
	274	out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
	275	AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
	276	ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
	277	AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
	278	nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
	279	AR934X_PLL_CPU_CONFIG_NINT_MASK;
	280	nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
	281	AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
	282	frac = 1 << 6;
	283	}
	284
6612a688	285	cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
97541ccf GJ	286	nfrac, frac, out_div);
	287
	288	pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);
	289	if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
	290	out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
	291	AR934X_SRIF_DPLL2_OUTDIV_MASK;
	292	pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG);
	293	nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
	294	AR934X_SRIF_DPLL1_NINT_MASK;
	295	nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
	296	ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
	297	AR934X_SRIF_DPLL1_REFDIV_MASK;
	298	frac = 1 << 18;
	299	} else {
	300	pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
	301	out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
	302	AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
	303	ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
	304	AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
	305	nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
	306	AR934X_PLL_DDR_CONFIG_NINT_MASK;
	307	nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
	308	AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
	309	frac = 1 << 10;
	310	}
	311
6612a688	312	ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
97541ccf	313	nfrac, frac, out_div);
8889612b GJ	314
	315	clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
	316
	317	postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
	318	AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
	319
	320	if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
6612a688	321	cpu_rate = ref_rate;
8889612b	322	else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
6612a688	323	cpu_rate = cpu_pll / (postdiv + 1);
8889612b	324	else
6612a688	325	cpu_rate = ddr_pll / (postdiv + 1);
8889612b GJ	326
	327	postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
	328	AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
	329
	330	if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
6612a688	331	ddr_rate = ref_rate;
8889612b	332	else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
6612a688	333	ddr_rate = ddr_pll / (postdiv + 1);
8889612b	334	else
6612a688	335	ddr_rate = cpu_pll / (postdiv + 1);
8889612b GJ	336
	337	postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
	338	AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
	339
	340	if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
6612a688	341	ahb_rate = ref_rate;
8889612b	342	else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
6612a688	343	ahb_rate = ddr_pll / (postdiv + 1);
8889612b	344	else
6612a688 GJ	345	ahb_rate = cpu_pll / (postdiv + 1);
6612a688 GJ	346
2c4f1ac5	347	ath79_add_sys_clkdev("ref", ref_rate);
af5ad0de AP	348	clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
	349	clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
	350	clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
8889612b	351
2c4f1ac5 GJ	352	clk_add_alias("wdt", NULL, "ref", NULL);
2c4f1ac5 GJ	353	clk_add_alias("uart", NULL, "ref", NULL);
97541ccf GJ	354
97541ccf GJ	355	iounmap(dpll_base);
8889612b GJ	356	}
8889612b GJ	357
41583c05 GJ	358	static void __init qca955x_clocks_init(void)
41583c05 GJ	359	{
6612a688 GJ	360	unsigned long ref_rate;
	361	unsigned long cpu_rate;
	362	unsigned long ddr_rate;
	363	unsigned long ahb_rate;
41583c05 GJ	364	u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
	365	u32 cpu_pll, ddr_pll;
	366	u32 bootstrap;
	367
	368	bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
	369	if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40)
6612a688	370	ref_rate = 40 * 1000 * 1000;
41583c05	371	else
6612a688	372	ref_rate = 25 * 1000 * 1000;
41583c05 GJ	373
	374	pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
	375	out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
	376	QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
	377	ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
	378	QCA955X_PLL_CPU_CONFIG_REFDIV_MASK;
	379	nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
	380	QCA955X_PLL_CPU_CONFIG_NINT_MASK;
	381	frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
	382	QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
	383
6612a688 GJ	384	cpu_pll = nint * ref_rate / ref_div;
6612a688 GJ	385	cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
41583c05 GJ	386	cpu_pll /= (1 << out_div);
	387
	388	pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
	389	out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
	390	QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
	391	ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
	392	QCA955X_PLL_DDR_CONFIG_REFDIV_MASK;
	393	nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
	394	QCA955X_PLL_DDR_CONFIG_NINT_MASK;
	395	frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
	396	QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
	397
6612a688 GJ	398	ddr_pll = nint * ref_rate / ref_div;
6612a688 GJ	399	ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
41583c05 GJ	400	ddr_pll /= (1 << out_div);
	401
	402	clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
	403
	404	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
	405	QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
	406
	407	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
6612a688	408	cpu_rate = ref_rate;
41583c05	409	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
6612a688	410	cpu_rate = ddr_pll / (postdiv + 1);
41583c05	411	else
6612a688	412	cpu_rate = cpu_pll / (postdiv + 1);
41583c05 GJ	413
	414	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
	415	QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
	416
	417	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
6612a688	418	ddr_rate = ref_rate;
41583c05	419	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
6612a688	420	ddr_rate = cpu_pll / (postdiv + 1);
41583c05	421	else
6612a688	422	ddr_rate = ddr_pll / (postdiv + 1);
41583c05 GJ	423
	424	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
	425	QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
	426
	427	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
6612a688	428	ahb_rate = ref_rate;
41583c05	429	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
6612a688	430	ahb_rate = ddr_pll / (postdiv + 1);
41583c05	431	else
6612a688 GJ	432	ahb_rate = cpu_pll / (postdiv + 1);
6612a688 GJ	433
2c4f1ac5	434	ath79_add_sys_clkdev("ref", ref_rate);
af5ad0de AP	435	clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
	436	clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
	437	clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
41583c05	438
2c4f1ac5 GJ	439	clk_add_alias("wdt", NULL, "ref", NULL);
2c4f1ac5 GJ	440	clk_add_alias("uart", NULL, "ref", NULL);
41583c05 GJ	441	}
41583c05 GJ	442
d4a67d9d GJ	443	void __init ath79_clocks_init(void)
	444	{
	445	if (soc_is_ar71xx())
	446	ar71xx_clocks_init();
f4c87b7a	447	else if (soc_is_ar724x() \|\| soc_is_ar913x())
d4a67d9d	448	ar724x_clocks_init();
04225e1d GJ	449	else if (soc_is_ar933x())
04225e1d GJ	450	ar933x_clocks_init();
8889612b GJ	451	else if (soc_is_ar934x())
8889612b GJ	452	ar934x_clocks_init();
41583c05 GJ	453	else if (soc_is_qca955x())
41583c05 GJ	454	qca955x_clocks_init();
d4a67d9d GJ	455	else
d4a67d9d GJ	456	BUG();
d4a67d9d GJ	457	}
d4a67d9d GJ	458
23107802 GJ	459	unsigned long __init
	460	ath79_get_sys_clk_rate(const char *id)
	461	{
	462	struct clk *clk;
	463	unsigned long rate;
	464
	465	clk = clk_get(NULL, id);
	466	if (IS_ERR(clk))
	467	panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk));
	468
	469	rate = clk_get_rate(clk);
	470	clk_put(clk);
	471
	472	return rate;
	473	}
6451af02 AB	474
	475	#ifdef CONFIG_OF
	476	static void __init ath79_clocks_init_dt(struct device_node *np)
	477	{
	478	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
	479	}
	480
	481	CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt);
	482	CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt);
6451af02 AB	483	CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt);
6451af02 AB	484	CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt);
3bdf1071 AP	485
	486	static void __init ath79_clocks_init_dt_ng(struct device_node *np)
	487	{
	488	struct clk *ref_clk;
	489	void __iomem *pll_base;
3bdf1071 AP	490
	491	ref_clk = of_clk_get(np, 0);
	492	if (IS_ERR(ref_clk)) {
7f27b5b8	493	pr_err("%pOF: of_clk_get failed\n", np);
3bdf1071 AP	494	goto err;
	495	}
	496
	497	pll_base = of_iomap(np, 0);
	498	if (!pll_base) {
7f27b5b8	499	pr_err("%pOF: can't map pll registers\n", np);
3bdf1071 AP	500	goto err_clk;
	501	}
	502
5ae5c452 AP	503	if (of_device_is_compatible(np, "qca,ar9130-pll"))
	504	ar724x_clk_init(ref_clk, pll_base);
	505	else if (of_device_is_compatible(np, "qca,ar9330-pll"))
	506	ar9330_clk_init(ref_clk, pll_base);
	507	else {
7f27b5b8	508	pr_err("%pOF: could not find any appropriate clk_init()\n", np);
b3d91db3	509	goto err_iounmap;
5ae5c452	510	}
3bdf1071 AP	511
3bdf1071 AP	512	if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
7f27b5b8	513	pr_err("%pOF: could not register clk provider\n", np);
b3d91db3	514	goto err_iounmap;
3bdf1071 AP	515	}
	516
	517	return;
	518
b3d91db3 AY	519	err_iounmap:
	520	iounmap(pll_base);
	521
3bdf1071 AP	522	err_clk:
	523	clk_put(ref_clk);
	524
	525	err:
	526	return;
	527	}
	528	CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng);
5ae5c452	529	CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt_ng);
6451af02	530	#endif