[mirror_ubuntu-bionic-kernel.git] / arch / mips / ath79 / clock.c

/*
 *  Atheros AR71XX/AR724X/AR913X common routines
 *
 *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
 *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
 *
 *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License version 2 as published
 *  by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <dt-bindings/clock/ath79-clk.h>

#include <asm/div64.h>

#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include "common.h"
#include "machtypes.h"

#define AR71XX_BASE_FREQ	40000000
#define AR724X_BASE_FREQ	40000000

static struct clk *clks[ATH79_CLK_END];
static struct clk_onecell_data clk_data = {
	.clks = clks,
	.clk_num = ARRAY_SIZE(clks),
};

static struct clk *__init ath79_add_sys_clkdev(
	const char *id, unsigned long rate)
{
	struct clk *clk;
	int err;

	clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate);
	if (!clk)
		panic("failed to allocate %s clock structure", id);

	err = clk_register_clkdev(clk, id, NULL);
	if (err)
		panic("unable to register %s clock device", id);

	return clk;
}

static void __init ar71xx_clocks_init(void)
{
	unsigned long ref_rate;
	unsigned long cpu_rate;
	unsigned long ddr_rate;
	unsigned long ahb_rate;
	u32 pll;
	u32 freq;
	u32 div;

	ref_rate = AR71XX_BASE_FREQ;

	pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);

	div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;
	freq = div * ref_rate;

	div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
	cpu_rate = freq / div;

	div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
	ddr_rate = freq / div;

	div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
	ahb_rate = cpu_rate / div;

	ath79_add_sys_clkdev("ref", ref_rate);
	clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
	clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
	clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);

	clk_add_alias("wdt", NULL, "ahb", NULL);
	clk_add_alias("uart", NULL, "ahb", NULL);
}

static struct clk * __init ath79_reg_ffclk(const char *name,
		const char *parent_name, unsigned int mult, unsigned int div)
{
	struct clk *clk;

	clk = clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
	if (IS_ERR(clk))
		panic("failed to allocate %s clock structure", name);

	return clk;
}

static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
{
	u32 pll;
	u32 mult, div, ddr_div, ahb_div;

	pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG);

	mult = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);
	div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2;

	ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
	ahb_div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;

	clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref", mult, div);
	clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref", mult, div * ddr_div);
	clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref", mult, div * ahb_div);
}

static void __init ar724x_clocks_init(void)
{
	struct clk *ref_clk;

	ref_clk = ath79_add_sys_clkdev("ref", AR724X_BASE_FREQ);

	ar724x_clk_init(ref_clk, ath79_pll_base);

	/* just make happy plat_time_init() from arch/mips/ath79/setup.c */
	clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
	clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
	clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);

	clk_add_alias("wdt", NULL, "ahb", NULL);
	clk_add_alias("uart", NULL, "ahb", NULL);
}

static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
{
	u32 clock_ctrl;
	u32 ref_div;
	u32 ninit_mul;
	u32 out_div;

	u32 cpu_div;
	u32 ddr_div;
	u32 ahb_div;

	clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG);
	if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
		ref_div = 1;
		ninit_mul = 1;
		out_div = 1;

		cpu_div = 1;
		ddr_div = 1;
		ahb_div = 1;
	} else {
		u32 cpu_config;
		u32 t;

		cpu_config = __raw_readl(pll_base + AR933X_PLL_CPU_CONFIG_REG);

		t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
		    AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
		ref_div = t;

		ninit_mul = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
		    AR933X_PLL_CPU_CONFIG_NINT_MASK;

		t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
		    AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
		if (t == 0)
			t = 1;

		out_div = (1 << t);

		cpu_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
		     AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;

		ddr_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
		      AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;

		ahb_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
		     AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
	}

	clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref",
					ninit_mul, ref_div * out_div * cpu_div);
	clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref",
					ninit_mul, ref_div * out_div * ddr_div);
	clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref",
					ninit_mul, ref_div * out_div * ahb_div);
}

static void __init ar933x_clocks_init(void)
{
	struct clk *ref_clk;
	unsigned long ref_rate;
	u32 t;

	t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
	if (t & AR933X_BOOTSTRAP_REF_CLK_40)
		ref_rate = (40 * 1000 * 1000);
	else
		ref_rate = (25 * 1000 * 1000);

	ref_clk = ath79_add_sys_clkdev("ref", ref_rate);

	ar9330_clk_init(ref_clk, ath79_pll_base);

	/* just make happy plat_time_init() from arch/mips/ath79/setup.c */
	clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
	clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
	clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);

	clk_add_alias("wdt", NULL, "ahb", NULL);
	clk_add_alias("uart", NULL, "ref", NULL);
}

static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
				      u32 frac, u32 out_div)
{
	u64 t;
	u32 ret;

	t = ref;
	t *= nint;
	do_div(t, ref_div);
	ret = t;

	t = ref;
	t *= nfrac;
	do_div(t, ref_div * frac);
	ret += t;

	ret /= (1 << out_div);
	return ret;
}

static void __init ar934x_clocks_init(void)
{
	unsigned long ref_rate;
	unsigned long cpu_rate;
	unsigned long ddr_rate;
	unsigned long ahb_rate;
	u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
	u32 cpu_pll, ddr_pll;
	u32 bootstrap;
	void __iomem *dpll_base;

	dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE);

	bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
	if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
		ref_rate = 40 * 1000 * 1000;
	else
		ref_rate = 25 * 1000 * 1000;

	pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
	if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
		out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
			  AR934X_SRIF_DPLL2_OUTDIV_MASK;
		pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG);
		nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
		       AR934X_SRIF_DPLL1_NINT_MASK;
		nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
		ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
			  AR934X_SRIF_DPLL1_REFDIV_MASK;
		frac = 1 << 18;
	} else {
		pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
		out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
			AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
		ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
			  AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
		nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
		       AR934X_PLL_CPU_CONFIG_NINT_MASK;
		nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
			AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
		frac = 1 << 6;
	}

	cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
				      nfrac, frac, out_div);

	pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);
	if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
		out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
			  AR934X_SRIF_DPLL2_OUTDIV_MASK;
		pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG);
		nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
		       AR934X_SRIF_DPLL1_NINT_MASK;
		nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
		ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
			  AR934X_SRIF_DPLL1_REFDIV_MASK;
		frac = 1 << 18;
	} else {
		pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
		out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
			  AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
		ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
			   AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
		nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
		       AR934X_PLL_DDR_CONFIG_NINT_MASK;
		nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
			AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
		frac = 1 << 10;
	}

	ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
				      nfrac, frac, out_div);

	clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);

	postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
		  AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;

	if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
		cpu_rate = ref_rate;
	else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
		cpu_rate = cpu_pll / (postdiv + 1);
	else
		cpu_rate = ddr_pll / (postdiv + 1);

	postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
		  AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;

	if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
		ddr_rate = ref_rate;
	else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
		ddr_rate = ddr_pll / (postdiv + 1);
	else
		ddr_rate = cpu_pll / (postdiv + 1);

	postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
		  AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;

	if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
		ahb_rate = ref_rate;
	else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
		ahb_rate = ddr_pll / (postdiv + 1);
	else
		ahb_rate = cpu_pll / (postdiv + 1);

	ath79_add_sys_clkdev("ref", ref_rate);
	clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
	clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
	clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);

	clk_add_alias("wdt", NULL, "ref", NULL);
	clk_add_alias("uart", NULL, "ref", NULL);

	iounmap(dpll_base);
}

static void __init qca955x_clocks_init(void)
{
	unsigned long ref_rate;
	unsigned long cpu_rate;
	unsigned long ddr_rate;
	unsigned long ahb_rate;
	u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
	u32 cpu_pll, ddr_pll;
	u32 bootstrap;

	bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
	if (bootstrap &	QCA955X_BOOTSTRAP_REF_CLK_40)
		ref_rate = 40 * 1000 * 1000;
	else
		ref_rate = 25 * 1000 * 1000;

	pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
	out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
		  QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
	ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
		  QCA955X_PLL_CPU_CONFIG_REFDIV_MASK;
	nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
	       QCA955X_PLL_CPU_CONFIG_NINT_MASK;
	frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
	       QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;

	cpu_pll = nint * ref_rate / ref_div;
	cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
	cpu_pll /= (1 << out_div);

	pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
	out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
		  QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
	ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
		  QCA955X_PLL_DDR_CONFIG_REFDIV_MASK;
	nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
	       QCA955X_PLL_DDR_CONFIG_NINT_MASK;
	frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
	       QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;

	ddr_pll = nint * ref_rate / ref_div;
	ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
	ddr_pll /= (1 << out_div);

	clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);

	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
		  QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;

	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
		cpu_rate = ref_rate;
	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
		cpu_rate = ddr_pll / (postdiv + 1);
	else
		cpu_rate = cpu_pll / (postdiv + 1);

	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
		  QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;

	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
		ddr_rate = ref_rate;
	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
		ddr_rate = cpu_pll / (postdiv + 1);
	else
		ddr_rate = ddr_pll / (postdiv + 1);

	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
		  QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;

	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
		ahb_rate = ref_rate;
	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
		ahb_rate = ddr_pll / (postdiv + 1);
	else
		ahb_rate = cpu_pll / (postdiv + 1);

	ath79_add_sys_clkdev("ref", ref_rate);
	clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
	clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
	clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);

	clk_add_alias("wdt", NULL, "ref", NULL);
	clk_add_alias("uart", NULL, "ref", NULL);
}

void __init ath79_clocks_init(void)
{
	if (soc_is_ar71xx())
		ar71xx_clocks_init();
	else if (soc_is_ar724x() || soc_is_ar913x())
		ar724x_clocks_init();
	else if (soc_is_ar933x())
		ar933x_clocks_init();
	else if (soc_is_ar934x())
		ar934x_clocks_init();
	else if (soc_is_qca955x())
		qca955x_clocks_init();
	else
		BUG();
}

unsigned long __init
ath79_get_sys_clk_rate(const char *id)
{
	struct clk *clk;
	unsigned long rate;

	clk = clk_get(NULL, id);
	if (IS_ERR(clk))
		panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk));

	rate = clk_get_rate(clk);
	clk_put(clk);

	return rate;
}

#ifdef CONFIG_OF
static void __init ath79_clocks_init_dt(struct device_node *np)
{
	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
}

CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt);
CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt);
CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt);
CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt);

static void __init ath79_clocks_init_dt_ng(struct device_node *np)
{
	struct clk *ref_clk;
	void __iomem *pll_base;
	const char *dnfn = of_node_full_name(np);

	ref_clk = of_clk_get(np, 0);
	if (IS_ERR(ref_clk)) {
		pr_err("%s: of_clk_get failed\n", dnfn);
		goto err;
	}

	pll_base = of_iomap(np, 0);
	if (!pll_base) {
		pr_err("%s: can't map pll registers\n", dnfn);
		goto err_clk;
	}

	if (of_device_is_compatible(np, "qca,ar9130-pll"))
		ar724x_clk_init(ref_clk, pll_base);
	else if (of_device_is_compatible(np, "qca,ar9330-pll"))
		ar9330_clk_init(ref_clk, pll_base);
	else {
		pr_err("%s: could not find any appropriate clk_init()\n", dnfn);
		goto err_clk;
	}

	if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
		pr_err("%s: could not register clk provider\n", dnfn);
		goto err_clk;
	}

	return;

err_clk:
	clk_put(ref_clk);

err:
	return;
}
CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng);
CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt_ng);
#endif
Commit	Line	Data
d4a67d9d GJ	1	/*
	2	* Atheros AR71XX/AR724X/AR913X common routines
	3	*
8889612b	4	* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
d4a67d9d GJ	5	* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
d4a67d9d GJ	6	*
8889612b GJ	7	* Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
8889612b GJ	8	*
d4a67d9d GJ	9	* This program is free software; you can redistribute it and/or modify it
	10	* under the terms of the GNU General Public License version 2 as published
	11	* by the Free Software Foundation.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/module.h>
	16	#include <linux/init.h>
	17	#include <linux/err.h>
	18	#include <linux/clk.h>
2c4f1ac5	19	#include <linux/clkdev.h>
411520af	20	#include <linux/clk-provider.h>
3bdf1071 AP	21	#include <linux/of.h>
3bdf1071 AP	22	#include <linux/of_address.h>
af5ad0de	23	#include <dt-bindings/clock/ath79-clk.h>
d4a67d9d	24
97541ccf GJ	25	#include <asm/div64.h>
97541ccf GJ	26
d4a67d9d GJ	27	#include <asm/mach-ath79/ath79.h>
	28	#include <asm/mach-ath79/ar71xx_regs.h>
	29	#include "common.h"
3bdf1071	30	#include "machtypes.h"
d4a67d9d GJ	31
d4a67d9d GJ	32	#define AR71XX_BASE_FREQ 40000000
c338d59d	33	#define AR724X_BASE_FREQ 40000000
d4a67d9d	34
af5ad0de	35	static struct clk *clks[ATH79_CLK_END];
6451af02 AB	36	static struct clk_onecell_data clk_data = {
	37	.clks = clks,
	38	.clk_num = ARRAY_SIZE(clks),
	39	};
	40
	41	static struct clk *__init ath79_add_sys_clkdev(
	42	const char *id, unsigned long rate)
2c4f1ac5 GJ	43	{
	44	struct clk *clk;
	45	int err;
	46
9c938a0d	47	clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate);
2c4f1ac5 GJ	48	if (!clk)
	49	panic("failed to allocate %s clock structure", id);
	50
2c4f1ac5 GJ	51	err = clk_register_clkdev(clk, id, NULL);
	52	if (err)
	53	panic("unable to register %s clock device", id);
6451af02 AB	54
6451af02 AB	55	return clk;
2c4f1ac5	56	}
d4a67d9d GJ	57
	58	static void __init ar71xx_clocks_init(void)
	59	{
6612a688 GJ	60	unsigned long ref_rate;
	61	unsigned long cpu_rate;
	62	unsigned long ddr_rate;
	63	unsigned long ahb_rate;
d4a67d9d GJ	64	u32 pll;
	65	u32 freq;
	66	u32 div;
	67
6612a688	68	ref_rate = AR71XX_BASE_FREQ;
d4a67d9d GJ	69
	70	pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
	71
626a0695	72	div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;
6612a688	73	freq = div * ref_rate;
d4a67d9d GJ	74
d4a67d9d GJ	75	div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
6612a688	76	cpu_rate = freq / div;
d4a67d9d GJ	77
d4a67d9d GJ	78	div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
6612a688	79	ddr_rate = freq / div;
d4a67d9d GJ	80
d4a67d9d GJ	81	div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
6612a688 GJ	82	ahb_rate = cpu_rate / div;
6612a688 GJ	83
2c4f1ac5	84	ath79_add_sys_clkdev("ref", ref_rate);
af5ad0de AP	85	clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
	86	clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
	87	clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
d4a67d9d	88
2c4f1ac5 GJ	89	clk_add_alias("wdt", NULL, "ahb", NULL);
2c4f1ac5 GJ	90	clk_add_alias("uart", NULL, "ahb", NULL);
d4a67d9d GJ	91	}
d4a67d9d GJ	92
3bdf1071 AP	93	static struct clk * __init ath79_reg_ffclk(const char *name,
3bdf1071 AP	94	const char *parent_name, unsigned int mult, unsigned int div)
d4a67d9d	95	{
3bdf1071	96	struct clk *clk;
d4a67d9d	97
3bdf1071	98	clk = clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
e3b23148	99	if (IS_ERR(clk))
3bdf1071	100	panic("failed to allocate %s clock structure", name);
d4a67d9d	101
3bdf1071 AP	102	return clk;
	103	}
	104
	105	static void __init ar724x_clk_init(struct clk ref_clk, void __iomem pll_base)
	106	{
	107	u32 pll;
	108	u32 mult, div, ddr_div, ahb_div;
d4a67d9d	109
3bdf1071 AP	110	pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG);
	111
	112	mult = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);
c338d59d	113	div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2;
d4a67d9d	114
3bdf1071 AP	115	ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
3bdf1071 AP	116	ahb_div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
d4a67d9d	117
3bdf1071 AP	118	clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref", mult, div);
	119	clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref", mult, div * ddr_div);
	120	clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref", mult, div * ahb_div);
	121	}
d4a67d9d	122
3bdf1071 AP	123	static void __init ar724x_clocks_init(void)
	124	{
	125	struct clk *ref_clk;
6612a688	126
3bdf1071 AP	127	ref_clk = ath79_add_sys_clkdev("ref", AR724X_BASE_FREQ);
	128
	129	ar724x_clk_init(ref_clk, ath79_pll_base);
	130
	131	/* just make happy plat_time_init() from arch/mips/ath79/setup.c */
	132	clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
	133	clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
	134	clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);
d4a67d9d	135
2c4f1ac5 GJ	136	clk_add_alias("wdt", NULL, "ahb", NULL);
2c4f1ac5 GJ	137	clk_add_alias("uart", NULL, "ahb", NULL);
d4a67d9d GJ	138	}
d4a67d9d GJ	139
5ae5c452	140	static void __init ar9330_clk_init(struct clk ref_clk, void __iomem pll_base)
04225e1d GJ	141	{
04225e1d GJ	142	u32 clock_ctrl;
5ae5c452 AP	143	u32 ref_div;
	144	u32 ninit_mul;
	145	u32 out_div;
04225e1d	146
5ae5c452 AP	147	u32 cpu_div;
	148	u32 ddr_div;
	149	u32 ahb_div;
04225e1d	150
5ae5c452	151	clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG);
04225e1d	152	if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
5ae5c452 AP	153	ref_div = 1;
	154	ninit_mul = 1;
	155	out_div = 1;
	156
	157	cpu_div = 1;
	158	ddr_div = 1;
	159	ahb_div = 1;
04225e1d	160	} else {
5ae5c452 AP	161	u32 cpu_config;
	162	u32 t;
	163
	164	cpu_config = __raw_readl(pll_base + AR933X_PLL_CPU_CONFIG_REG);
04225e1d GJ	165
	166	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
	167	AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
5ae5c452	168	ref_div = t;
04225e1d	169
5ae5c452	170	ninit_mul = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
04225e1d	171	AR933X_PLL_CPU_CONFIG_NINT_MASK;
04225e1d GJ	172
	173	t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
	174	AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
	175	if (t == 0)
	176	t = 1;
	177
5ae5c452	178	out_div = (1 << t);
04225e1d	179
5ae5c452	180	cpu_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
04225e1d	181	AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
04225e1d	182
5ae5c452	183	ddr_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
04225e1d	184	AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
04225e1d	185
5ae5c452	186	ahb_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
04225e1d	187	AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
04225e1d GJ	188	}
04225e1d GJ	189
5ae5c452 AP	190	clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref",
	191	ninit_mul, ref_div * out_div * cpu_div);
	192	clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref",
	193	ninit_mul, ref_div * out_div * ddr_div);
	194	clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref",
	195	ninit_mul, ref_div * out_div * ahb_div);
	196	}
	197
	198	static void __init ar933x_clocks_init(void)
	199	{
	200	struct clk *ref_clk;
	201	unsigned long ref_rate;
	202	u32 t;
	203
	204	t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
	205	if (t & AR933X_BOOTSTRAP_REF_CLK_40)
	206	ref_rate = (40 * 1000 * 1000);
	207	else
	208	ref_rate = (25 * 1000 * 1000);
	209
	210	ref_clk = ath79_add_sys_clkdev("ref", ref_rate);
	211
	212	ar9330_clk_init(ref_clk, ath79_pll_base);
	213
	214	/* just make happy plat_time_init() from arch/mips/ath79/setup.c */
	215	clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
	216	clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
	217	clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);
6612a688	218
2c4f1ac5 GJ	219	clk_add_alias("wdt", NULL, "ahb", NULL);
2c4f1ac5 GJ	220	clk_add_alias("uart", NULL, "ref", NULL);
04225e1d GJ	221	}
04225e1d GJ	222
97541ccf GJ	223	static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
	224	u32 frac, u32 out_div)
	225	{
	226	u64 t;
	227	u32 ret;
	228
837f036c	229	t = ref;
97541ccf GJ	230	t *= nint;
	231	do_div(t, ref_div);
	232	ret = t;
	233
837f036c	234	t = ref;
97541ccf GJ	235	t *= nfrac;
	236	do_div(t, ref_div * frac);
	237	ret += t;
	238
	239	ret /= (1 << out_div);
	240	return ret;
	241	}
	242
8889612b GJ	243	static void __init ar934x_clocks_init(void)
8889612b GJ	244	{
6612a688 GJ	245	unsigned long ref_rate;
	246	unsigned long cpu_rate;
	247	unsigned long ddr_rate;
	248	unsigned long ahb_rate;
97541ccf	249	u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
8889612b GJ	250	u32 cpu_pll, ddr_pll;
8889612b GJ	251	u32 bootstrap;
97541ccf GJ	252	void __iomem *dpll_base;
	253
	254	dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE);
8889612b GJ	255
8889612b GJ	256	bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
70342287	257	if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
6612a688	258	ref_rate = 40 * 1000 * 1000;
8889612b	259	else
6612a688	260	ref_rate = 25 * 1000 * 1000;
8889612b	261
97541ccf GJ	262	pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
	263	if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
	264	out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
	265	AR934X_SRIF_DPLL2_OUTDIV_MASK;
	266	pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG);
	267	nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
	268	AR934X_SRIF_DPLL1_NINT_MASK;
	269	nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
	270	ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
	271	AR934X_SRIF_DPLL1_REFDIV_MASK;
	272	frac = 1 << 18;
	273	} else {
	274	pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
	275	out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
	276	AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
	277	ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
	278	AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
	279	nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
	280	AR934X_PLL_CPU_CONFIG_NINT_MASK;
	281	nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
	282	AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
	283	frac = 1 << 6;
	284	}
	285
6612a688	286	cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
97541ccf GJ	287	nfrac, frac, out_div);
	288
	289	pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);
	290	if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
	291	out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
	292	AR934X_SRIF_DPLL2_OUTDIV_MASK;
	293	pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG);
	294	nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
	295	AR934X_SRIF_DPLL1_NINT_MASK;
	296	nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
	297	ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
	298	AR934X_SRIF_DPLL1_REFDIV_MASK;
	299	frac = 1 << 18;
	300	} else {
	301	pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
	302	out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
	303	AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
	304	ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
	305	AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
	306	nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
	307	AR934X_PLL_DDR_CONFIG_NINT_MASK;
	308	nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
	309	AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
	310	frac = 1 << 10;
	311	}
	312
6612a688	313	ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
97541ccf	314	nfrac, frac, out_div);
8889612b GJ	315
	316	clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
	317
	318	postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
	319	AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
	320
	321	if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
6612a688	322	cpu_rate = ref_rate;
8889612b	323	else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
6612a688	324	cpu_rate = cpu_pll / (postdiv + 1);
8889612b	325	else
6612a688	326	cpu_rate = ddr_pll / (postdiv + 1);
8889612b GJ	327
	328	postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
	329	AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
	330
	331	if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
6612a688	332	ddr_rate = ref_rate;
8889612b	333	else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
6612a688	334	ddr_rate = ddr_pll / (postdiv + 1);
8889612b	335	else
6612a688	336	ddr_rate = cpu_pll / (postdiv + 1);
8889612b GJ	337
	338	postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
	339	AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
	340
	341	if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
6612a688	342	ahb_rate = ref_rate;
8889612b	343	else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
6612a688	344	ahb_rate = ddr_pll / (postdiv + 1);
8889612b	345	else
6612a688 GJ	346	ahb_rate = cpu_pll / (postdiv + 1);
6612a688 GJ	347
2c4f1ac5	348	ath79_add_sys_clkdev("ref", ref_rate);
af5ad0de AP	349	clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
	350	clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
	351	clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
8889612b	352
2c4f1ac5 GJ	353	clk_add_alias("wdt", NULL, "ref", NULL);
2c4f1ac5 GJ	354	clk_add_alias("uart", NULL, "ref", NULL);
97541ccf GJ	355
97541ccf GJ	356	iounmap(dpll_base);
8889612b GJ	357	}
8889612b GJ	358
41583c05 GJ	359	static void __init qca955x_clocks_init(void)
41583c05 GJ	360	{
6612a688 GJ	361	unsigned long ref_rate;
	362	unsigned long cpu_rate;
	363	unsigned long ddr_rate;
	364	unsigned long ahb_rate;
41583c05 GJ	365	u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
	366	u32 cpu_pll, ddr_pll;
	367	u32 bootstrap;
	368
	369	bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
	370	if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40)
6612a688	371	ref_rate = 40 * 1000 * 1000;
41583c05	372	else
6612a688	373	ref_rate = 25 * 1000 * 1000;
41583c05 GJ	374
	375	pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
	376	out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
	377	QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
	378	ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
	379	QCA955X_PLL_CPU_CONFIG_REFDIV_MASK;
	380	nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
	381	QCA955X_PLL_CPU_CONFIG_NINT_MASK;
	382	frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
	383	QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
	384
6612a688 GJ	385	cpu_pll = nint * ref_rate / ref_div;
6612a688 GJ	386	cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
41583c05 GJ	387	cpu_pll /= (1 << out_div);
	388
	389	pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
	390	out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
	391	QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
	392	ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
	393	QCA955X_PLL_DDR_CONFIG_REFDIV_MASK;
	394	nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
	395	QCA955X_PLL_DDR_CONFIG_NINT_MASK;
	396	frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
	397	QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
	398
6612a688 GJ	399	ddr_pll = nint * ref_rate / ref_div;
6612a688 GJ	400	ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
41583c05 GJ	401	ddr_pll /= (1 << out_div);
	402
	403	clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
	404
	405	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
	406	QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
	407
	408	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
6612a688	409	cpu_rate = ref_rate;
41583c05	410	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
6612a688	411	cpu_rate = ddr_pll / (postdiv + 1);
41583c05	412	else
6612a688	413	cpu_rate = cpu_pll / (postdiv + 1);
41583c05 GJ	414
	415	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
	416	QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
	417
	418	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
6612a688	419	ddr_rate = ref_rate;
41583c05	420	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
6612a688	421	ddr_rate = cpu_pll / (postdiv + 1);
41583c05	422	else
6612a688	423	ddr_rate = ddr_pll / (postdiv + 1);
41583c05 GJ	424
	425	postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
	426	QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
	427
	428	if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
6612a688	429	ahb_rate = ref_rate;
41583c05	430	else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
6612a688	431	ahb_rate = ddr_pll / (postdiv + 1);
41583c05	432	else
6612a688 GJ	433	ahb_rate = cpu_pll / (postdiv + 1);
6612a688 GJ	434
2c4f1ac5	435	ath79_add_sys_clkdev("ref", ref_rate);
af5ad0de AP	436	clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
	437	clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
	438	clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
41583c05	439
2c4f1ac5 GJ	440	clk_add_alias("wdt", NULL, "ref", NULL);
2c4f1ac5 GJ	441	clk_add_alias("uart", NULL, "ref", NULL);
41583c05 GJ	442	}
41583c05 GJ	443
d4a67d9d GJ	444	void __init ath79_clocks_init(void)
	445	{
	446	if (soc_is_ar71xx())
	447	ar71xx_clocks_init();
f4c87b7a	448	else if (soc_is_ar724x() \|\| soc_is_ar913x())
d4a67d9d	449	ar724x_clocks_init();
04225e1d GJ	450	else if (soc_is_ar933x())
04225e1d GJ	451	ar933x_clocks_init();
8889612b GJ	452	else if (soc_is_ar934x())
8889612b GJ	453	ar934x_clocks_init();
41583c05 GJ	454	else if (soc_is_qca955x())
41583c05 GJ	455	qca955x_clocks_init();
d4a67d9d GJ	456	else
d4a67d9d GJ	457	BUG();
d4a67d9d GJ	458	}
d4a67d9d GJ	459
23107802 GJ	460	unsigned long __init
	461	ath79_get_sys_clk_rate(const char *id)
	462	{
	463	struct clk *clk;
	464	unsigned long rate;
	465
	466	clk = clk_get(NULL, id);
	467	if (IS_ERR(clk))
	468	panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk));
	469
	470	rate = clk_get_rate(clk);
	471	clk_put(clk);
	472
	473	return rate;
	474	}
6451af02 AB	475
	476	#ifdef CONFIG_OF
	477	static void __init ath79_clocks_init_dt(struct device_node *np)
	478	{
	479	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
	480	}
	481
	482	CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt);
	483	CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt);
6451af02 AB	484	CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt);
6451af02 AB	485	CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt);
3bdf1071 AP	486
	487	static void __init ath79_clocks_init_dt_ng(struct device_node *np)
	488	{
	489	struct clk *ref_clk;
	490	void __iomem *pll_base;
	491	const char *dnfn = of_node_full_name(np);
	492
	493	ref_clk = of_clk_get(np, 0);
	494	if (IS_ERR(ref_clk)) {
	495	pr_err("%s: of_clk_get failed\n", dnfn);
	496	goto err;
	497	}
	498
	499	pll_base = of_iomap(np, 0);
	500	if (!pll_base) {
	501	pr_err("%s: can't map pll registers\n", dnfn);
	502	goto err_clk;
	503	}
	504
5ae5c452 AP	505	if (of_device_is_compatible(np, "qca,ar9130-pll"))
	506	ar724x_clk_init(ref_clk, pll_base);
	507	else if (of_device_is_compatible(np, "qca,ar9330-pll"))
	508	ar9330_clk_init(ref_clk, pll_base);
	509	else {
	510	pr_err("%s: could not find any appropriate clk_init()\n", dnfn);
	511	goto err_clk;
	512	}
3bdf1071 AP	513
	514	if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
	515	pr_err("%s: could not register clk provider\n", dnfn);
	516	goto err_clk;
	517	}
	518
	519	return;
	520
	521	err_clk:
	522	clk_put(ref_clk);
	523
	524	err:
	525	return;
	526	}
	527	CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng);
5ae5c452	528	CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt_ng);
6451af02	529	#endif