[mirror_ubuntu-jammy-kernel.git] / arch / mips / ath79 / common.c

/*
 *  Atheros AR71XX/AR724X/AR913X common routines
 *
 *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
 *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
 *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
 *
 *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License version 2 as published
 *  by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/export.h>
#include <linux/types.h>
#include <linux/spinlock.h>

#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include "common.h"

static DEFINE_SPINLOCK(ath79_device_reset_lock);

u32 ath79_cpu_freq;
EXPORT_SYMBOL_GPL(ath79_cpu_freq);

u32 ath79_ahb_freq;
EXPORT_SYMBOL_GPL(ath79_ahb_freq);

u32 ath79_ddr_freq;
EXPORT_SYMBOL_GPL(ath79_ddr_freq);

enum ath79_soc_type ath79_soc;
unsigned int ath79_soc_rev;

void __iomem *ath79_pll_base;
void __iomem *ath79_reset_base;
EXPORT_SYMBOL_GPL(ath79_reset_base);
static void __iomem *ath79_ddr_base;
static void __iomem *ath79_ddr_wb_flush_base;
static void __iomem *ath79_ddr_pci_win_base;

void ath79_ddr_ctrl_init(void)
{
	ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
					 AR71XX_DDR_CTRL_SIZE);
	if (soc_is_ar913x() || soc_is_ar724x() || soc_is_ar933x()) {
		ath79_ddr_wb_flush_base = ath79_ddr_base + 0x7c;
		ath79_ddr_pci_win_base = 0;
	} else {
		ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c;
		ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c;
	}
}
EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init);

void ath79_ddr_wb_flush(u32 reg)
{
	void __iomem *flush_reg = ath79_ddr_wb_flush_base + reg;

	/* Flush the DDR write buffer. */
	__raw_writel(0x1, flush_reg);
	while (__raw_readl(flush_reg) & 0x1)
		;

	/* It must be run twice. */
	__raw_writel(0x1, flush_reg);
	while (__raw_readl(flush_reg) & 0x1)
		;
}
EXPORT_SYMBOL_GPL(ath79_ddr_wb_flush);

void ath79_ddr_set_pci_windows(void)
{
	BUG_ON(!ath79_ddr_pci_win_base);

	__raw_writel(AR71XX_PCI_WIN0_OFFS, ath79_ddr_pci_win_base + 0x0);
	__raw_writel(AR71XX_PCI_WIN1_OFFS, ath79_ddr_pci_win_base + 0x4);
	__raw_writel(AR71XX_PCI_WIN2_OFFS, ath79_ddr_pci_win_base + 0x8);
	__raw_writel(AR71XX_PCI_WIN3_OFFS, ath79_ddr_pci_win_base + 0xc);
	__raw_writel(AR71XX_PCI_WIN4_OFFS, ath79_ddr_pci_win_base + 0x10);
	__raw_writel(AR71XX_PCI_WIN5_OFFS, ath79_ddr_pci_win_base + 0x14);
	__raw_writel(AR71XX_PCI_WIN6_OFFS, ath79_ddr_pci_win_base + 0x18);
	__raw_writel(AR71XX_PCI_WIN7_OFFS, ath79_ddr_pci_win_base + 0x1c);
}
EXPORT_SYMBOL_GPL(ath79_ddr_set_pci_windows);

void ath79_device_reset_set(u32 mask)
{
	unsigned long flags;
	u32 reg;
	u32 t;

	if (soc_is_ar71xx())
		reg = AR71XX_RESET_REG_RESET_MODULE;
	else if (soc_is_ar724x())
		reg = AR724X_RESET_REG_RESET_MODULE;
	else if (soc_is_ar913x())
		reg = AR913X_RESET_REG_RESET_MODULE;
	else if (soc_is_ar933x())
		reg = AR933X_RESET_REG_RESET_MODULE;
	else if (soc_is_ar934x())
		reg = AR934X_RESET_REG_RESET_MODULE;
	else if (soc_is_qca953x())
		reg = QCA953X_RESET_REG_RESET_MODULE;
	else if (soc_is_qca955x())
		reg = QCA955X_RESET_REG_RESET_MODULE;
	else if (soc_is_qca956x() || soc_is_tp9343())
		reg = QCA956X_RESET_REG_RESET_MODULE;
	else
		BUG();

	spin_lock_irqsave(&ath79_device_reset_lock, flags);
	t = ath79_reset_rr(reg);
	ath79_reset_wr(reg, t | mask);
	spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
}
EXPORT_SYMBOL_GPL(ath79_device_reset_set);

void ath79_device_reset_clear(u32 mask)
{
	unsigned long flags;
	u32 reg;
	u32 t;

	if (soc_is_ar71xx())
		reg = AR71XX_RESET_REG_RESET_MODULE;
	else if (soc_is_ar724x())
		reg = AR724X_RESET_REG_RESET_MODULE;
	else if (soc_is_ar913x())
		reg = AR913X_RESET_REG_RESET_MODULE;
	else if (soc_is_ar933x())
		reg = AR933X_RESET_REG_RESET_MODULE;
	else if (soc_is_ar934x())
		reg = AR934X_RESET_REG_RESET_MODULE;
	else if (soc_is_qca953x())
		reg = QCA953X_RESET_REG_RESET_MODULE;
	else if (soc_is_qca955x())
		reg = QCA955X_RESET_REG_RESET_MODULE;
	else if (soc_is_qca956x() || soc_is_tp9343())
		reg = QCA956X_RESET_REG_RESET_MODULE;
	else
		BUG();

	spin_lock_irqsave(&ath79_device_reset_lock, flags);
	t = ath79_reset_rr(reg);
	ath79_reset_wr(reg, t & ~mask);
	spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
}
EXPORT_SYMBOL_GPL(ath79_device_reset_clear);
Commit	Line	Data
d4a67d9d GJ	1	/*
	2	* Atheros AR71XX/AR724X/AR913X common routines
	3	*
42184768 GJ	4	* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
42184768 GJ	5	* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
d4a67d9d GJ	6	* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
d4a67d9d GJ	7	*
42184768 GJ	8	* Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
42184768 GJ	9	*
d4a67d9d GJ	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License version 2 as published
	12	* by the Free Software Foundation.
	13	*/
	14
	15	#include <linux/kernel.h>
26dd3e4f	16	#include <linux/export.h>
d4a67d9d GJ	17	#include <linux/types.h>
	18	#include <linux/spinlock.h>
	19
	20	#include <asm/mach-ath79/ath79.h>
	21	#include <asm/mach-ath79/ar71xx_regs.h>
	22	#include "common.h"
	23
	24	static DEFINE_SPINLOCK(ath79_device_reset_lock);
	25
	26	u32 ath79_cpu_freq;
	27	EXPORT_SYMBOL_GPL(ath79_cpu_freq);
	28
	29	u32 ath79_ahb_freq;
	30	EXPORT_SYMBOL_GPL(ath79_ahb_freq);
	31
	32	u32 ath79_ddr_freq;
	33	EXPORT_SYMBOL_GPL(ath79_ddr_freq);
	34
	35	enum ath79_soc_type ath79_soc;
be5f3623	36	unsigned int ath79_soc_rev;
d4a67d9d GJ	37
	38	void __iomem *ath79_pll_base;
	39	void __iomem *ath79_reset_base;
	40	EXPORT_SYMBOL_GPL(ath79_reset_base);
24b0e3e8 AB	41	static void __iomem *ath79_ddr_base;
	42	static void __iomem *ath79_ddr_wb_flush_base;
	43	static void __iomem *ath79_ddr_pci_win_base;
	44
	45	void ath79_ddr_ctrl_init(void)
	46	{
	47	ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
	48	AR71XX_DDR_CTRL_SIZE);
6241bf6a	49	if (soc_is_ar913x() \|\| soc_is_ar724x() \|\| soc_is_ar933x()) {
24b0e3e8 AB	50	ath79_ddr_wb_flush_base = ath79_ddr_base + 0x7c;
24b0e3e8 AB	51	ath79_ddr_pci_win_base = 0;
6241bf6a FF	52	} else {
	53	ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c;
	54	ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c;
24b0e3e8 AB	55	}
	56	}
	57	EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init);
d4a67d9d GJ	58
	59	void ath79_ddr_wb_flush(u32 reg)
	60	{
24b0e3e8	61	void __iomem *flush_reg = ath79_ddr_wb_flush_base + reg;
d4a67d9d GJ	62
	63	/* Flush the DDR write buffer. */
	64	__raw_writel(0x1, flush_reg);
	65	while (__raw_readl(flush_reg) & 0x1)
	66	;
	67
	68	/* It must be run twice. */
	69	__raw_writel(0x1, flush_reg);
	70	while (__raw_readl(flush_reg) & 0x1)
	71	;
	72	}
	73	EXPORT_SYMBOL_GPL(ath79_ddr_wb_flush);
	74
24b0e3e8 AB	75	void ath79_ddr_set_pci_windows(void)
	76	{
	77	BUG_ON(!ath79_ddr_pci_win_base);
	78
9184dc8f FF	79	__raw_writel(AR71XX_PCI_WIN0_OFFS, ath79_ddr_pci_win_base + 0x0);
	80	__raw_writel(AR71XX_PCI_WIN1_OFFS, ath79_ddr_pci_win_base + 0x4);
	81	__raw_writel(AR71XX_PCI_WIN2_OFFS, ath79_ddr_pci_win_base + 0x8);
	82	__raw_writel(AR71XX_PCI_WIN3_OFFS, ath79_ddr_pci_win_base + 0xc);
	83	__raw_writel(AR71XX_PCI_WIN4_OFFS, ath79_ddr_pci_win_base + 0x10);
	84	__raw_writel(AR71XX_PCI_WIN5_OFFS, ath79_ddr_pci_win_base + 0x14);
	85	__raw_writel(AR71XX_PCI_WIN6_OFFS, ath79_ddr_pci_win_base + 0x18);
	86	__raw_writel(AR71XX_PCI_WIN7_OFFS, ath79_ddr_pci_win_base + 0x1c);
24b0e3e8 AB	87	}
	88	EXPORT_SYMBOL_GPL(ath79_ddr_set_pci_windows);
	89
d4a67d9d GJ	90	void ath79_device_reset_set(u32 mask)
	91	{
	92	unsigned long flags;
	93	u32 reg;
	94	u32 t;
	95
	96	if (soc_is_ar71xx())
	97	reg = AR71XX_RESET_REG_RESET_MODULE;
	98	else if (soc_is_ar724x())
	99	reg = AR724X_RESET_REG_RESET_MODULE;
	100	else if (soc_is_ar913x())
	101	reg = AR913X_RESET_REG_RESET_MODULE;
7ee15d8a GJ	102	else if (soc_is_ar933x())
7ee15d8a GJ	103	reg = AR933X_RESET_REG_RESET_MODULE;
42184768 GJ	104	else if (soc_is_ar934x())
42184768 GJ	105	reg = AR934X_RESET_REG_RESET_MODULE;
af2d1b52 MS	106	else if (soc_is_qca953x())
af2d1b52 MS	107	reg = QCA953X_RESET_REG_RESET_MODULE;
7d4c2af9 GJ	108	else if (soc_is_qca955x())
7d4c2af9 GJ	109	reg = QCA955X_RESET_REG_RESET_MODULE;
af2d1b52 MS	110	else if (soc_is_qca956x() \|\| soc_is_tp9343())
af2d1b52 MS	111	reg = QCA956X_RESET_REG_RESET_MODULE;
d4a67d9d GJ	112	else
	113	BUG();
	114
	115	spin_lock_irqsave(&ath79_device_reset_lock, flags);
	116	t = ath79_reset_rr(reg);
	117	ath79_reset_wr(reg, t \| mask);
	118	spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
	119	}
	120	EXPORT_SYMBOL_GPL(ath79_device_reset_set);
	121
	122	void ath79_device_reset_clear(u32 mask)
	123	{
	124	unsigned long flags;
	125	u32 reg;
	126	u32 t;
	127
	128	if (soc_is_ar71xx())
	129	reg = AR71XX_RESET_REG_RESET_MODULE;
	130	else if (soc_is_ar724x())
	131	reg = AR724X_RESET_REG_RESET_MODULE;
	132	else if (soc_is_ar913x())
	133	reg = AR913X_RESET_REG_RESET_MODULE;
7ee15d8a GJ	134	else if (soc_is_ar933x())
7ee15d8a GJ	135	reg = AR933X_RESET_REG_RESET_MODULE;
42184768 GJ	136	else if (soc_is_ar934x())
42184768 GJ	137	reg = AR934X_RESET_REG_RESET_MODULE;
af2d1b52 MS	138	else if (soc_is_qca953x())
af2d1b52 MS	139	reg = QCA953X_RESET_REG_RESET_MODULE;
7d4c2af9 GJ	140	else if (soc_is_qca955x())
7d4c2af9 GJ	141	reg = QCA955X_RESET_REG_RESET_MODULE;
af2d1b52 MS	142	else if (soc_is_qca956x() \|\| soc_is_tp9343())
af2d1b52 MS	143	reg = QCA956X_RESET_REG_RESET_MODULE;
d4a67d9d GJ	144	else
	145	BUG();
	146
	147	spin_lock_irqsave(&ath79_device_reset_lock, flags);
	148	t = ath79_reset_rr(reg);
	149	ath79_reset_wr(reg, t & ~mask);
	150	spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
	151	}
	152	EXPORT_SYMBOL_GPL(ath79_device_reset_clear);