[mirror_ubuntu-jammy-kernel.git] / arch / mips / ath79 / setup.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 *  Atheros AR71XX/AR724X/AR913X specific setup
 *
 *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
 *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
 *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
 *
 *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/memblock.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/of_fdt.h>
#include <linux/irqchip.h>

#include <asm/bootinfo.h>
#include <asm/idle.h>
#include <asm/time.h>		/* for mips_hpt_frequency */
#include <asm/reboot.h>		/* for _machine_{restart,halt} */
#include <asm/mips_machine.h>
#include <asm/prom.h>
#include <asm/fw/fw.h>

#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include "common.h"

#define ATH79_SYS_TYPE_LEN	64

static char ath79_sys_type[ATH79_SYS_TYPE_LEN];

static void ath79_restart(char *command)
{
	local_irq_disable();
	ath79_device_reset_set(AR71XX_RESET_FULL_CHIP);
	for (;;)
		if (cpu_wait)
			cpu_wait();
}

static void ath79_halt(void)
{
	while (1)
		cpu_wait();
}

static void __init ath79_detect_sys_type(void)
{
	char *chip = "????";
	u32 id;
	u32 major;
	u32 minor;
	u32 rev = 0;
	u32 ver = 1;

	id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
	major = id & REV_ID_MAJOR_MASK;

	switch (major) {
	case REV_ID_MAJOR_AR71XX:
		minor = id & AR71XX_REV_ID_MINOR_MASK;
		rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
		rev &= AR71XX_REV_ID_REVISION_MASK;
		switch (minor) {
		case AR71XX_REV_ID_MINOR_AR7130:
			ath79_soc = ATH79_SOC_AR7130;
			chip = "7130";
			break;

		case AR71XX_REV_ID_MINOR_AR7141:
			ath79_soc = ATH79_SOC_AR7141;
			chip = "7141";
			break;

		case AR71XX_REV_ID_MINOR_AR7161:
			ath79_soc = ATH79_SOC_AR7161;
			chip = "7161";
			break;
		}
		break;

	case REV_ID_MAJOR_AR7240:
		ath79_soc = ATH79_SOC_AR7240;
		chip = "7240";
		rev = id & AR724X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_AR7241:
		ath79_soc = ATH79_SOC_AR7241;
		chip = "7241";
		rev = id & AR724X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_AR7242:
		ath79_soc = ATH79_SOC_AR7242;
		chip = "7242";
		rev = id & AR724X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_AR913X:
		minor = id & AR913X_REV_ID_MINOR_MASK;
		rev = id >> AR913X_REV_ID_REVISION_SHIFT;
		rev &= AR913X_REV_ID_REVISION_MASK;
		switch (minor) {
		case AR913X_REV_ID_MINOR_AR9130:
			ath79_soc = ATH79_SOC_AR9130;
			chip = "9130";
			break;

		case AR913X_REV_ID_MINOR_AR9132:
			ath79_soc = ATH79_SOC_AR9132;
			chip = "9132";
			break;
		}
		break;

	case REV_ID_MAJOR_AR9330:
		ath79_soc = ATH79_SOC_AR9330;
		chip = "9330";
		rev = id & AR933X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_AR9331:
		ath79_soc = ATH79_SOC_AR9331;
		chip = "9331";
		rev = id & AR933X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_AR9341:
		ath79_soc = ATH79_SOC_AR9341;
		chip = "9341";
		rev = id & AR934X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_AR9342:
		ath79_soc = ATH79_SOC_AR9342;
		chip = "9342";
		rev = id & AR934X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_AR9344:
		ath79_soc = ATH79_SOC_AR9344;
		chip = "9344";
		rev = id & AR934X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_QCA9533_V2:
		ver = 2;
		ath79_soc_rev = 2;
		/* drop through */

	case REV_ID_MAJOR_QCA9533:
		ath79_soc = ATH79_SOC_QCA9533;
		chip = "9533";
		rev = id & QCA953X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_QCA9556:
		ath79_soc = ATH79_SOC_QCA9556;
		chip = "9556";
		rev = id & QCA955X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_QCA9558:
		ath79_soc = ATH79_SOC_QCA9558;
		chip = "9558";
		rev = id & QCA955X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_QCA956X:
		ath79_soc = ATH79_SOC_QCA956X;
		chip = "956X";
		rev = id & QCA956X_REV_ID_REVISION_MASK;
		break;

	case REV_ID_MAJOR_TP9343:
		ath79_soc = ATH79_SOC_TP9343;
		chip = "9343";
		rev = id & QCA956X_REV_ID_REVISION_MASK;
		break;

	default:
		panic("ath79: unknown SoC, id:0x%08x", id);
	}

	if (ver == 1)
		ath79_soc_rev = rev;

	if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x())
		sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
			chip, ver, rev);
	else if (soc_is_tp9343())
		sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",
			chip, rev);
	else
		sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
	pr_info("SoC: %s\n", ath79_sys_type);
}

const char *get_system_type(void)
{
	return ath79_sys_type;
}

unsigned int get_c0_compare_int(void)
{
	return CP0_LEGACY_COMPARE_IRQ;
}

void __init plat_mem_setup(void)
{
	unsigned long fdt_start;

	set_io_port_base(KSEG1);

	/* Get the position of the FDT passed by the bootloader */
	fdt_start = fw_getenvl("fdt_start");
	if (fdt_start)
		__dt_setup_arch((void *)KSEG0ADDR(fdt_start));
	else if (fw_passed_dtb)
		__dt_setup_arch((void *)KSEG0ADDR(fw_passed_dtb));

	ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
					   AR71XX_RESET_SIZE);
	ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
					 AR71XX_PLL_SIZE);
	ath79_detect_sys_type();
	ath79_ddr_ctrl_init();

	detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);

	_machine_restart = ath79_restart;
	_machine_halt = ath79_halt;
	pm_power_off = ath79_halt;
}

void __init plat_time_init(void)
{
	struct device_node *np;
	struct clk *clk;
	unsigned long cpu_clk_rate;

	of_clk_init(NULL);

	np = of_get_cpu_node(0, NULL);
	if (!np) {
		pr_err("Failed to get CPU node\n");
		return;
	}

	clk = of_clk_get(np, 0);
	if (IS_ERR(clk)) {
		pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk));
		return;
	}

	cpu_clk_rate = clk_get_rate(clk);

	pr_info("CPU clock: %lu.%03lu MHz\n",
		cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000);

	mips_hpt_frequency = cpu_clk_rate / 2;

	clk_put(clk);
}

void __init arch_init_irq(void)
{
	irqchip_init();
}

void __init device_tree_init(void)
{
	unflatten_and_copy_device_tree();
}
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
d4a67d9d GJ	2	/*
	3	* Atheros AR71XX/AR724X/AR913X specific setup
	4	*
d8411466	5	* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
d4a67d9d GJ	6	* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
	7	* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
	8	*
d8411466	9	* Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
d4a67d9d GJ	10	*/
	11
	12	#include <linux/kernel.h>
	13	#include <linux/init.h>
62e59c4e	14	#include <linux/io.h>
57c8a661	15	#include <linux/memblock.h>
d4a67d9d GJ	16	#include <linux/err.h>
d4a67d9d GJ	17	#include <linux/clk.h>
20ff3ada	18	#include <linux/clk-provider.h>
03c8c407	19	#include <linux/of_fdt.h>
51fa4f89	20	#include <linux/irqchip.h>
d4a67d9d GJ	21
d4a67d9d GJ	22	#include <asm/bootinfo.h>
bdc92d74	23	#include <asm/idle.h>
d4a67d9d GJ	24	#include <asm/time.h> /* for mips_hpt_frequency */
d4a67d9d GJ	25	#include <asm/reboot.h> /* for _machine_{restart,halt} */
0aabf1a4	26	#include <asm/mips_machine.h>
03c8c407 AB	27	#include <asm/prom.h>
03c8c407 AB	28	#include <asm/fw/fw.h>
d4a67d9d GJ	29
	30	#include <asm/mach-ath79/ath79.h>
	31	#include <asm/mach-ath79/ar71xx_regs.h>
	32	#include "common.h"
d4a67d9d GJ	33
	34	#define ATH79_SYS_TYPE_LEN 64
	35
d4a67d9d GJ	36	static char ath79_sys_type[ATH79_SYS_TYPE_LEN];
	37
	38	static void ath79_restart(char *command)
	39	{
f8a7bfe1	40	local_irq_disable();
d4a67d9d GJ	41	ath79_device_reset_set(AR71XX_RESET_FULL_CHIP);
	42	for (;;)
	43	if (cpu_wait)
	44	cpu_wait();
	45	}
	46
	47	static void ath79_halt(void)
	48	{
	49	while (1)
	50	cpu_wait();
	51	}
	52
d4a67d9d GJ	53	static void __init ath79_detect_sys_type(void)
	54	{
	55	char *chip = "????";
	56	u32 id;
	57	u32 major;
	58	u32 minor;
	59	u32 rev = 0;
af2d1b52	60	u32 ver = 1;
d4a67d9d GJ	61
	62	id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
	63	major = id & REV_ID_MAJOR_MASK;
	64
	65	switch (major) {
	66	case REV_ID_MAJOR_AR71XX:
	67	minor = id & AR71XX_REV_ID_MINOR_MASK;
	68	rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
	69	rev &= AR71XX_REV_ID_REVISION_MASK;
	70	switch (minor) {
	71	case AR71XX_REV_ID_MINOR_AR7130:
	72	ath79_soc = ATH79_SOC_AR7130;
	73	chip = "7130";
	74	break;
	75
	76	case AR71XX_REV_ID_MINOR_AR7141:
	77	ath79_soc = ATH79_SOC_AR7141;
	78	chip = "7141";
	79	break;
	80
	81	case AR71XX_REV_ID_MINOR_AR7161:
	82	ath79_soc = ATH79_SOC_AR7161;
	83	chip = "7161";
	84	break;
	85	}
	86	break;
	87
	88	case REV_ID_MAJOR_AR7240:
	89	ath79_soc = ATH79_SOC_AR7240;
	90	chip = "7240";
8bed1288	91	rev = id & AR724X_REV_ID_REVISION_MASK;
d4a67d9d GJ	92	break;
	93
	94	case REV_ID_MAJOR_AR7241:
	95	ath79_soc = ATH79_SOC_AR7241;
	96	chip = "7241";
8bed1288	97	rev = id & AR724X_REV_ID_REVISION_MASK;
d4a67d9d GJ	98	break;
	99
	100	case REV_ID_MAJOR_AR7242:
	101	ath79_soc = ATH79_SOC_AR7242;
	102	chip = "7242";
8bed1288	103	rev = id & AR724X_REV_ID_REVISION_MASK;
d4a67d9d GJ	104	break;
	105
	106	case REV_ID_MAJOR_AR913X:
	107	minor = id & AR913X_REV_ID_MINOR_MASK;
	108	rev = id >> AR913X_REV_ID_REVISION_SHIFT;
	109	rev &= AR913X_REV_ID_REVISION_MASK;
	110	switch (minor) {
	111	case AR913X_REV_ID_MINOR_AR9130:
	112	ath79_soc = ATH79_SOC_AR9130;
	113	chip = "9130";
	114	break;
	115
	116	case AR913X_REV_ID_MINOR_AR9132:
	117	ath79_soc = ATH79_SOC_AR9132;
	118	chip = "9132";
	119	break;
	120	}
	121	break;
	122
80a7ed81 GJ	123	case REV_ID_MAJOR_AR9330:
	124	ath79_soc = ATH79_SOC_AR9330;
	125	chip = "9330";
	126	rev = id & AR933X_REV_ID_REVISION_MASK;
	127	break;
	128
	129	case REV_ID_MAJOR_AR9331:
	130	ath79_soc = ATH79_SOC_AR9331;
	131	chip = "9331";
	132	rev = id & AR933X_REV_ID_REVISION_MASK;
	133	break;
	134
d8411466 GJ	135	case REV_ID_MAJOR_AR9341:
	136	ath79_soc = ATH79_SOC_AR9341;
	137	chip = "9341";
	138	rev = id & AR934X_REV_ID_REVISION_MASK;
	139	break;
	140
	141	case REV_ID_MAJOR_AR9342:
	142	ath79_soc = ATH79_SOC_AR9342;
	143	chip = "9342";
	144	rev = id & AR934X_REV_ID_REVISION_MASK;
	145	break;
	146
	147	case REV_ID_MAJOR_AR9344:
	148	ath79_soc = ATH79_SOC_AR9344;
	149	chip = "9344";
	150	rev = id & AR934X_REV_ID_REVISION_MASK;
	151	break;
	152
af2d1b52 MS	153	case REV_ID_MAJOR_QCA9533_V2:
	154	ver = 2;
	155	ath79_soc_rev = 2;
	156	/* drop through */
	157
	158	case REV_ID_MAJOR_QCA9533:
	159	ath79_soc = ATH79_SOC_QCA9533;
	160	chip = "9533";
	161	rev = id & QCA953X_REV_ID_REVISION_MASK;
	162	break;
	163
2e6c91e3 GJ	164	case REV_ID_MAJOR_QCA9556:
	165	ath79_soc = ATH79_SOC_QCA9556;
	166	chip = "9556";
	167	rev = id & QCA955X_REV_ID_REVISION_MASK;
	168	break;
	169
	170	case REV_ID_MAJOR_QCA9558:
	171	ath79_soc = ATH79_SOC_QCA9558;
	172	chip = "9558";
	173	rev = id & QCA955X_REV_ID_REVISION_MASK;
	174	break;
	175
af2d1b52 MS	176	case REV_ID_MAJOR_QCA956X:
	177	ath79_soc = ATH79_SOC_QCA956X;
	178	chip = "956X";
	179	rev = id & QCA956X_REV_ID_REVISION_MASK;
	180	break;
	181
	182	case REV_ID_MAJOR_TP9343:
	183	ath79_soc = ATH79_SOC_TP9343;
	184	chip = "9343";
	185	rev = id & QCA956X_REV_ID_REVISION_MASK;
	186	break;
	187
d4a67d9d	188	default:
ab75dc02	189	panic("ath79: unknown SoC, id:0x%08x", id);
d4a67d9d GJ	190	}
d4a67d9d GJ	191
af2d1b52 MS	192	if (ver == 1)
af2d1b52 MS	193	ath79_soc_rev = rev;
be5f3623	194
af2d1b52 MS	195	if (soc_is_qca953x() \|\| soc_is_qca955x() \|\| soc_is_qca956x())
	196	sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
	197	chip, ver, rev);
	198	else if (soc_is_tp9343())
	199	sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",
2e6c91e3 GJ	200	chip, rev);
	201	else
	202	sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
d4a67d9d GJ	203	pr_info("SoC: %s\n", ath79_sys_type);
	204	}
	205
	206	const char *get_system_type(void)
	207	{
	208	return ath79_sys_type;
	209	}
	210
078a55fc	211	unsigned int get_c0_compare_int(void)
d4a67d9d GJ	212	{
	213	return CP0_LEGACY_COMPARE_IRQ;
	214	}
	215
	216	void __init plat_mem_setup(void)
	217	{
03c8c407 AB	218	unsigned long fdt_start;
03c8c407 AB	219
d4a67d9d GJ	220	set_io_port_base(KSEG1);
d4a67d9d GJ	221
03c8c407 AB	222	/* Get the position of the FDT passed by the bootloader */
	223	fdt_start = fw_getenvl("fdt_start");
	224	if (fdt_start)
	225	__dt_setup_arch((void *)KSEG0ADDR(fdt_start));
15f37e15 JG	226	else if (fw_passed_dtb)
15f37e15 JG	227	__dt_setup_arch((void *)KSEG0ADDR(fw_passed_dtb));
03c8c407	228
3a77e0d7 JC	229	ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
	230	AR71XX_RESET_SIZE);
	231	ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
	232	AR71XX_PLL_SIZE);
	233	ath79_detect_sys_type();
	234	ath79_ddr_ctrl_init();
f4fe969d	235
3a77e0d7	236	detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
f4fe969d	237
3a77e0d7	238	_machine_restart = ath79_restart;
d4a67d9d GJ	239	_machine_halt = ath79_halt;
	240	pm_power_off = ath79_halt;
	241	}
	242
3a77e0d7	243	void __init plat_time_init(void)
3bdf1071 AP	244	{
	245	struct device_node *np;
	246	struct clk *clk;
	247	unsigned long cpu_clk_rate;
	248
	249	of_clk_init(NULL);
	250
	251	np = of_get_cpu_node(0, NULL);
	252	if (!np) {
	253	pr_err("Failed to get CPU node\n");
	254	return;
	255	}
	256
	257	clk = of_clk_get(np, 0);
	258	if (IS_ERR(clk)) {
	259	pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk));
	260	return;
	261	}
	262
	263	cpu_clk_rate = clk_get_rate(clk);
	264
	265	pr_info("CPU clock: %lu.%03lu MHz\n",
	266	cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000);
	267
	268	mips_hpt_frequency = cpu_clk_rate / 2;
	269
	270	clk_put(clk);
	271	}
	272
51fa4f89 JC	273	void __init arch_init_irq(void)
	274	{
	275	irqchip_init();
	276	}
	277
03c8c407 AB	278	void __init device_tree_init(void)
	279	{
	280	unflatten_and_copy_device_tree();
	281	}