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1da177e4 LT |
1 | /* |
2 | * | |
3 | * BRIEF MODULE DESCRIPTION | |
4 | * The Descriptor Based DMA channel manager that first appeared | |
5 | * on the Au1550. I started with dma.c, but I think all that is | |
6 | * left is this initial comment :-) | |
7 | * | |
8 | * Copyright 2004 Embedded Edge, LLC | |
9 | * dan@embeddededge.com | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License as published by the | |
13 | * Free Software Foundation; either version 2 of the License, or (at your | |
14 | * option) any later version. | |
15 | * | |
16 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
18 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
19 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
20 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
21 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
22 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
23 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
25 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License along | |
28 | * with this program; if not, write to the Free Software Foundation, Inc., | |
29 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
30 | * | |
31 | */ | |
e3ad1c23 | 32 | |
1da177e4 LT |
33 | #include <linux/kernel.h> |
34 | #include <linux/errno.h> | |
35 | #include <linux/sched.h> | |
36 | #include <linux/slab.h> | |
37 | #include <linux/spinlock.h> | |
38 | #include <linux/string.h> | |
39 | #include <linux/delay.h> | |
40 | #include <linux/interrupt.h> | |
2d32ffa4 | 41 | #include <linux/module.h> |
1da177e4 LT |
42 | #include <asm/mach-au1x00/au1000.h> |
43 | #include <asm/mach-au1x00/au1xxx_dbdma.h> | |
44 | #include <asm/system.h> | |
45 | ||
e3ad1c23 | 46 | |
1da177e4 LT |
47 | #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) |
48 | ||
49 | /* | |
50 | * The Descriptor Based DMA supports up to 16 channels. | |
51 | * | |
52 | * There are 32 devices defined. We keep an internal structure | |
53 | * of devices using these channels, along with additional | |
54 | * information. | |
55 | * | |
56 | * We allocate the descriptors and allow access to them through various | |
57 | * functions. The drivers allocate the data buffers and assign them | |
58 | * to the descriptors. | |
59 | */ | |
2f69ddcc | 60 | static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock); |
1da177e4 LT |
61 | |
62 | /* I couldn't find a macro that did this...... | |
63 | */ | |
64 | #define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1)) | |
65 | ||
e3ad1c23 PP |
66 | static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE; |
67 | static int dbdma_initialized=0; | |
1da177e4 LT |
68 | static void au1xxx_dbdma_init(void); |
69 | ||
1da177e4 LT |
70 | static dbdev_tab_t dbdev_tab[] = { |
71 | #ifdef CONFIG_SOC_AU1550 | |
72 | /* UARTS */ | |
73 | { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 }, | |
74 | { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 }, | |
75 | { DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 }, | |
76 | { DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 }, | |
77 | ||
78 | /* EXT DMA */ | |
79 | { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 }, | |
80 | { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 }, | |
81 | { DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 }, | |
82 | { DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 }, | |
83 | ||
84 | /* USB DEV */ | |
85 | { DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 }, | |
86 | { DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 }, | |
87 | { DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 }, | |
88 | { DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 }, | |
89 | { DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 }, | |
90 | { DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 }, | |
91 | ||
92 | /* PSC 0 */ | |
93 | { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 }, | |
94 | { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 }, | |
95 | ||
96 | /* PSC 1 */ | |
97 | { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 }, | |
98 | { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 }, | |
99 | ||
100 | /* PSC 2 */ | |
101 | { DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 }, | |
102 | { DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 }, | |
103 | ||
104 | /* PSC 3 */ | |
105 | { DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 }, | |
106 | { DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 }, | |
107 | ||
108 | { DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 }, /* PCI */ | |
109 | { DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */ | |
110 | ||
111 | /* MAC 0 */ | |
112 | { DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, | |
113 | { DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, | |
114 | ||
115 | /* MAC 1 */ | |
116 | { DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, | |
117 | { DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, | |
118 | ||
119 | #endif /* CONFIG_SOC_AU1550 */ | |
120 | ||
121 | #ifdef CONFIG_SOC_AU1200 | |
122 | { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 }, | |
123 | { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 }, | |
124 | { DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 }, | |
125 | { DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 }, | |
126 | ||
127 | { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 }, | |
128 | { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 }, | |
129 | ||
130 | { DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, | |
131 | { DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, | |
132 | { DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, | |
133 | { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, | |
134 | ||
e3ad1c23 PP |
135 | { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 }, |
136 | { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 }, | |
137 | { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 }, | |
138 | { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 }, | |
1da177e4 | 139 | |
e3ad1c23 PP |
140 | { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 }, |
141 | { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 }, | |
1da177e4 | 142 | |
13bb199f PP |
143 | { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 }, |
144 | { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x11a0001c, 0, 0 }, | |
1da177e4 LT |
145 | { DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, |
146 | ||
13bb199f PP |
147 | { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 }, |
148 | { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x11b0001c, 0, 0 }, | |
1da177e4 LT |
149 | { DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, |
150 | ||
e3ad1c23 PP |
151 | { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 }, |
152 | { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 }, | |
153 | { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 }, | |
1da177e4 LT |
154 | { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, |
155 | ||
156 | { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, | |
157 | ||
158 | #endif // CONFIG_SOC_AU1200 | |
159 | ||
160 | { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, | |
161 | { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, | |
e3ad1c23 PP |
162 | |
163 | /* Provide 16 user definable device types */ | |
164 | { 0, 0, 0, 0, 0, 0, 0 }, | |
165 | { 0, 0, 0, 0, 0, 0, 0 }, | |
166 | { 0, 0, 0, 0, 0, 0, 0 }, | |
167 | { 0, 0, 0, 0, 0, 0, 0 }, | |
168 | { 0, 0, 0, 0, 0, 0, 0 }, | |
169 | { 0, 0, 0, 0, 0, 0, 0 }, | |
170 | { 0, 0, 0, 0, 0, 0, 0 }, | |
171 | { 0, 0, 0, 0, 0, 0, 0 }, | |
172 | { 0, 0, 0, 0, 0, 0, 0 }, | |
173 | { 0, 0, 0, 0, 0, 0, 0 }, | |
174 | { 0, 0, 0, 0, 0, 0, 0 }, | |
175 | { 0, 0, 0, 0, 0, 0, 0 }, | |
176 | { 0, 0, 0, 0, 0, 0, 0 }, | |
177 | { 0, 0, 0, 0, 0, 0, 0 }, | |
178 | { 0, 0, 0, 0, 0, 0, 0 }, | |
179 | { 0, 0, 0, 0, 0, 0, 0 }, | |
1da177e4 LT |
180 | }; |
181 | ||
182 | #define DBDEV_TAB_SIZE (sizeof(dbdev_tab) / sizeof(dbdev_tab_t)) | |
183 | ||
184 | static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS]; | |
185 | ||
186 | static dbdev_tab_t * | |
49a89efb | 187 | find_dbdev_id(u32 id) |
1da177e4 LT |
188 | { |
189 | int i; | |
190 | dbdev_tab_t *p; | |
191 | for (i = 0; i < DBDEV_TAB_SIZE; ++i) { | |
192 | p = &dbdev_tab[i]; | |
193 | if (p->dev_id == id) | |
194 | return p; | |
195 | } | |
196 | return NULL; | |
197 | } | |
198 | ||
26a940e2 PP |
199 | void * au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp) |
200 | { | |
201 | return phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); | |
202 | } | |
203 | EXPORT_SYMBOL(au1xxx_ddma_get_nextptr_virt); | |
204 | ||
e3ad1c23 PP |
205 | u32 |
206 | au1xxx_ddma_add_device(dbdev_tab_t *dev) | |
207 | { | |
208 | u32 ret = 0; | |
209 | dbdev_tab_t *p=NULL; | |
210 | static u16 new_id=0x1000; | |
211 | ||
212 | p = find_dbdev_id(0); | |
213 | if ( NULL != p ) | |
214 | { | |
215 | memcpy(p, dev, sizeof(dbdev_tab_t)); | |
a3dddd56 | 216 | p->dev_id = DSCR_DEV2CUSTOM_ID(new_id,dev->dev_id); |
e3ad1c23 PP |
217 | ret = p->dev_id; |
218 | new_id++; | |
219 | #if 0 | |
220 | printk("add_device: id:%x flags:%x padd:%x\n", | |
221 | p->dev_id, p->dev_flags, p->dev_physaddr ); | |
222 | #endif | |
223 | } | |
224 | ||
225 | return ret; | |
226 | } | |
227 | EXPORT_SYMBOL(au1xxx_ddma_add_device); | |
228 | ||
1da177e4 LT |
229 | /* Allocate a channel and return a non-zero descriptor if successful. |
230 | */ | |
231 | u32 | |
232 | au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, | |
53e62d3a | 233 | void (*callback)(int, void *), void *callparam) |
1da177e4 LT |
234 | { |
235 | unsigned long flags; | |
236 | u32 used, chan, rv; | |
237 | u32 dcp; | |
238 | int i; | |
239 | dbdev_tab_t *stp, *dtp; | |
240 | chan_tab_t *ctp; | |
e3ad1c23 | 241 | au1x_dma_chan_t *cp; |
1da177e4 LT |
242 | |
243 | /* We do the intialization on the first channel allocation. | |
244 | * We have to wait because of the interrupt handler initialization | |
245 | * which can't be done successfully during board set up. | |
246 | */ | |
247 | if (!dbdma_initialized) | |
248 | au1xxx_dbdma_init(); | |
249 | dbdma_initialized = 1; | |
250 | ||
53e62d3a RB |
251 | if ((stp = find_dbdev_id(srcid)) == NULL) |
252 | return 0; | |
253 | if ((dtp = find_dbdev_id(destid)) == NULL) | |
254 | return 0; | |
1da177e4 LT |
255 | |
256 | used = 0; | |
257 | rv = 0; | |
258 | ||
259 | /* Check to see if we can get both channels. | |
260 | */ | |
261 | spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags); | |
262 | if (!(stp->dev_flags & DEV_FLAGS_INUSE) || | |
263 | (stp->dev_flags & DEV_FLAGS_ANYUSE)) { | |
a3dddd56 | 264 | /* Got source */ |
1da177e4 LT |
265 | stp->dev_flags |= DEV_FLAGS_INUSE; |
266 | if (!(dtp->dev_flags & DEV_FLAGS_INUSE) || | |
267 | (dtp->dev_flags & DEV_FLAGS_ANYUSE)) { | |
268 | /* Got destination */ | |
269 | dtp->dev_flags |= DEV_FLAGS_INUSE; | |
270 | } | |
271 | else { | |
272 | /* Can't get dest. Release src. | |
273 | */ | |
274 | stp->dev_flags &= ~DEV_FLAGS_INUSE; | |
275 | used++; | |
276 | } | |
277 | } | |
278 | else { | |
279 | used++; | |
280 | } | |
281 | spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags); | |
282 | ||
283 | if (!used) { | |
284 | /* Let's see if we can allocate a channel for it. | |
285 | */ | |
286 | ctp = NULL; | |
287 | chan = 0; | |
288 | spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags); | |
289 | for (i=0; i<NUM_DBDMA_CHANS; i++) { | |
290 | if (chan_tab_ptr[i] == NULL) { | |
291 | /* If kmalloc fails, it is caught below same | |
292 | * as a channel not available. | |
293 | */ | |
c0613894 | 294 | ctp = kmalloc(sizeof(chan_tab_t), GFP_ATOMIC); |
1da177e4 | 295 | chan_tab_ptr[i] = ctp; |
1da177e4 LT |
296 | break; |
297 | } | |
298 | } | |
299 | spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags); | |
300 | ||
301 | if (ctp != NULL) { | |
302 | memset(ctp, 0, sizeof(chan_tab_t)); | |
e3ad1c23 | 303 | ctp->chan_index = chan = i; |
1da177e4 LT |
304 | dcp = DDMA_CHANNEL_BASE; |
305 | dcp += (0x0100 * chan); | |
306 | ctp->chan_ptr = (au1x_dma_chan_t *)dcp; | |
e3ad1c23 | 307 | cp = (au1x_dma_chan_t *)dcp; |
1da177e4 LT |
308 | ctp->chan_src = stp; |
309 | ctp->chan_dest = dtp; | |
310 | ctp->chan_callback = callback; | |
311 | ctp->chan_callparam = callparam; | |
312 | ||
313 | /* Initialize channel configuration. | |
314 | */ | |
315 | i = 0; | |
316 | if (stp->dev_intlevel) | |
317 | i |= DDMA_CFG_SED; | |
318 | if (stp->dev_intpolarity) | |
319 | i |= DDMA_CFG_SP; | |
320 | if (dtp->dev_intlevel) | |
321 | i |= DDMA_CFG_DED; | |
322 | if (dtp->dev_intpolarity) | |
323 | i |= DDMA_CFG_DP; | |
e3ad1c23 PP |
324 | if ((stp->dev_flags & DEV_FLAGS_SYNC) || |
325 | (dtp->dev_flags & DEV_FLAGS_SYNC)) | |
326 | i |= DDMA_CFG_SYNC; | |
1da177e4 LT |
327 | cp->ddma_cfg = i; |
328 | au_sync(); | |
329 | ||
330 | /* Return a non-zero value that can be used to | |
331 | * find the channel information in subsequent | |
332 | * operations. | |
333 | */ | |
334 | rv = (u32)(&chan_tab_ptr[chan]); | |
335 | } | |
336 | else { | |
e3ad1c23 | 337 | /* Release devices */ |
1da177e4 LT |
338 | stp->dev_flags &= ~DEV_FLAGS_INUSE; |
339 | dtp->dev_flags &= ~DEV_FLAGS_INUSE; | |
340 | } | |
341 | } | |
342 | return rv; | |
343 | } | |
e3ad1c23 | 344 | EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc); |
1da177e4 LT |
345 | |
346 | /* Set the device width if source or destination is a FIFO. | |
347 | * Should be 8, 16, or 32 bits. | |
348 | */ | |
349 | u32 | |
350 | au1xxx_dbdma_set_devwidth(u32 chanid, int bits) | |
351 | { | |
352 | u32 rv; | |
353 | chan_tab_t *ctp; | |
354 | dbdev_tab_t *stp, *dtp; | |
355 | ||
356 | ctp = *((chan_tab_t **)chanid); | |
357 | stp = ctp->chan_src; | |
358 | dtp = ctp->chan_dest; | |
359 | rv = 0; | |
360 | ||
361 | if (stp->dev_flags & DEV_FLAGS_IN) { /* Source in fifo */ | |
362 | rv = stp->dev_devwidth; | |
363 | stp->dev_devwidth = bits; | |
364 | } | |
365 | if (dtp->dev_flags & DEV_FLAGS_OUT) { /* Destination out fifo */ | |
366 | rv = dtp->dev_devwidth; | |
367 | dtp->dev_devwidth = bits; | |
368 | } | |
369 | ||
370 | return rv; | |
371 | } | |
e3ad1c23 | 372 | EXPORT_SYMBOL(au1xxx_dbdma_set_devwidth); |
1da177e4 LT |
373 | |
374 | /* Allocate a descriptor ring, initializing as much as possible. | |
375 | */ | |
376 | u32 | |
377 | au1xxx_dbdma_ring_alloc(u32 chanid, int entries) | |
378 | { | |
379 | int i; | |
380 | u32 desc_base, srcid, destid; | |
381 | u32 cmd0, cmd1, src1, dest1; | |
382 | u32 src0, dest0; | |
383 | chan_tab_t *ctp; | |
384 | dbdev_tab_t *stp, *dtp; | |
385 | au1x_ddma_desc_t *dp; | |
386 | ||
387 | /* I guess we could check this to be within the | |
388 | * range of the table...... | |
389 | */ | |
390 | ctp = *((chan_tab_t **)chanid); | |
391 | stp = ctp->chan_src; | |
392 | dtp = ctp->chan_dest; | |
393 | ||
394 | /* The descriptors must be 32-byte aligned. There is a | |
395 | * possibility the allocation will give us such an address, | |
396 | * and if we try that first we are likely to not waste larger | |
397 | * slabs of memory. | |
398 | */ | |
e3ad1c23 PP |
399 | desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t), |
400 | GFP_KERNEL|GFP_DMA); | |
1da177e4 LT |
401 | if (desc_base == 0) |
402 | return 0; | |
403 | ||
404 | if (desc_base & 0x1f) { | |
405 | /* Lost....do it again, allocate extra, and round | |
406 | * the address base. | |
407 | */ | |
408 | kfree((const void *)desc_base); | |
409 | i = entries * sizeof(au1x_ddma_desc_t); | |
410 | i += (sizeof(au1x_ddma_desc_t) - 1); | |
e3ad1c23 | 411 | if ((desc_base = (u32)kmalloc(i, GFP_KERNEL|GFP_DMA)) == 0) |
1da177e4 LT |
412 | return 0; |
413 | ||
414 | desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t)); | |
415 | } | |
416 | dp = (au1x_ddma_desc_t *)desc_base; | |
417 | ||
418 | /* Keep track of the base descriptor. | |
419 | */ | |
420 | ctp->chan_desc_base = dp; | |
421 | ||
422 | /* Initialize the rings with as much information as we know. | |
423 | */ | |
424 | srcid = stp->dev_id; | |
425 | destid = dtp->dev_id; | |
426 | ||
427 | cmd0 = cmd1 = src1 = dest1 = 0; | |
428 | src0 = dest0 = 0; | |
429 | ||
430 | cmd0 |= DSCR_CMD0_SID(srcid); | |
431 | cmd0 |= DSCR_CMD0_DID(destid); | |
432 | cmd0 |= DSCR_CMD0_IE | DSCR_CMD0_CV; | |
13bb199f PP |
433 | cmd0 |= DSCR_CMD0_ST(DSCR_CMD0_ST_NOCHANGE); |
434 | ||
435 | /* is it mem to mem transfer? */ | |
436 | if(((DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_THROTTLE) || (DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_ALWAYS)) && | |
437 | ((DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_THROTTLE) || (DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_ALWAYS))) { | |
438 | cmd0 |= DSCR_CMD0_MEM; | |
439 | } | |
1da177e4 LT |
440 | |
441 | switch (stp->dev_devwidth) { | |
442 | case 8: | |
443 | cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_BYTE); | |
444 | break; | |
445 | case 16: | |
446 | cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_HALFWORD); | |
447 | break; | |
448 | case 32: | |
449 | default: | |
450 | cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_WORD); | |
451 | break; | |
452 | } | |
453 | ||
454 | switch (dtp->dev_devwidth) { | |
455 | case 8: | |
456 | cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_BYTE); | |
457 | break; | |
458 | case 16: | |
459 | cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_HALFWORD); | |
460 | break; | |
461 | case 32: | |
462 | default: | |
463 | cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_WORD); | |
464 | break; | |
465 | } | |
466 | ||
467 | /* If the device is marked as an in/out FIFO, ensure it is | |
468 | * set non-coherent. | |
469 | */ | |
470 | if (stp->dev_flags & DEV_FLAGS_IN) | |
471 | cmd0 |= DSCR_CMD0_SN; /* Source in fifo */ | |
472 | if (dtp->dev_flags & DEV_FLAGS_OUT) | |
473 | cmd0 |= DSCR_CMD0_DN; /* Destination out fifo */ | |
474 | ||
475 | /* Set up source1. For now, assume no stride and increment. | |
476 | * A channel attribute update can change this later. | |
477 | */ | |
478 | switch (stp->dev_tsize) { | |
479 | case 1: | |
480 | src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE1); | |
481 | break; | |
482 | case 2: | |
483 | src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE2); | |
484 | break; | |
485 | case 4: | |
486 | src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE4); | |
487 | break; | |
488 | case 8: | |
489 | default: | |
490 | src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE8); | |
491 | break; | |
492 | } | |
493 | ||
494 | /* If source input is fifo, set static address. | |
495 | */ | |
496 | if (stp->dev_flags & DEV_FLAGS_IN) { | |
e3ad1c23 PP |
497 | if ( stp->dev_flags & DEV_FLAGS_BURSTABLE ) |
498 | src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST); | |
499 | else | |
1da177e4 | 500 | src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC); |
e3ad1c23 | 501 | |
1da177e4 | 502 | } |
e3ad1c23 PP |
503 | if (stp->dev_physaddr) |
504 | src0 = stp->dev_physaddr; | |
1da177e4 LT |
505 | |
506 | /* Set up dest1. For now, assume no stride and increment. | |
507 | * A channel attribute update can change this later. | |
508 | */ | |
509 | switch (dtp->dev_tsize) { | |
510 | case 1: | |
511 | dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE1); | |
512 | break; | |
513 | case 2: | |
514 | dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE2); | |
515 | break; | |
516 | case 4: | |
517 | dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE4); | |
518 | break; | |
519 | case 8: | |
520 | default: | |
521 | dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE8); | |
522 | break; | |
523 | } | |
524 | ||
525 | /* If destination output is fifo, set static address. | |
526 | */ | |
527 | if (dtp->dev_flags & DEV_FLAGS_OUT) { | |
e3ad1c23 PP |
528 | if ( dtp->dev_flags & DEV_FLAGS_BURSTABLE ) |
529 | dest1 |= DSCR_DEST1_DAM(DSCR_xAM_BURST); | |
530 | else | |
1da177e4 LT |
531 | dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC); |
532 | } | |
e3ad1c23 PP |
533 | if (dtp->dev_physaddr) |
534 | dest0 = dtp->dev_physaddr; | |
1da177e4 | 535 | |
e3ad1c23 PP |
536 | #if 0 |
537 | printk("did:%x sid:%x cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n", | |
538 | dtp->dev_id, stp->dev_id, cmd0, cmd1, src0, src1, dest0, dest1 ); | |
539 | #endif | |
1da177e4 LT |
540 | for (i=0; i<entries; i++) { |
541 | dp->dscr_cmd0 = cmd0; | |
542 | dp->dscr_cmd1 = cmd1; | |
543 | dp->dscr_source0 = src0; | |
544 | dp->dscr_source1 = src1; | |
545 | dp->dscr_dest0 = dest0; | |
546 | dp->dscr_dest1 = dest1; | |
547 | dp->dscr_stat = 0; | |
13bb199f PP |
548 | dp->sw_context = 0; |
549 | dp->sw_status = 0; | |
1da177e4 LT |
550 | dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1)); |
551 | dp++; | |
552 | } | |
553 | ||
554 | /* Make last descrptor point to the first. | |
555 | */ | |
556 | dp--; | |
557 | dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(ctp->chan_desc_base)); | |
558 | ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base; | |
559 | ||
560 | return (u32)(ctp->chan_desc_base); | |
561 | } | |
e3ad1c23 | 562 | EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc); |
1da177e4 LT |
563 | |
564 | /* Put a source buffer into the DMA ring. | |
565 | * This updates the source pointer and byte count. Normally used | |
566 | * for memory to fifo transfers. | |
567 | */ | |
568 | u32 | |
e3ad1c23 | 569 | _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags) |
1da177e4 LT |
570 | { |
571 | chan_tab_t *ctp; | |
572 | au1x_ddma_desc_t *dp; | |
573 | ||
574 | /* I guess we could check this to be within the | |
575 | * range of the table...... | |
576 | */ | |
577 | ctp = *((chan_tab_t **)chanid); | |
578 | ||
579 | /* We should have multiple callers for a particular channel, | |
580 | * an interrupt doesn't affect this pointer nor the descriptor, | |
581 | * so no locking should be needed. | |
582 | */ | |
583 | dp = ctp->put_ptr; | |
584 | ||
585 | /* If the descriptor is valid, we are way ahead of the DMA | |
586 | * engine, so just return an error condition. | |
587 | */ | |
588 | if (dp->dscr_cmd0 & DSCR_CMD0_V) { | |
589 | return 0; | |
590 | } | |
591 | ||
592 | /* Load up buffer address and byte count. | |
593 | */ | |
594 | dp->dscr_source0 = virt_to_phys(buf); | |
595 | dp->dscr_cmd1 = nbytes; | |
e3ad1c23 PP |
596 | /* Check flags */ |
597 | if (flags & DDMA_FLAGS_IE) | |
598 | dp->dscr_cmd0 |= DSCR_CMD0_IE; | |
599 | if (flags & DDMA_FLAGS_NOIE) | |
600 | dp->dscr_cmd0 &= ~DSCR_CMD0_IE; | |
1da177e4 | 601 | |
e3ad1c23 PP |
602 | /* |
603 | * There is an errata on the Au1200/Au1550 parts that could result | |
604 | * in "stale" data being DMA'd. It has to do with the snoop logic on | |
605 | * the dache eviction buffer. NONCOHERENT_IO is on by default for | |
606 | * these parts. If it is fixedin the future, these dma_cache_inv will | |
607 | * just be nothing more than empty macros. See io.h. | |
608 | * */ | |
2d32ffa4 | 609 | dma_cache_wback_inv((unsigned long)buf, nbytes); |
e3ad1c23 PP |
610 | dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ |
611 | au_sync(); | |
2d32ffa4 | 612 | dma_cache_wback_inv((unsigned long)dp, sizeof(dp)); |
e3ad1c23 PP |
613 | ctp->chan_ptr->ddma_dbell = 0; |
614 | ||
13bb199f PP |
615 | /* Get next descriptor pointer. |
616 | */ | |
617 | ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); | |
618 | ||
1da177e4 LT |
619 | /* return something not zero. |
620 | */ | |
621 | return nbytes; | |
622 | } | |
e3ad1c23 | 623 | EXPORT_SYMBOL(_au1xxx_dbdma_put_source); |
1da177e4 LT |
624 | |
625 | /* Put a destination buffer into the DMA ring. | |
626 | * This updates the destination pointer and byte count. Normally used | |
627 | * to place an empty buffer into the ring for fifo to memory transfers. | |
628 | */ | |
629 | u32 | |
e3ad1c23 | 630 | _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags) |
1da177e4 LT |
631 | { |
632 | chan_tab_t *ctp; | |
633 | au1x_ddma_desc_t *dp; | |
634 | ||
635 | /* I guess we could check this to be within the | |
636 | * range of the table...... | |
637 | */ | |
638 | ctp = *((chan_tab_t **)chanid); | |
639 | ||
640 | /* We should have multiple callers for a particular channel, | |
641 | * an interrupt doesn't affect this pointer nor the descriptor, | |
642 | * so no locking should be needed. | |
643 | */ | |
644 | dp = ctp->put_ptr; | |
645 | ||
646 | /* If the descriptor is valid, we are way ahead of the DMA | |
647 | * engine, so just return an error condition. | |
648 | */ | |
649 | if (dp->dscr_cmd0 & DSCR_CMD0_V) | |
650 | return 0; | |
651 | ||
e3ad1c23 PP |
652 | /* Load up buffer address and byte count */ |
653 | ||
654 | /* Check flags */ | |
655 | if (flags & DDMA_FLAGS_IE) | |
656 | dp->dscr_cmd0 |= DSCR_CMD0_IE; | |
657 | if (flags & DDMA_FLAGS_NOIE) | |
658 | dp->dscr_cmd0 &= ~DSCR_CMD0_IE; | |
659 | ||
1da177e4 LT |
660 | dp->dscr_dest0 = virt_to_phys(buf); |
661 | dp->dscr_cmd1 = nbytes; | |
e3ad1c23 PP |
662 | #if 0 |
663 | printk("cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n", | |
664 | dp->dscr_cmd0, dp->dscr_cmd1, dp->dscr_source0, | |
665 | dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1 ); | |
666 | #endif | |
667 | /* | |
668 | * There is an errata on the Au1200/Au1550 parts that could result in | |
669 | * "stale" data being DMA'd. It has to do with the snoop logic on the | |
670 | * dache eviction buffer. NONCOHERENT_IO is on by default for these | |
671 | * parts. If it is fixedin the future, these dma_cache_inv will just | |
672 | * be nothing more than empty macros. See io.h. | |
673 | * */ | |
2d32ffa4 | 674 | dma_cache_inv((unsigned long)buf,nbytes); |
1da177e4 | 675 | dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ |
e3ad1c23 | 676 | au_sync(); |
2d32ffa4 | 677 | dma_cache_wback_inv((unsigned long)dp, sizeof(dp)); |
e3ad1c23 | 678 | ctp->chan_ptr->ddma_dbell = 0; |
1da177e4 LT |
679 | |
680 | /* Get next descriptor pointer. | |
681 | */ | |
682 | ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); | |
683 | ||
684 | /* return something not zero. | |
685 | */ | |
686 | return nbytes; | |
687 | } | |
e3ad1c23 | 688 | EXPORT_SYMBOL(_au1xxx_dbdma_put_dest); |
1da177e4 LT |
689 | |
690 | /* Get a destination buffer into the DMA ring. | |
691 | * Normally used to get a full buffer from the ring during fifo | |
692 | * to memory transfers. This does not set the valid bit, you will | |
693 | * have to put another destination buffer to keep the DMA going. | |
694 | */ | |
695 | u32 | |
696 | au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes) | |
697 | { | |
698 | chan_tab_t *ctp; | |
699 | au1x_ddma_desc_t *dp; | |
700 | u32 rv; | |
701 | ||
702 | /* I guess we could check this to be within the | |
703 | * range of the table...... | |
704 | */ | |
705 | ctp = *((chan_tab_t **)chanid); | |
706 | ||
707 | /* We should have multiple callers for a particular channel, | |
708 | * an interrupt doesn't affect this pointer nor the descriptor, | |
709 | * so no locking should be needed. | |
710 | */ | |
711 | dp = ctp->get_ptr; | |
712 | ||
713 | /* If the descriptor is valid, we are way ahead of the DMA | |
714 | * engine, so just return an error condition. | |
715 | */ | |
716 | if (dp->dscr_cmd0 & DSCR_CMD0_V) | |
717 | return 0; | |
718 | ||
719 | /* Return buffer address and byte count. | |
720 | */ | |
721 | *buf = (void *)(phys_to_virt(dp->dscr_dest0)); | |
722 | *nbytes = dp->dscr_cmd1; | |
723 | rv = dp->dscr_stat; | |
724 | ||
725 | /* Get next descriptor pointer. | |
726 | */ | |
727 | ctp->get_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); | |
728 | ||
729 | /* return something not zero. | |
730 | */ | |
731 | return rv; | |
732 | } | |
733 | ||
3e2c6ef3 DP |
734 | EXPORT_SYMBOL_GPL(au1xxx_dbdma_get_dest); |
735 | ||
1da177e4 LT |
736 | void |
737 | au1xxx_dbdma_stop(u32 chanid) | |
738 | { | |
739 | chan_tab_t *ctp; | |
e3ad1c23 | 740 | au1x_dma_chan_t *cp; |
1da177e4 LT |
741 | int halt_timeout = 0; |
742 | ||
743 | ctp = *((chan_tab_t **)chanid); | |
744 | ||
745 | cp = ctp->chan_ptr; | |
746 | cp->ddma_cfg &= ~DDMA_CFG_EN; /* Disable channel */ | |
747 | au_sync(); | |
748 | while (!(cp->ddma_stat & DDMA_STAT_H)) { | |
749 | udelay(1); | |
750 | halt_timeout++; | |
751 | if (halt_timeout > 100) { | |
752 | printk("warning: DMA channel won't halt\n"); | |
753 | break; | |
754 | } | |
755 | } | |
756 | /* clear current desc valid and doorbell */ | |
757 | cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V); | |
758 | au_sync(); | |
759 | } | |
e3ad1c23 | 760 | EXPORT_SYMBOL(au1xxx_dbdma_stop); |
1da177e4 LT |
761 | |
762 | /* Start using the current descriptor pointer. If the dbdma encounters | |
763 | * a not valid descriptor, it will stop. In this case, we can just | |
764 | * continue by adding a buffer to the list and starting again. | |
765 | */ | |
766 | void | |
767 | au1xxx_dbdma_start(u32 chanid) | |
768 | { | |
769 | chan_tab_t *ctp; | |
e3ad1c23 | 770 | au1x_dma_chan_t *cp; |
1da177e4 LT |
771 | |
772 | ctp = *((chan_tab_t **)chanid); | |
1da177e4 LT |
773 | cp = ctp->chan_ptr; |
774 | cp->ddma_desptr = virt_to_phys(ctp->cur_ptr); | |
775 | cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */ | |
776 | au_sync(); | |
e3ad1c23 | 777 | cp->ddma_dbell = 0; |
1da177e4 LT |
778 | au_sync(); |
779 | } | |
e3ad1c23 | 780 | EXPORT_SYMBOL(au1xxx_dbdma_start); |
1da177e4 LT |
781 | |
782 | void | |
783 | au1xxx_dbdma_reset(u32 chanid) | |
784 | { | |
785 | chan_tab_t *ctp; | |
786 | au1x_ddma_desc_t *dp; | |
787 | ||
788 | au1xxx_dbdma_stop(chanid); | |
789 | ||
790 | ctp = *((chan_tab_t **)chanid); | |
791 | ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base; | |
792 | ||
793 | /* Run through the descriptors and reset the valid indicator. | |
794 | */ | |
795 | dp = ctp->chan_desc_base; | |
796 | ||
797 | do { | |
798 | dp->dscr_cmd0 &= ~DSCR_CMD0_V; | |
e3ad1c23 PP |
799 | /* reset our SW status -- this is used to determine |
800 | * if a descriptor is in use by upper level SW. Since | |
801 | * posting can reset 'V' bit. | |
802 | */ | |
803 | dp->sw_status = 0; | |
1da177e4 LT |
804 | dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); |
805 | } while (dp != ctp->chan_desc_base); | |
806 | } | |
e3ad1c23 | 807 | EXPORT_SYMBOL(au1xxx_dbdma_reset); |
1da177e4 LT |
808 | |
809 | u32 | |
810 | au1xxx_get_dma_residue(u32 chanid) | |
811 | { | |
812 | chan_tab_t *ctp; | |
e3ad1c23 | 813 | au1x_dma_chan_t *cp; |
1da177e4 LT |
814 | u32 rv; |
815 | ||
816 | ctp = *((chan_tab_t **)chanid); | |
817 | cp = ctp->chan_ptr; | |
818 | ||
819 | /* This is only valid if the channel is stopped. | |
820 | */ | |
821 | rv = cp->ddma_bytecnt; | |
822 | au_sync(); | |
823 | ||
824 | return rv; | |
825 | } | |
826 | ||
3e2c6ef3 DP |
827 | EXPORT_SYMBOL_GPL(au1xxx_get_dma_residue); |
828 | ||
1da177e4 LT |
829 | void |
830 | au1xxx_dbdma_chan_free(u32 chanid) | |
831 | { | |
832 | chan_tab_t *ctp; | |
833 | dbdev_tab_t *stp, *dtp; | |
834 | ||
835 | ctp = *((chan_tab_t **)chanid); | |
836 | stp = ctp->chan_src; | |
837 | dtp = ctp->chan_dest; | |
838 | ||
839 | au1xxx_dbdma_stop(chanid); | |
840 | ||
2d32ffa4 | 841 | kfree((void *)ctp->chan_desc_base); |
1da177e4 LT |
842 | |
843 | stp->dev_flags &= ~DEV_FLAGS_INUSE; | |
844 | dtp->dev_flags &= ~DEV_FLAGS_INUSE; | |
845 | chan_tab_ptr[ctp->chan_index] = NULL; | |
846 | ||
847 | kfree(ctp); | |
848 | } | |
e3ad1c23 | 849 | EXPORT_SYMBOL(au1xxx_dbdma_chan_free); |
1da177e4 | 850 | |
2d32ffa4 | 851 | static irqreturn_t |
36d98e79 | 852 | dbdma_interrupt(int irq, void *dev_id) |
1da177e4 | 853 | { |
2d32ffa4 PP |
854 | u32 intstat; |
855 | u32 chan_index; | |
1da177e4 LT |
856 | chan_tab_t *ctp; |
857 | au1x_ddma_desc_t *dp; | |
e3ad1c23 | 858 | au1x_dma_chan_t *cp; |
1da177e4 LT |
859 | |
860 | intstat = dbdma_gptr->ddma_intstat; | |
861 | au_sync(); | |
862 | chan_index = au_ffs(intstat) - 1; | |
863 | ||
864 | ctp = chan_tab_ptr[chan_index]; | |
865 | cp = ctp->chan_ptr; | |
866 | dp = ctp->cur_ptr; | |
867 | ||
868 | /* Reset interrupt. | |
869 | */ | |
870 | cp->ddma_irq = 0; | |
871 | au_sync(); | |
872 | ||
873 | if (ctp->chan_callback) | |
53e62d3a | 874 | (ctp->chan_callback)(irq, ctp->chan_callparam); |
1da177e4 LT |
875 | |
876 | ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); | |
2d32ffa4 | 877 | return IRQ_RETVAL(1); |
1da177e4 LT |
878 | } |
879 | ||
e3ad1c23 | 880 | static void au1xxx_dbdma_init(void) |
1da177e4 | 881 | { |
e3ad1c23 PP |
882 | int irq_nr; |
883 | ||
1da177e4 LT |
884 | dbdma_gptr->ddma_config = 0; |
885 | dbdma_gptr->ddma_throttle = 0; | |
886 | dbdma_gptr->ddma_inten = 0xffff; | |
887 | au_sync(); | |
888 | ||
e3ad1c23 PP |
889 | #if defined(CONFIG_SOC_AU1550) |
890 | irq_nr = AU1550_DDMA_INT; | |
891 | #elif defined(CONFIG_SOC_AU1200) | |
892 | irq_nr = AU1200_DDMA_INT; | |
893 | #else | |
894 | #error Unknown Au1x00 SOC | |
895 | #endif | |
896 | ||
f40298fd | 897 | if (request_irq(irq_nr, dbdma_interrupt, IRQF_DISABLED, |
1da177e4 LT |
898 | "Au1xxx dbdma", (void *)dbdma_gptr)) |
899 | printk("Can't get 1550 dbdma irq"); | |
900 | } | |
901 | ||
902 | void | |
903 | au1xxx_dbdma_dump(u32 chanid) | |
904 | { | |
905 | chan_tab_t *ctp; | |
906 | au1x_ddma_desc_t *dp; | |
907 | dbdev_tab_t *stp, *dtp; | |
e3ad1c23 PP |
908 | au1x_dma_chan_t *cp; |
909 | u32 i = 0; | |
1da177e4 LT |
910 | |
911 | ctp = *((chan_tab_t **)chanid); | |
912 | stp = ctp->chan_src; | |
913 | dtp = ctp->chan_dest; | |
914 | cp = ctp->chan_ptr; | |
915 | ||
916 | printk("Chan %x, stp %x (dev %d) dtp %x (dev %d) \n", | |
917 | (u32)ctp, (u32)stp, stp - dbdev_tab, (u32)dtp, dtp - dbdev_tab); | |
918 | printk("desc base %x, get %x, put %x, cur %x\n", | |
919 | (u32)(ctp->chan_desc_base), (u32)(ctp->get_ptr), | |
920 | (u32)(ctp->put_ptr), (u32)(ctp->cur_ptr)); | |
921 | ||
922 | printk("dbdma chan %x\n", (u32)cp); | |
923 | printk("cfg %08x, desptr %08x, statptr %08x\n", | |
924 | cp->ddma_cfg, cp->ddma_desptr, cp->ddma_statptr); | |
925 | printk("dbell %08x, irq %08x, stat %08x, bytecnt %08x\n", | |
926 | cp->ddma_dbell, cp->ddma_irq, cp->ddma_stat, cp->ddma_bytecnt); | |
927 | ||
928 | ||
929 | /* Run through the descriptors | |
930 | */ | |
931 | dp = ctp->chan_desc_base; | |
932 | ||
933 | do { | |
e3ad1c23 PP |
934 | printk("Dp[%d]= %08x, cmd0 %08x, cmd1 %08x\n", |
935 | i++, (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1); | |
936 | printk("src0 %08x, src1 %08x, dest0 %08x, dest1 %08x\n", | |
937 | dp->dscr_source0, dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1); | |
938 | printk("stat %08x, nxtptr %08x\n", | |
939 | dp->dscr_stat, dp->dscr_nxtptr); | |
1da177e4 LT |
940 | dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); |
941 | } while (dp != ctp->chan_desc_base); | |
942 | } | |
943 | ||
e3ad1c23 PP |
944 | /* Put a descriptor into the DMA ring. |
945 | * This updates the source/destination pointers and byte count. | |
946 | */ | |
947 | u32 | |
948 | au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr ) | |
949 | { | |
950 | chan_tab_t *ctp; | |
951 | au1x_ddma_desc_t *dp; | |
952 | u32 nbytes=0; | |
953 | ||
954 | /* I guess we could check this to be within the | |
955 | * range of the table...... | |
956 | */ | |
957 | ctp = *((chan_tab_t **)chanid); | |
958 | ||
959 | /* We should have multiple callers for a particular channel, | |
960 | * an interrupt doesn't affect this pointer nor the descriptor, | |
961 | * so no locking should be needed. | |
962 | */ | |
963 | dp = ctp->put_ptr; | |
964 | ||
965 | /* If the descriptor is valid, we are way ahead of the DMA | |
966 | * engine, so just return an error condition. | |
967 | */ | |
968 | if (dp->dscr_cmd0 & DSCR_CMD0_V) | |
969 | return 0; | |
970 | ||
971 | /* Load up buffer addresses and byte count. | |
972 | */ | |
973 | dp->dscr_dest0 = dscr->dscr_dest0; | |
974 | dp->dscr_source0 = dscr->dscr_source0; | |
975 | dp->dscr_dest1 = dscr->dscr_dest1; | |
976 | dp->dscr_source1 = dscr->dscr_source1; | |
977 | dp->dscr_cmd1 = dscr->dscr_cmd1; | |
978 | nbytes = dscr->dscr_cmd1; | |
979 | /* Allow the caller to specifiy if an interrupt is generated */ | |
980 | dp->dscr_cmd0 &= ~DSCR_CMD0_IE; | |
981 | dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V; | |
982 | ctp->chan_ptr->ddma_dbell = 0; | |
983 | ||
984 | /* Get next descriptor pointer. | |
985 | */ | |
986 | ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); | |
987 | ||
988 | /* return something not zero. | |
989 | */ | |
990 | return nbytes; | |
991 | } | |
992 | ||
1da177e4 LT |
993 | #endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */ |
994 |