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1da177e4 LT |
1 | /* |
2 | * | |
3 | * BRIEF MODULE DESCRIPTION | |
4 | * The Descriptor Based DMA channel manager that first appeared | |
5 | * on the Au1550. I started with dma.c, but I think all that is | |
6 | * left is this initial comment :-) | |
7 | * | |
8 | * Copyright 2004 Embedded Edge, LLC | |
9 | * dan@embeddededge.com | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License as published by the | |
13 | * Free Software Foundation; either version 2 of the License, or (at your | |
14 | * option) any later version. | |
15 | * | |
16 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
18 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
19 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
20 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
21 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
22 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
23 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
25 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License along | |
28 | * with this program; if not, write to the Free Software Foundation, Inc., | |
29 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
30 | * | |
31 | */ | |
e3ad1c23 | 32 | |
1da177e4 | 33 | #include <linux/kernel.h> |
1da177e4 LT |
34 | #include <linux/slab.h> |
35 | #include <linux/spinlock.h> | |
1da177e4 | 36 | #include <linux/interrupt.h> |
2d32ffa4 | 37 | #include <linux/module.h> |
1da177e4 LT |
38 | #include <asm/mach-au1x00/au1000.h> |
39 | #include <asm/mach-au1x00/au1xxx_dbdma.h> | |
e3ad1c23 | 40 | |
1da177e4 LT |
41 | #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) |
42 | ||
43 | /* | |
44 | * The Descriptor Based DMA supports up to 16 channels. | |
45 | * | |
46 | * There are 32 devices defined. We keep an internal structure | |
47 | * of devices using these channels, along with additional | |
48 | * information. | |
49 | * | |
50 | * We allocate the descriptors and allow access to them through various | |
51 | * functions. The drivers allocate the data buffers and assign them | |
52 | * to the descriptors. | |
53 | */ | |
2f69ddcc | 54 | static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock); |
1da177e4 | 55 | |
c1dcb14e | 56 | /* I couldn't find a macro that did this... */ |
1da177e4 LT |
57 | #define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1)) |
58 | ||
e3ad1c23 | 59 | static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE; |
c1dcb14e | 60 | static int dbdma_initialized; |
1da177e4 LT |
61 | static void au1xxx_dbdma_init(void); |
62 | ||
1da177e4 LT |
63 | static dbdev_tab_t dbdev_tab[] = { |
64 | #ifdef CONFIG_SOC_AU1550 | |
65 | /* UARTS */ | |
66 | { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 }, | |
67 | { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 }, | |
68 | { DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 }, | |
69 | { DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 }, | |
70 | ||
71 | /* EXT DMA */ | |
72 | { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 }, | |
73 | { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 }, | |
74 | { DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 }, | |
75 | { DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 }, | |
76 | ||
77 | /* USB DEV */ | |
78 | { DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 }, | |
79 | { DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 }, | |
80 | { DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 }, | |
81 | { DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 }, | |
82 | { DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 }, | |
83 | { DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 }, | |
84 | ||
85 | /* PSC 0 */ | |
86 | { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 }, | |
87 | { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 }, | |
88 | ||
89 | /* PSC 1 */ | |
90 | { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 }, | |
91 | { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 }, | |
92 | ||
93 | /* PSC 2 */ | |
94 | { DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 }, | |
95 | { DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 }, | |
96 | ||
97 | /* PSC 3 */ | |
98 | { DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 }, | |
99 | { DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 }, | |
100 | ||
101 | { DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 }, /* PCI */ | |
102 | { DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */ | |
103 | ||
104 | /* MAC 0 */ | |
105 | { DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, | |
106 | { DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, | |
107 | ||
108 | /* MAC 1 */ | |
109 | { DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, | |
110 | { DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 }, | |
111 | ||
112 | #endif /* CONFIG_SOC_AU1550 */ | |
113 | ||
114 | #ifdef CONFIG_SOC_AU1200 | |
115 | { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 }, | |
116 | { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 }, | |
117 | { DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 }, | |
118 | { DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 }, | |
119 | ||
120 | { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 }, | |
121 | { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 }, | |
122 | ||
123 | { DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, | |
124 | { DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, | |
125 | { DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, | |
126 | { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, | |
127 | ||
e3ad1c23 PP |
128 | { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 }, |
129 | { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 }, | |
130 | { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 }, | |
131 | { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 }, | |
1da177e4 | 132 | |
e3ad1c23 PP |
133 | { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 }, |
134 | { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 }, | |
1da177e4 | 135 | |
13bb199f PP |
136 | { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x11a0001c, 0, 0 }, |
137 | { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x11a0001c, 0, 0 }, | |
1da177e4 LT |
138 | { DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, |
139 | ||
13bb199f PP |
140 | { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x11b0001c, 0, 0 }, |
141 | { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x11b0001c, 0, 0 }, | |
1da177e4 LT |
142 | { DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, |
143 | ||
e3ad1c23 PP |
144 | { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 }, |
145 | { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 }, | |
146 | { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 }, | |
1da177e4 LT |
147 | { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, |
148 | ||
149 | { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, | |
150 | ||
c1dcb14e | 151 | #endif /* CONFIG_SOC_AU1200 */ |
1da177e4 LT |
152 | |
153 | { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, | |
154 | { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, | |
e3ad1c23 PP |
155 | |
156 | /* Provide 16 user definable device types */ | |
0ec734c2 WO |
157 | { ~0, 0, 0, 0, 0, 0, 0 }, |
158 | { ~0, 0, 0, 0, 0, 0, 0 }, | |
159 | { ~0, 0, 0, 0, 0, 0, 0 }, | |
160 | { ~0, 0, 0, 0, 0, 0, 0 }, | |
161 | { ~0, 0, 0, 0, 0, 0, 0 }, | |
162 | { ~0, 0, 0, 0, 0, 0, 0 }, | |
163 | { ~0, 0, 0, 0, 0, 0, 0 }, | |
164 | { ~0, 0, 0, 0, 0, 0, 0 }, | |
165 | { ~0, 0, 0, 0, 0, 0, 0 }, | |
166 | { ~0, 0, 0, 0, 0, 0, 0 }, | |
167 | { ~0, 0, 0, 0, 0, 0, 0 }, | |
168 | { ~0, 0, 0, 0, 0, 0, 0 }, | |
169 | { ~0, 0, 0, 0, 0, 0, 0 }, | |
170 | { ~0, 0, 0, 0, 0, 0, 0 }, | |
171 | { ~0, 0, 0, 0, 0, 0, 0 }, | |
172 | { ~0, 0, 0, 0, 0, 0, 0 }, | |
1da177e4 LT |
173 | }; |
174 | ||
2b22c034 | 175 | #define DBDEV_TAB_SIZE ARRAY_SIZE(dbdev_tab) |
1da177e4 LT |
176 | |
177 | static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS]; | |
178 | ||
c1dcb14e | 179 | static dbdev_tab_t *find_dbdev_id(u32 id) |
1da177e4 LT |
180 | { |
181 | int i; | |
182 | dbdev_tab_t *p; | |
183 | for (i = 0; i < DBDEV_TAB_SIZE; ++i) { | |
184 | p = &dbdev_tab[i]; | |
185 | if (p->dev_id == id) | |
186 | return p; | |
187 | } | |
188 | return NULL; | |
189 | } | |
190 | ||
c1dcb14e | 191 | void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp) |
26a940e2 | 192 | { |
c1dcb14e | 193 | return phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); |
26a940e2 PP |
194 | } |
195 | EXPORT_SYMBOL(au1xxx_ddma_get_nextptr_virt); | |
196 | ||
c1dcb14e | 197 | u32 au1xxx_ddma_add_device(dbdev_tab_t *dev) |
e3ad1c23 PP |
198 | { |
199 | u32 ret = 0; | |
c1dcb14e SS |
200 | dbdev_tab_t *p; |
201 | static u16 new_id = 0x1000; | |
e3ad1c23 | 202 | |
0ec734c2 | 203 | p = find_dbdev_id(~0); |
c1dcb14e | 204 | if (NULL != p) { |
e3ad1c23 | 205 | memcpy(p, dev, sizeof(dbdev_tab_t)); |
21a151d8 | 206 | p->dev_id = DSCR_DEV2CUSTOM_ID(new_id, dev->dev_id); |
e3ad1c23 PP |
207 | ret = p->dev_id; |
208 | new_id++; | |
209 | #if 0 | |
c1dcb14e SS |
210 | printk(KERN_DEBUG "add_device: id:%x flags:%x padd:%x\n", |
211 | p->dev_id, p->dev_flags, p->dev_physaddr); | |
e3ad1c23 PP |
212 | #endif |
213 | } | |
214 | ||
215 | return ret; | |
216 | } | |
217 | EXPORT_SYMBOL(au1xxx_ddma_add_device); | |
218 | ||
ccdb0034 ML |
219 | void au1xxx_ddma_del_device(u32 devid) |
220 | { | |
221 | dbdev_tab_t *p = find_dbdev_id(devid); | |
222 | ||
223 | if (p != NULL) { | |
224 | memset(p, 0, sizeof(dbdev_tab_t)); | |
225 | p->dev_id = ~0; | |
226 | } | |
227 | } | |
228 | EXPORT_SYMBOL(au1xxx_ddma_del_device); | |
229 | ||
c1dcb14e SS |
230 | /* Allocate a channel and return a non-zero descriptor if successful. */ |
231 | u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, | |
53e62d3a | 232 | void (*callback)(int, void *), void *callparam) |
1da177e4 LT |
233 | { |
234 | unsigned long flags; | |
235 | u32 used, chan, rv; | |
236 | u32 dcp; | |
237 | int i; | |
238 | dbdev_tab_t *stp, *dtp; | |
239 | chan_tab_t *ctp; | |
e3ad1c23 | 240 | au1x_dma_chan_t *cp; |
1da177e4 | 241 | |
c1dcb14e SS |
242 | /* |
243 | * We do the intialization on the first channel allocation. | |
1da177e4 LT |
244 | * We have to wait because of the interrupt handler initialization |
245 | * which can't be done successfully during board set up. | |
246 | */ | |
247 | if (!dbdma_initialized) | |
248 | au1xxx_dbdma_init(); | |
249 | dbdma_initialized = 1; | |
250 | ||
c1dcb14e SS |
251 | stp = find_dbdev_id(srcid); |
252 | if (stp == NULL) | |
53e62d3a | 253 | return 0; |
c1dcb14e SS |
254 | dtp = find_dbdev_id(destid); |
255 | if (dtp == NULL) | |
53e62d3a | 256 | return 0; |
1da177e4 LT |
257 | |
258 | used = 0; | |
259 | rv = 0; | |
260 | ||
c1dcb14e | 261 | /* Check to see if we can get both channels. */ |
1da177e4 LT |
262 | spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags); |
263 | if (!(stp->dev_flags & DEV_FLAGS_INUSE) || | |
264 | (stp->dev_flags & DEV_FLAGS_ANYUSE)) { | |
a3dddd56 | 265 | /* Got source */ |
1da177e4 LT |
266 | stp->dev_flags |= DEV_FLAGS_INUSE; |
267 | if (!(dtp->dev_flags & DEV_FLAGS_INUSE) || | |
268 | (dtp->dev_flags & DEV_FLAGS_ANYUSE)) { | |
269 | /* Got destination */ | |
270 | dtp->dev_flags |= DEV_FLAGS_INUSE; | |
c1dcb14e SS |
271 | } else { |
272 | /* Can't get dest. Release src. */ | |
1da177e4 LT |
273 | stp->dev_flags &= ~DEV_FLAGS_INUSE; |
274 | used++; | |
275 | } | |
c1dcb14e | 276 | } else |
1da177e4 | 277 | used++; |
1da177e4 LT |
278 | spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags); |
279 | ||
280 | if (!used) { | |
c1dcb14e | 281 | /* Let's see if we can allocate a channel for it. */ |
1da177e4 LT |
282 | ctp = NULL; |
283 | chan = 0; | |
284 | spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags); | |
c1dcb14e | 285 | for (i = 0; i < NUM_DBDMA_CHANS; i++) |
1da177e4 | 286 | if (chan_tab_ptr[i] == NULL) { |
c1dcb14e SS |
287 | /* |
288 | * If kmalloc fails, it is caught below same | |
1da177e4 LT |
289 | * as a channel not available. |
290 | */ | |
c0613894 | 291 | ctp = kmalloc(sizeof(chan_tab_t), GFP_ATOMIC); |
1da177e4 | 292 | chan_tab_ptr[i] = ctp; |
1da177e4 LT |
293 | break; |
294 | } | |
1da177e4 LT |
295 | spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags); |
296 | ||
297 | if (ctp != NULL) { | |
298 | memset(ctp, 0, sizeof(chan_tab_t)); | |
e3ad1c23 | 299 | ctp->chan_index = chan = i; |
1da177e4 LT |
300 | dcp = DDMA_CHANNEL_BASE; |
301 | dcp += (0x0100 * chan); | |
302 | ctp->chan_ptr = (au1x_dma_chan_t *)dcp; | |
e3ad1c23 | 303 | cp = (au1x_dma_chan_t *)dcp; |
1da177e4 LT |
304 | ctp->chan_src = stp; |
305 | ctp->chan_dest = dtp; | |
306 | ctp->chan_callback = callback; | |
307 | ctp->chan_callparam = callparam; | |
308 | ||
c1dcb14e | 309 | /* Initialize channel configuration. */ |
1da177e4 LT |
310 | i = 0; |
311 | if (stp->dev_intlevel) | |
312 | i |= DDMA_CFG_SED; | |
313 | if (stp->dev_intpolarity) | |
314 | i |= DDMA_CFG_SP; | |
315 | if (dtp->dev_intlevel) | |
316 | i |= DDMA_CFG_DED; | |
317 | if (dtp->dev_intpolarity) | |
318 | i |= DDMA_CFG_DP; | |
e3ad1c23 PP |
319 | if ((stp->dev_flags & DEV_FLAGS_SYNC) || |
320 | (dtp->dev_flags & DEV_FLAGS_SYNC)) | |
321 | i |= DDMA_CFG_SYNC; | |
1da177e4 LT |
322 | cp->ddma_cfg = i; |
323 | au_sync(); | |
324 | ||
325 | /* Return a non-zero value that can be used to | |
326 | * find the channel information in subsequent | |
327 | * operations. | |
328 | */ | |
329 | rv = (u32)(&chan_tab_ptr[chan]); | |
c1dcb14e | 330 | } else { |
e3ad1c23 | 331 | /* Release devices */ |
1da177e4 LT |
332 | stp->dev_flags &= ~DEV_FLAGS_INUSE; |
333 | dtp->dev_flags &= ~DEV_FLAGS_INUSE; | |
334 | } | |
335 | } | |
336 | return rv; | |
337 | } | |
e3ad1c23 | 338 | EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc); |
1da177e4 | 339 | |
c1dcb14e SS |
340 | /* |
341 | * Set the device width if source or destination is a FIFO. | |
1da177e4 LT |
342 | * Should be 8, 16, or 32 bits. |
343 | */ | |
c1dcb14e | 344 | u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits) |
1da177e4 LT |
345 | { |
346 | u32 rv; | |
347 | chan_tab_t *ctp; | |
348 | dbdev_tab_t *stp, *dtp; | |
349 | ||
350 | ctp = *((chan_tab_t **)chanid); | |
351 | stp = ctp->chan_src; | |
352 | dtp = ctp->chan_dest; | |
353 | rv = 0; | |
354 | ||
355 | if (stp->dev_flags & DEV_FLAGS_IN) { /* Source in fifo */ | |
356 | rv = stp->dev_devwidth; | |
357 | stp->dev_devwidth = bits; | |
358 | } | |
359 | if (dtp->dev_flags & DEV_FLAGS_OUT) { /* Destination out fifo */ | |
360 | rv = dtp->dev_devwidth; | |
361 | dtp->dev_devwidth = bits; | |
362 | } | |
363 | ||
364 | return rv; | |
365 | } | |
e3ad1c23 | 366 | EXPORT_SYMBOL(au1xxx_dbdma_set_devwidth); |
1da177e4 | 367 | |
c1dcb14e SS |
368 | /* Allocate a descriptor ring, initializing as much as possible. */ |
369 | u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries) | |
1da177e4 LT |
370 | { |
371 | int i; | |
372 | u32 desc_base, srcid, destid; | |
373 | u32 cmd0, cmd1, src1, dest1; | |
374 | u32 src0, dest0; | |
375 | chan_tab_t *ctp; | |
376 | dbdev_tab_t *stp, *dtp; | |
377 | au1x_ddma_desc_t *dp; | |
378 | ||
c1dcb14e SS |
379 | /* |
380 | * I guess we could check this to be within the | |
1da177e4 LT |
381 | * range of the table...... |
382 | */ | |
383 | ctp = *((chan_tab_t **)chanid); | |
384 | stp = ctp->chan_src; | |
385 | dtp = ctp->chan_dest; | |
386 | ||
c1dcb14e SS |
387 | /* |
388 | * The descriptors must be 32-byte aligned. There is a | |
1da177e4 LT |
389 | * possibility the allocation will give us such an address, |
390 | * and if we try that first we are likely to not waste larger | |
391 | * slabs of memory. | |
392 | */ | |
e3ad1c23 | 393 | desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t), |
c1dcb14e | 394 | GFP_KERNEL|GFP_DMA); |
1da177e4 LT |
395 | if (desc_base == 0) |
396 | return 0; | |
397 | ||
398 | if (desc_base & 0x1f) { | |
c1dcb14e SS |
399 | /* |
400 | * Lost....do it again, allocate extra, and round | |
1da177e4 LT |
401 | * the address base. |
402 | */ | |
403 | kfree((const void *)desc_base); | |
404 | i = entries * sizeof(au1x_ddma_desc_t); | |
405 | i += (sizeof(au1x_ddma_desc_t) - 1); | |
c1dcb14e SS |
406 | desc_base = (u32)kmalloc(i, GFP_KERNEL|GFP_DMA); |
407 | if (desc_base == 0) | |
1da177e4 LT |
408 | return 0; |
409 | ||
410 | desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t)); | |
411 | } | |
412 | dp = (au1x_ddma_desc_t *)desc_base; | |
413 | ||
c1dcb14e | 414 | /* Keep track of the base descriptor. */ |
1da177e4 LT |
415 | ctp->chan_desc_base = dp; |
416 | ||
c1dcb14e | 417 | /* Initialize the rings with as much information as we know. */ |
1da177e4 LT |
418 | srcid = stp->dev_id; |
419 | destid = dtp->dev_id; | |
420 | ||
421 | cmd0 = cmd1 = src1 = dest1 = 0; | |
422 | src0 = dest0 = 0; | |
423 | ||
424 | cmd0 |= DSCR_CMD0_SID(srcid); | |
425 | cmd0 |= DSCR_CMD0_DID(destid); | |
426 | cmd0 |= DSCR_CMD0_IE | DSCR_CMD0_CV; | |
13bb199f PP |
427 | cmd0 |= DSCR_CMD0_ST(DSCR_CMD0_ST_NOCHANGE); |
428 | ||
c1dcb14e SS |
429 | /* Is it mem to mem transfer? */ |
430 | if (((DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_THROTTLE) || | |
431 | (DSCR_CUSTOM2DEV_ID(srcid) == DSCR_CMD0_ALWAYS)) && | |
432 | ((DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_THROTTLE) || | |
433 | (DSCR_CUSTOM2DEV_ID(destid) == DSCR_CMD0_ALWAYS))) | |
434 | cmd0 |= DSCR_CMD0_MEM; | |
1da177e4 LT |
435 | |
436 | switch (stp->dev_devwidth) { | |
437 | case 8: | |
438 | cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_BYTE); | |
439 | break; | |
440 | case 16: | |
441 | cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_HALFWORD); | |
442 | break; | |
443 | case 32: | |
444 | default: | |
445 | cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_WORD); | |
446 | break; | |
447 | } | |
448 | ||
449 | switch (dtp->dev_devwidth) { | |
450 | case 8: | |
451 | cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_BYTE); | |
452 | break; | |
453 | case 16: | |
454 | cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_HALFWORD); | |
455 | break; | |
456 | case 32: | |
457 | default: | |
458 | cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_WORD); | |
459 | break; | |
460 | } | |
461 | ||
c1dcb14e SS |
462 | /* |
463 | * If the device is marked as an in/out FIFO, ensure it is | |
1da177e4 LT |
464 | * set non-coherent. |
465 | */ | |
466 | if (stp->dev_flags & DEV_FLAGS_IN) | |
c1dcb14e | 467 | cmd0 |= DSCR_CMD0_SN; /* Source in FIFO */ |
1da177e4 | 468 | if (dtp->dev_flags & DEV_FLAGS_OUT) |
c1dcb14e | 469 | cmd0 |= DSCR_CMD0_DN; /* Destination out FIFO */ |
1da177e4 | 470 | |
c1dcb14e SS |
471 | /* |
472 | * Set up source1. For now, assume no stride and increment. | |
1da177e4 LT |
473 | * A channel attribute update can change this later. |
474 | */ | |
475 | switch (stp->dev_tsize) { | |
476 | case 1: | |
477 | src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE1); | |
478 | break; | |
479 | case 2: | |
480 | src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE2); | |
481 | break; | |
482 | case 4: | |
483 | src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE4); | |
484 | break; | |
485 | case 8: | |
486 | default: | |
487 | src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE8); | |
488 | break; | |
489 | } | |
490 | ||
c1dcb14e | 491 | /* If source input is FIFO, set static address. */ |
1da177e4 | 492 | if (stp->dev_flags & DEV_FLAGS_IN) { |
c1dcb14e | 493 | if (stp->dev_flags & DEV_FLAGS_BURSTABLE) |
e3ad1c23 PP |
494 | src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST); |
495 | else | |
c1dcb14e | 496 | src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC); |
1da177e4 | 497 | } |
c1dcb14e | 498 | |
e3ad1c23 PP |
499 | if (stp->dev_physaddr) |
500 | src0 = stp->dev_physaddr; | |
1da177e4 | 501 | |
c1dcb14e SS |
502 | /* |
503 | * Set up dest1. For now, assume no stride and increment. | |
1da177e4 LT |
504 | * A channel attribute update can change this later. |
505 | */ | |
506 | switch (dtp->dev_tsize) { | |
507 | case 1: | |
508 | dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE1); | |
509 | break; | |
510 | case 2: | |
511 | dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE2); | |
512 | break; | |
513 | case 4: | |
514 | dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE4); | |
515 | break; | |
516 | case 8: | |
517 | default: | |
518 | dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE8); | |
519 | break; | |
520 | } | |
521 | ||
c1dcb14e | 522 | /* If destination output is FIFO, set static address. */ |
1da177e4 | 523 | if (dtp->dev_flags & DEV_FLAGS_OUT) { |
c1dcb14e SS |
524 | if (dtp->dev_flags & DEV_FLAGS_BURSTABLE) |
525 | dest1 |= DSCR_DEST1_DAM(DSCR_xAM_BURST); | |
526 | else | |
527 | dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC); | |
1da177e4 | 528 | } |
c1dcb14e | 529 | |
e3ad1c23 PP |
530 | if (dtp->dev_physaddr) |
531 | dest0 = dtp->dev_physaddr; | |
1da177e4 | 532 | |
e3ad1c23 | 533 | #if 0 |
c1dcb14e SS |
534 | printk(KERN_DEBUG "did:%x sid:%x cmd0:%x cmd1:%x source0:%x " |
535 | "source1:%x dest0:%x dest1:%x\n", | |
536 | dtp->dev_id, stp->dev_id, cmd0, cmd1, src0, | |
537 | src1, dest0, dest1); | |
e3ad1c23 | 538 | #endif |
c1dcb14e | 539 | for (i = 0; i < entries; i++) { |
1da177e4 LT |
540 | dp->dscr_cmd0 = cmd0; |
541 | dp->dscr_cmd1 = cmd1; | |
542 | dp->dscr_source0 = src0; | |
543 | dp->dscr_source1 = src1; | |
544 | dp->dscr_dest0 = dest0; | |
545 | dp->dscr_dest1 = dest1; | |
546 | dp->dscr_stat = 0; | |
13bb199f PP |
547 | dp->sw_context = 0; |
548 | dp->sw_status = 0; | |
1da177e4 LT |
549 | dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1)); |
550 | dp++; | |
551 | } | |
552 | ||
c1dcb14e | 553 | /* Make last descrptor point to the first. */ |
1da177e4 LT |
554 | dp--; |
555 | dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(ctp->chan_desc_base)); | |
556 | ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base; | |
557 | ||
c1dcb14e | 558 | return (u32)ctp->chan_desc_base; |
1da177e4 | 559 | } |
e3ad1c23 | 560 | EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc); |
1da177e4 | 561 | |
c1dcb14e SS |
562 | /* |
563 | * Put a source buffer into the DMA ring. | |
1da177e4 LT |
564 | * This updates the source pointer and byte count. Normally used |
565 | * for memory to fifo transfers. | |
566 | */ | |
c1dcb14e | 567 | u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags) |
1da177e4 LT |
568 | { |
569 | chan_tab_t *ctp; | |
570 | au1x_ddma_desc_t *dp; | |
571 | ||
c1dcb14e SS |
572 | /* |
573 | * I guess we could check this to be within the | |
1da177e4 LT |
574 | * range of the table...... |
575 | */ | |
c1dcb14e | 576 | ctp = *(chan_tab_t **)chanid; |
1da177e4 | 577 | |
c1dcb14e SS |
578 | /* |
579 | * We should have multiple callers for a particular channel, | |
1da177e4 LT |
580 | * an interrupt doesn't affect this pointer nor the descriptor, |
581 | * so no locking should be needed. | |
582 | */ | |
583 | dp = ctp->put_ptr; | |
584 | ||
c1dcb14e SS |
585 | /* |
586 | * If the descriptor is valid, we are way ahead of the DMA | |
1da177e4 LT |
587 | * engine, so just return an error condition. |
588 | */ | |
c1dcb14e | 589 | if (dp->dscr_cmd0 & DSCR_CMD0_V) |
1da177e4 | 590 | return 0; |
1da177e4 | 591 | |
c1dcb14e | 592 | /* Load up buffer address and byte count. */ |
1da177e4 LT |
593 | dp->dscr_source0 = virt_to_phys(buf); |
594 | dp->dscr_cmd1 = nbytes; | |
c1dcb14e | 595 | /* Check flags */ |
e3ad1c23 PP |
596 | if (flags & DDMA_FLAGS_IE) |
597 | dp->dscr_cmd0 |= DSCR_CMD0_IE; | |
598 | if (flags & DDMA_FLAGS_NOIE) | |
599 | dp->dscr_cmd0 &= ~DSCR_CMD0_IE; | |
1da177e4 | 600 | |
e3ad1c23 PP |
601 | /* |
602 | * There is an errata on the Au1200/Au1550 parts that could result | |
c1dcb14e SS |
603 | * in "stale" data being DMA'ed. It has to do with the snoop logic on |
604 | * the cache eviction buffer. DMA_NONCOHERENT is on by default for | |
605 | * these parts. If it is fixed in the future, these dma_cache_inv will | |
e3ad1c23 | 606 | * just be nothing more than empty macros. See io.h. |
c1dcb14e | 607 | */ |
2d32ffa4 | 608 | dma_cache_wback_inv((unsigned long)buf, nbytes); |
c1dcb14e | 609 | dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ |
e3ad1c23 | 610 | au_sync(); |
2d32ffa4 | 611 | dma_cache_wback_inv((unsigned long)dp, sizeof(dp)); |
c1dcb14e | 612 | ctp->chan_ptr->ddma_dbell = 0; |
e3ad1c23 | 613 | |
c1dcb14e | 614 | /* Get next descriptor pointer. */ |
13bb199f PP |
615 | ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); |
616 | ||
c1dcb14e | 617 | /* Return something non-zero. */ |
1da177e4 LT |
618 | return nbytes; |
619 | } | |
e3ad1c23 | 620 | EXPORT_SYMBOL(_au1xxx_dbdma_put_source); |
1da177e4 LT |
621 | |
622 | /* Put a destination buffer into the DMA ring. | |
623 | * This updates the destination pointer and byte count. Normally used | |
624 | * to place an empty buffer into the ring for fifo to memory transfers. | |
625 | */ | |
626 | u32 | |
e3ad1c23 | 627 | _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags) |
1da177e4 LT |
628 | { |
629 | chan_tab_t *ctp; | |
630 | au1x_ddma_desc_t *dp; | |
631 | ||
632 | /* I guess we could check this to be within the | |
633 | * range of the table...... | |
634 | */ | |
635 | ctp = *((chan_tab_t **)chanid); | |
636 | ||
637 | /* We should have multiple callers for a particular channel, | |
638 | * an interrupt doesn't affect this pointer nor the descriptor, | |
639 | * so no locking should be needed. | |
640 | */ | |
641 | dp = ctp->put_ptr; | |
642 | ||
643 | /* If the descriptor is valid, we are way ahead of the DMA | |
644 | * engine, so just return an error condition. | |
645 | */ | |
646 | if (dp->dscr_cmd0 & DSCR_CMD0_V) | |
647 | return 0; | |
648 | ||
e3ad1c23 PP |
649 | /* Load up buffer address and byte count */ |
650 | ||
651 | /* Check flags */ | |
652 | if (flags & DDMA_FLAGS_IE) | |
653 | dp->dscr_cmd0 |= DSCR_CMD0_IE; | |
654 | if (flags & DDMA_FLAGS_NOIE) | |
655 | dp->dscr_cmd0 &= ~DSCR_CMD0_IE; | |
656 | ||
1da177e4 LT |
657 | dp->dscr_dest0 = virt_to_phys(buf); |
658 | dp->dscr_cmd1 = nbytes; | |
e3ad1c23 | 659 | #if 0 |
c1dcb14e SS |
660 | printk(KERN_DEBUG "cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n", |
661 | dp->dscr_cmd0, dp->dscr_cmd1, dp->dscr_source0, | |
662 | dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1); | |
e3ad1c23 PP |
663 | #endif |
664 | /* | |
665 | * There is an errata on the Au1200/Au1550 parts that could result in | |
c1dcb14e SS |
666 | * "stale" data being DMA'ed. It has to do with the snoop logic on the |
667 | * cache eviction buffer. DMA_NONCOHERENT is on by default for these | |
668 | * parts. If it is fixed in the future, these dma_cache_inv will just | |
e3ad1c23 | 669 | * be nothing more than empty macros. See io.h. |
c1dcb14e | 670 | */ |
21a151d8 | 671 | dma_cache_inv((unsigned long)buf, nbytes); |
1da177e4 | 672 | dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ |
e3ad1c23 | 673 | au_sync(); |
2d32ffa4 | 674 | dma_cache_wback_inv((unsigned long)dp, sizeof(dp)); |
c1dcb14e | 675 | ctp->chan_ptr->ddma_dbell = 0; |
1da177e4 | 676 | |
c1dcb14e | 677 | /* Get next descriptor pointer. */ |
1da177e4 LT |
678 | ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); |
679 | ||
c1dcb14e | 680 | /* Return something non-zero. */ |
1da177e4 LT |
681 | return nbytes; |
682 | } | |
e3ad1c23 | 683 | EXPORT_SYMBOL(_au1xxx_dbdma_put_dest); |
1da177e4 | 684 | |
c1dcb14e SS |
685 | /* |
686 | * Get a destination buffer into the DMA ring. | |
1da177e4 LT |
687 | * Normally used to get a full buffer from the ring during fifo |
688 | * to memory transfers. This does not set the valid bit, you will | |
689 | * have to put another destination buffer to keep the DMA going. | |
690 | */ | |
c1dcb14e | 691 | u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes) |
1da177e4 LT |
692 | { |
693 | chan_tab_t *ctp; | |
694 | au1x_ddma_desc_t *dp; | |
695 | u32 rv; | |
696 | ||
c1dcb14e SS |
697 | /* |
698 | * I guess we could check this to be within the | |
1da177e4 LT |
699 | * range of the table...... |
700 | */ | |
701 | ctp = *((chan_tab_t **)chanid); | |
702 | ||
c1dcb14e SS |
703 | /* |
704 | * We should have multiple callers for a particular channel, | |
1da177e4 LT |
705 | * an interrupt doesn't affect this pointer nor the descriptor, |
706 | * so no locking should be needed. | |
707 | */ | |
708 | dp = ctp->get_ptr; | |
709 | ||
c1dcb14e SS |
710 | /* |
711 | * If the descriptor is valid, we are way ahead of the DMA | |
1da177e4 LT |
712 | * engine, so just return an error condition. |
713 | */ | |
714 | if (dp->dscr_cmd0 & DSCR_CMD0_V) | |
715 | return 0; | |
716 | ||
c1dcb14e | 717 | /* Return buffer address and byte count. */ |
1da177e4 LT |
718 | *buf = (void *)(phys_to_virt(dp->dscr_dest0)); |
719 | *nbytes = dp->dscr_cmd1; | |
720 | rv = dp->dscr_stat; | |
721 | ||
c1dcb14e | 722 | /* Get next descriptor pointer. */ |
1da177e4 LT |
723 | ctp->get_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); |
724 | ||
c1dcb14e | 725 | /* Return something non-zero. */ |
1da177e4 LT |
726 | return rv; |
727 | } | |
3e2c6ef3 DP |
728 | EXPORT_SYMBOL_GPL(au1xxx_dbdma_get_dest); |
729 | ||
c1dcb14e | 730 | void au1xxx_dbdma_stop(u32 chanid) |
1da177e4 LT |
731 | { |
732 | chan_tab_t *ctp; | |
e3ad1c23 | 733 | au1x_dma_chan_t *cp; |
1da177e4 LT |
734 | int halt_timeout = 0; |
735 | ||
736 | ctp = *((chan_tab_t **)chanid); | |
737 | ||
738 | cp = ctp->chan_ptr; | |
739 | cp->ddma_cfg &= ~DDMA_CFG_EN; /* Disable channel */ | |
740 | au_sync(); | |
741 | while (!(cp->ddma_stat & DDMA_STAT_H)) { | |
742 | udelay(1); | |
743 | halt_timeout++; | |
744 | if (halt_timeout > 100) { | |
c1dcb14e | 745 | printk(KERN_WARNING "warning: DMA channel won't halt\n"); |
1da177e4 LT |
746 | break; |
747 | } | |
748 | } | |
749 | /* clear current desc valid and doorbell */ | |
750 | cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V); | |
751 | au_sync(); | |
752 | } | |
e3ad1c23 | 753 | EXPORT_SYMBOL(au1xxx_dbdma_stop); |
1da177e4 | 754 | |
c1dcb14e SS |
755 | /* |
756 | * Start using the current descriptor pointer. If the DBDMA encounters | |
757 | * a non-valid descriptor, it will stop. In this case, we can just | |
1da177e4 LT |
758 | * continue by adding a buffer to the list and starting again. |
759 | */ | |
c1dcb14e | 760 | void au1xxx_dbdma_start(u32 chanid) |
1da177e4 LT |
761 | { |
762 | chan_tab_t *ctp; | |
e3ad1c23 | 763 | au1x_dma_chan_t *cp; |
1da177e4 LT |
764 | |
765 | ctp = *((chan_tab_t **)chanid); | |
1da177e4 LT |
766 | cp = ctp->chan_ptr; |
767 | cp->ddma_desptr = virt_to_phys(ctp->cur_ptr); | |
768 | cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */ | |
769 | au_sync(); | |
e3ad1c23 | 770 | cp->ddma_dbell = 0; |
1da177e4 LT |
771 | au_sync(); |
772 | } | |
e3ad1c23 | 773 | EXPORT_SYMBOL(au1xxx_dbdma_start); |
1da177e4 | 774 | |
c1dcb14e | 775 | void au1xxx_dbdma_reset(u32 chanid) |
1da177e4 LT |
776 | { |
777 | chan_tab_t *ctp; | |
778 | au1x_ddma_desc_t *dp; | |
779 | ||
780 | au1xxx_dbdma_stop(chanid); | |
781 | ||
782 | ctp = *((chan_tab_t **)chanid); | |
783 | ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base; | |
784 | ||
c1dcb14e | 785 | /* Run through the descriptors and reset the valid indicator. */ |
1da177e4 LT |
786 | dp = ctp->chan_desc_base; |
787 | ||
788 | do { | |
789 | dp->dscr_cmd0 &= ~DSCR_CMD0_V; | |
c1dcb14e SS |
790 | /* |
791 | * Reset our software status -- this is used to determine | |
792 | * if a descriptor is in use by upper level software. Since | |
e3ad1c23 PP |
793 | * posting can reset 'V' bit. |
794 | */ | |
795 | dp->sw_status = 0; | |
1da177e4 LT |
796 | dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); |
797 | } while (dp != ctp->chan_desc_base); | |
798 | } | |
e3ad1c23 | 799 | EXPORT_SYMBOL(au1xxx_dbdma_reset); |
1da177e4 | 800 | |
c1dcb14e | 801 | u32 au1xxx_get_dma_residue(u32 chanid) |
1da177e4 LT |
802 | { |
803 | chan_tab_t *ctp; | |
e3ad1c23 | 804 | au1x_dma_chan_t *cp; |
1da177e4 LT |
805 | u32 rv; |
806 | ||
807 | ctp = *((chan_tab_t **)chanid); | |
808 | cp = ctp->chan_ptr; | |
809 | ||
c1dcb14e | 810 | /* This is only valid if the channel is stopped. */ |
1da177e4 LT |
811 | rv = cp->ddma_bytecnt; |
812 | au_sync(); | |
813 | ||
814 | return rv; | |
815 | } | |
3e2c6ef3 DP |
816 | EXPORT_SYMBOL_GPL(au1xxx_get_dma_residue); |
817 | ||
c1dcb14e | 818 | void au1xxx_dbdma_chan_free(u32 chanid) |
1da177e4 LT |
819 | { |
820 | chan_tab_t *ctp; | |
821 | dbdev_tab_t *stp, *dtp; | |
822 | ||
823 | ctp = *((chan_tab_t **)chanid); | |
824 | stp = ctp->chan_src; | |
825 | dtp = ctp->chan_dest; | |
826 | ||
827 | au1xxx_dbdma_stop(chanid); | |
828 | ||
2d32ffa4 | 829 | kfree((void *)ctp->chan_desc_base); |
1da177e4 LT |
830 | |
831 | stp->dev_flags &= ~DEV_FLAGS_INUSE; | |
832 | dtp->dev_flags &= ~DEV_FLAGS_INUSE; | |
833 | chan_tab_ptr[ctp->chan_index] = NULL; | |
834 | ||
835 | kfree(ctp); | |
836 | } | |
e3ad1c23 | 837 | EXPORT_SYMBOL(au1xxx_dbdma_chan_free); |
1da177e4 | 838 | |
c1dcb14e | 839 | static irqreturn_t dbdma_interrupt(int irq, void *dev_id) |
1da177e4 | 840 | { |
2d32ffa4 PP |
841 | u32 intstat; |
842 | u32 chan_index; | |
1da177e4 LT |
843 | chan_tab_t *ctp; |
844 | au1x_ddma_desc_t *dp; | |
e3ad1c23 | 845 | au1x_dma_chan_t *cp; |
1da177e4 LT |
846 | |
847 | intstat = dbdma_gptr->ddma_intstat; | |
848 | au_sync(); | |
4b366732 | 849 | chan_index = __ffs(intstat); |
1da177e4 LT |
850 | |
851 | ctp = chan_tab_ptr[chan_index]; | |
852 | cp = ctp->chan_ptr; | |
853 | dp = ctp->cur_ptr; | |
854 | ||
c1dcb14e | 855 | /* Reset interrupt. */ |
1da177e4 LT |
856 | cp->ddma_irq = 0; |
857 | au_sync(); | |
858 | ||
859 | if (ctp->chan_callback) | |
c1dcb14e | 860 | ctp->chan_callback(irq, ctp->chan_callparam); |
1da177e4 LT |
861 | |
862 | ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); | |
2d32ffa4 | 863 | return IRQ_RETVAL(1); |
1da177e4 LT |
864 | } |
865 | ||
e3ad1c23 | 866 | static void au1xxx_dbdma_init(void) |
1da177e4 | 867 | { |
e3ad1c23 PP |
868 | int irq_nr; |
869 | ||
1da177e4 LT |
870 | dbdma_gptr->ddma_config = 0; |
871 | dbdma_gptr->ddma_throttle = 0; | |
872 | dbdma_gptr->ddma_inten = 0xffff; | |
873 | au_sync(); | |
874 | ||
e3ad1c23 PP |
875 | #if defined(CONFIG_SOC_AU1550) |
876 | irq_nr = AU1550_DDMA_INT; | |
877 | #elif defined(CONFIG_SOC_AU1200) | |
878 | irq_nr = AU1200_DDMA_INT; | |
879 | #else | |
880 | #error Unknown Au1x00 SOC | |
881 | #endif | |
882 | ||
f40298fd | 883 | if (request_irq(irq_nr, dbdma_interrupt, IRQF_DISABLED, |
1da177e4 | 884 | "Au1xxx dbdma", (void *)dbdma_gptr)) |
c1dcb14e | 885 | printk(KERN_ERR "Can't get 1550 dbdma irq"); |
1da177e4 LT |
886 | } |
887 | ||
c1dcb14e | 888 | void au1xxx_dbdma_dump(u32 chanid) |
1da177e4 | 889 | { |
c1dcb14e SS |
890 | chan_tab_t *ctp; |
891 | au1x_ddma_desc_t *dp; | |
892 | dbdev_tab_t *stp, *dtp; | |
893 | au1x_dma_chan_t *cp; | |
894 | u32 i = 0; | |
1da177e4 LT |
895 | |
896 | ctp = *((chan_tab_t **)chanid); | |
897 | stp = ctp->chan_src; | |
898 | dtp = ctp->chan_dest; | |
899 | cp = ctp->chan_ptr; | |
900 | ||
c1dcb14e SS |
901 | printk(KERN_DEBUG "Chan %x, stp %x (dev %d) dtp %x (dev %d) \n", |
902 | (u32)ctp, (u32)stp, stp - dbdev_tab, (u32)dtp, | |
903 | dtp - dbdev_tab); | |
904 | printk(KERN_DEBUG "desc base %x, get %x, put %x, cur %x\n", | |
905 | (u32)(ctp->chan_desc_base), (u32)(ctp->get_ptr), | |
906 | (u32)(ctp->put_ptr), (u32)(ctp->cur_ptr)); | |
907 | ||
908 | printk(KERN_DEBUG "dbdma chan %x\n", (u32)cp); | |
909 | printk(KERN_DEBUG "cfg %08x, desptr %08x, statptr %08x\n", | |
910 | cp->ddma_cfg, cp->ddma_desptr, cp->ddma_statptr); | |
911 | printk(KERN_DEBUG "dbell %08x, irq %08x, stat %08x, bytecnt %08x\n", | |
912 | cp->ddma_dbell, cp->ddma_irq, cp->ddma_stat, | |
913 | cp->ddma_bytecnt); | |
914 | ||
915 | /* Run through the descriptors */ | |
1da177e4 LT |
916 | dp = ctp->chan_desc_base; |
917 | ||
918 | do { | |
c1dcb14e SS |
919 | printk(KERN_DEBUG "Dp[%d]= %08x, cmd0 %08x, cmd1 %08x\n", |
920 | i++, (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1); | |
921 | printk(KERN_DEBUG "src0 %08x, src1 %08x, dest0 %08x, dest1 %08x\n", | |
922 | dp->dscr_source0, dp->dscr_source1, | |
923 | dp->dscr_dest0, dp->dscr_dest1); | |
924 | printk(KERN_DEBUG "stat %08x, nxtptr %08x\n", | |
925 | dp->dscr_stat, dp->dscr_nxtptr); | |
1da177e4 LT |
926 | dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); |
927 | } while (dp != ctp->chan_desc_base); | |
928 | } | |
929 | ||
e3ad1c23 PP |
930 | /* Put a descriptor into the DMA ring. |
931 | * This updates the source/destination pointers and byte count. | |
932 | */ | |
c1dcb14e | 933 | u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr) |
e3ad1c23 PP |
934 | { |
935 | chan_tab_t *ctp; | |
936 | au1x_ddma_desc_t *dp; | |
c1dcb14e | 937 | u32 nbytes = 0; |
e3ad1c23 | 938 | |
c1dcb14e SS |
939 | /* |
940 | * I guess we could check this to be within the | |
941 | * range of the table...... | |
942 | */ | |
e3ad1c23 PP |
943 | ctp = *((chan_tab_t **)chanid); |
944 | ||
c1dcb14e SS |
945 | /* |
946 | * We should have multiple callers for a particular channel, | |
947 | * an interrupt doesn't affect this pointer nor the descriptor, | |
948 | * so no locking should be needed. | |
949 | */ | |
e3ad1c23 PP |
950 | dp = ctp->put_ptr; |
951 | ||
c1dcb14e SS |
952 | /* |
953 | * If the descriptor is valid, we are way ahead of the DMA | |
954 | * engine, so just return an error condition. | |
955 | */ | |
e3ad1c23 PP |
956 | if (dp->dscr_cmd0 & DSCR_CMD0_V) |
957 | return 0; | |
958 | ||
c1dcb14e | 959 | /* Load up buffer addresses and byte count. */ |
e3ad1c23 PP |
960 | dp->dscr_dest0 = dscr->dscr_dest0; |
961 | dp->dscr_source0 = dscr->dscr_source0; | |
962 | dp->dscr_dest1 = dscr->dscr_dest1; | |
963 | dp->dscr_source1 = dscr->dscr_source1; | |
964 | dp->dscr_cmd1 = dscr->dscr_cmd1; | |
965 | nbytes = dscr->dscr_cmd1; | |
966 | /* Allow the caller to specifiy if an interrupt is generated */ | |
967 | dp->dscr_cmd0 &= ~DSCR_CMD0_IE; | |
968 | dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V; | |
969 | ctp->chan_ptr->ddma_dbell = 0; | |
970 | ||
c1dcb14e | 971 | /* Get next descriptor pointer. */ |
e3ad1c23 PP |
972 | ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); |
973 | ||
c1dcb14e | 974 | /* Return something non-zero. */ |
e3ad1c23 PP |
975 | return nbytes; |
976 | } | |
977 | ||
1da177e4 | 978 | #endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */ |