[mirror_ubuntu-bionic-kernel.git] / arch / mips / boot / dts / brcm / bcm7425.dtsi

// SPDX-License-Identifier: GPL-2.0
/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "brcm,bcm7425";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		mips-hpt-frequency = <163125000>;

		cpu@0 {
			compatible = "brcm,bmips5000";
			device_type = "cpu";
			reg = <0>;
		};

		cpu@1 {
			compatible = "brcm,bmips5000";
			device_type = "cpu";
			reg = <1>;
		};
	};

	aliases {
		uart0 = &uart0;
	};

	cpu_intc: interrupt-controller {
		#address-cells = <0>;
		compatible = "mti,cpu-interrupt-controller";

		interrupt-controller;
		#interrupt-cells = <1>;
	};

	clocks {
		uart_clk: uart_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <81000000>;
		};

		upg_clk: upg_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <27000000>;
		};
	};

	rdb {
		#address-cells = <1>;
		#size-cells = <1>;

		compatible = "simple-bus";
		ranges = <0 0x10000000 0x01000000>;

		periph_intc: interrupt-controller@41a400 {
			compatible = "brcm,bcm7038-l1-intc";
			reg = <0x41a400 0x30>, <0x41a600 0x30>;

			interrupt-controller;
			#interrupt-cells = <1>;

			interrupt-parent = <&cpu_intc>;
			interrupts = <2>, <3>;
		};

		sun_l2_intc: interrupt-controller@403000 {
			compatible = "brcm,l2-intc";
			reg = <0x403000 0x30>;
			interrupt-controller;
			#interrupt-cells = <1>;
			interrupt-parent = <&periph_intc>;
			interrupts = <47>;
		};

		gisb-arb@400000 {
			compatible = "brcm,bcm7400-gisb-arb";
			reg = <0x400000 0xdc>;
			native-endian;
			interrupt-parent = <&sun_l2_intc>;
			interrupts = <0>, <2>;
			brcm,gisb-arb-master-mask = <0x177b>;
			brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pcie_0",
						     "bsp_0", "rdc_0",
						     "raaga_0", "avd_1",
						     "jtag_0", "svd_0",
						     "vice_0";
		};

		upg_irq0_intc: interrupt-controller@406780 {
			compatible = "brcm,bcm7120-l2-intc";
			reg = <0x406780 0x8>;

			brcm,int-map-mask = <0x44>, <0x7000000>;
			brcm,int-fwd-mask = <0x70000>;

			interrupt-controller;
			#interrupt-cells = <1>;

			interrupt-parent = <&periph_intc>;
			interrupts = <55>, <53>;
			interrupt-names = "upg_main", "upg_bsc";
		};

		upg_aon_irq0_intc: interrupt-controller@409480 {
			compatible = "brcm,bcm7120-l2-intc";
			reg = <0x409480 0x8>;

			brcm,int-map-mask = <0x40>, <0x18000000>, <0x100000>;
			brcm,int-fwd-mask = <0>;
			brcm,irq-can-wake;

			interrupt-controller;
			#interrupt-cells = <1>;

			interrupt-parent = <&periph_intc>;
			interrupts = <56>, <54>, <59>;
			interrupt-names = "upg_main_aon", "upg_bsc_aon",
					  "upg_spi";
		};

		sun_top_ctrl: syscon@404000 {
			compatible = "brcm,bcm7425-sun-top-ctrl", "syscon";
			reg = <0x404000 0x51c>;
			native-endian;
		};

		reboot {
			compatible = "brcm,brcmstb-reboot";
			syscon = <&sun_top_ctrl 0x304 0x308>;
		};

		uart0: serial@406b00 {
			compatible = "ns16550a";
			reg = <0x406b00 0x20>;
			reg-io-width = <0x4>;
			reg-shift = <0x2>;
			interrupt-parent = <&periph_intc>;
			interrupts = <61>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		uart1: serial@406b40 {
			compatible = "ns16550a";
			reg = <0x406b40 0x20>;
			reg-io-width = <0x4>;
			reg-shift = <0x2>;
			interrupt-parent = <&periph_intc>;
			interrupts = <62>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		uart2: serial@406b80 {
			compatible = "ns16550a";
			reg = <0x406b80 0x20>;
			reg-io-width = <0x4>;
			reg-shift = <0x2>;
			interrupt-parent = <&periph_intc>;
			interrupts = <63>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		bsca: i2c@409180 {
		      clock-frequency = <390000>;
		      compatible = "brcm,brcmstb-i2c";
		      interrupt-parent = <&upg_aon_irq0_intc>;
		      reg = <0x409180 0x58>;
		      interrupts = <27>;
		      interrupt-names = "upg_bsca";
		      status = "disabled";
		};

		bscb: i2c@409400 {
		      clock-frequency = <390000>;
		      compatible = "brcm,brcmstb-i2c";
		      interrupt-parent = <&upg_aon_irq0_intc>;
		      reg = <0x409400 0x58>;
		      interrupts = <28>;
		      interrupt-names = "upg_bscb";
		      status = "disabled";
		};

		bscc: i2c@406200 {
		      clock-frequency = <390000>;
		      compatible = "brcm,brcmstb-i2c";
		      interrupt-parent = <&upg_irq0_intc>;
		      reg = <0x406200 0x58>;
		      interrupts = <24>;
		      interrupt-names = "upg_bscc";
		      status = "disabled";
		};

		bscd: i2c@406280 {
		      clock-frequency = <390000>;
		      compatible = "brcm,brcmstb-i2c";
		      interrupt-parent = <&upg_irq0_intc>;
		      reg = <0x406280 0x58>;
		      interrupts = <25>;
		      interrupt-names = "upg_bscd";
		      status = "disabled";
		};

		bsce: i2c@406300 {
		      clock-frequency = <390000>;
		      compatible = "brcm,brcmstb-i2c";
		      interrupt-parent = <&upg_irq0_intc>;
		      reg = <0x406300 0x58>;
		      interrupts = <26>;
		      interrupt-names = "upg_bsce";
		      status = "disabled";
		};

		pwma: pwm@406580 {
			compatible = "brcm,bcm7038-pwm";
			reg = <0x406580 0x28>;
			#pwm-cells = <2>;
			clocks = <&upg_clk>;
			status = "disabled";
		};

		pwmb: pwm@406800 {
			compatible = "brcm,bcm7038-pwm";
			reg = <0x406800 0x28>;
			#pwm-cells = <2>;
			clocks = <&upg_clk>;
			status = "disabled";
		};

		aon_pm_l2_intc: interrupt-controller@408440 {
			compatible = "brcm,l2-intc";
			reg = <0x408440 0x30>;
			interrupt-controller;
			#interrupt-cells = <1>;
			interrupt-parent = <&periph_intc>;
			interrupts = <49>;
			brcm,irq-can-wake;
		};

		upg_gio: gpio@406700 {
			compatible = "brcm,brcmstb-gpio";
			reg = <0x406700 0x80>;
			#gpio-cells = <2>;
			#interrupt-cells = <2>;
			gpio-controller;
			interrupt-controller;
			interrupt-parent = <&upg_irq0_intc>;
			interrupts = <6>;
			brcm,gpio-bank-widths = <32 32 32 21>;
		};

		upg_gio_aon: gpio@4094c0 {
			compatible = "brcm,brcmstb-gpio";
			reg = <0x4094c0 0x40>;
			#gpio-cells = <2>;
			#interrupt-cells = <2>;
			gpio-controller;
			interrupt-controller;
			interrupt-parent = <&upg_aon_irq0_intc>;
			interrupts = <6>;
			interrupts-extended = <&upg_aon_irq0_intc 6>,
					      <&aon_pm_l2_intc 5>;
			wakeup-source;
			brcm,gpio-bank-widths = <18 4>;
		};

		enet0: ethernet@b80000 {
			phy-mode = "internal";
			phy-handle = <&phy1>;
			mac-address = [ 00 10 18 36 23 1a ];
			compatible = "brcm,genet-v3";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			reg = <0xb80000 0x11c88>;
			interrupts = <17>, <18>;
			interrupt-parent = <&periph_intc>;
			status = "disabled";

			mdio@e14 {
				compatible = "brcm,genet-mdio-v3";
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0xe14 0x8>;

				phy1: ethernet-phy@1 {
					max-speed = <100>;
					reg = <0x1>;
					compatible = "brcm,40nm-ephy",
						"ethernet-phy-ieee802.3-c22";
				};
			};
		};

		ehci0: usb@480300 {
			compatible = "brcm,bcm7425-ehci", "generic-ehci";
			reg = <0x480300 0x100>;
			native-endian;
			interrupt-parent = <&periph_intc>;
			interrupts = <65>;
			status = "disabled";
		};

		ohci0: usb@480400 {
			compatible = "brcm,bcm7425-ohci", "generic-ohci";
			reg = <0x480400 0x100>;
			native-endian;
			no-big-frame-no;
			interrupt-parent = <&periph_intc>;
			interrupts = <67>;
			status = "disabled";
		};

		ehci1: usb@480500 {
			compatible = "brcm,bcm7425-ehci", "generic-ehci";
			reg = <0x480500 0x100>;
			native-endian;
			interrupt-parent = <&periph_intc>;
			interrupts = <66>;
			status = "disabled";
		};

		ohci1: usb@480600 {
			compatible = "brcm,bcm7425-ohci", "generic-ohci";
			reg = <0x480600 0x100>;
			native-endian;
			no-big-frame-no;
			interrupt-parent = <&periph_intc>;
			interrupts = <68>;
			status = "disabled";
		};

		ehci2: usb@490300 {
			compatible = "brcm,bcm7425-ehci", "generic-ehci";
			reg = <0x490300 0x100>;
			native-endian;
			interrupt-parent = <&periph_intc>;
			interrupts = <70>;
			status = "disabled";
		};

		ohci2: usb@490400 {
			compatible = "brcm,bcm7425-ohci", "generic-ohci";
			reg = <0x490400 0x100>;
			native-endian;
			no-big-frame-no;
			interrupt-parent = <&periph_intc>;
			interrupts = <72>;
			status = "disabled";
		};

		ehci3: usb@490500 {
			compatible = "brcm,bcm7425-ehci", "generic-ehci";
			reg = <0x490500 0x100>;
			native-endian;
			interrupt-parent = <&periph_intc>;
			interrupts = <71>;
			status = "disabled";
		};

		ohci3: usb@490600 {
			compatible = "brcm,bcm7425-ohci", "generic-ohci";
			reg = <0x490600 0x100>;
			native-endian;
			no-big-frame-no;
			interrupt-parent = <&periph_intc>;
			interrupts = <73>;
			status = "disabled";
		};

		hif_l2_intc: interrupt-controller@41a000 {
			compatible = "brcm,l2-intc";
			reg = <0x41a000 0x30>;
			interrupt-controller;
			#interrupt-cells = <1>;
			interrupt-parent = <&periph_intc>;
			interrupts = <24>;
		};

		nand: nand@41b800 {
			compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
			#address-cells = <1>;
			#size-cells = <0>;
			reg-names = "nand";
			reg = <0x41b800 0x400>;
			interrupt-parent = <&hif_l2_intc>;
			interrupts = <24>;
			status = "disabled";
		};

		sata: sata@181000 {
			compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
			reg-names = "ahci", "top-ctrl";
			reg = <0x181000 0xa9c>, <0x180020 0x1c>;
			interrupt-parent = <&periph_intc>;
			interrupts = <41>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			sata0: sata-port@0 {
				reg = <0>;
				phys = <&sata_phy0>;
			};

			sata1: sata-port@1 {
				reg = <1>;
				phys = <&sata_phy1>;
			};
		};

		sata_phy: sata-phy@180100 {
			compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
			reg = <0x180100 0x0eff>;
			reg-names = "phy";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			sata_phy0: sata-phy@0 {
				reg = <0>;
				#phy-cells = <0>;
			};

			sata_phy1: sata-phy@1 {
				reg = <1>;
				#phy-cells = <0>;
			};
		};

		sdhci0: sdhci@419000 {
			compatible = "brcm,bcm7425-sdhci";
			reg = <0x419000 0x100>;
			interrupt-parent = <&periph_intc>;
			interrupts = <43>;
			sd-uhs-sdr50;
			mmc-hs200-1_8v;
			status = "disabled";
		};

		sdhci1: sdhci@419200 {
			compatible = "brcm,bcm7425-sdhci";
			reg = <0x419200 0x100>;
			interrupt-parent = <&periph_intc>;
			interrupts = <44>;
			sd-uhs-sdr50;
			mmc-hs200-1_8v;
			status = "disabled";
		};

		spi_l2_intc: interrupt-controller@41ad00 {
			compatible = "brcm,l2-intc";
			reg = <0x41ad00 0x30>;
			interrupt-controller;
			#interrupt-cells = <1>;
			interrupt-parent = <&periph_intc>;
			interrupts = <25>;
		};

		qspi: spi@41c000 {
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			compatible = "brcm,spi-bcm-qspi",
				     "brcm,spi-brcmstb-qspi";
			clocks = <&upg_clk>;
			reg = <0x419920 0x4 0x41c200 0x188 0x41c000 0x50>;
			reg-names = "cs_reg", "hif_mspi", "bspi";
			interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
			interrupt-parent = <&spi_l2_intc>;
			interrupt-names = "spi_lr_fullness_reached",
					  "spi_lr_session_aborted",
					  "spi_lr_impatient",
					  "spi_lr_session_done",
					  "spi_lr_overread",
					  "mspi_done",
					  "mspi_halted";
			status = "disabled";
		};

		mspi: spi@409200 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "brcm,spi-bcm-qspi",
				     "brcm,spi-brcmstb-mspi";
			clocks = <&upg_clk>;
			reg = <0x409200 0x180>;
			reg-names = "mspi";
			interrupts = <0x14>;
			interrupt-parent = <&upg_aon_irq0_intc>;
			interrupt-names = "mspi_done";
			status = "disabled";
		};
	};
};
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
8945e37e KC	2	/ {
	3	#address-cells = <1>;
	4	#size-cells = <1>;
	5	compatible = "brcm,bcm7425";
	6
	7	cpus {
	8	#address-cells = <1>;
	9	#size-cells = <0>;
	10
	11	mips-hpt-frequency = <163125000>;
	12
	13	cpu@0 {
	14	compatible = "brcm,bmips5000";
	15	device_type = "cpu";
	16	reg = <0>;
	17	};
	18
	19	cpu@1 {
	20	compatible = "brcm,bmips5000";
	21	device_type = "cpu";
	22	reg = <1>;
	23	};
	24	};
	25
	26	aliases {
	27	uart0 = &uart0;
	28	};
	29
a2c510a2	30	cpu_intc: interrupt-controller {
8945e37e KC	31	#address-cells = <0>;
	32	compatible = "mti,cpu-interrupt-controller";
	33
	34	interrupt-controller;
	35	#interrupt-cells = <1>;
	36	};
	37
	38	clocks {
	39	uart_clk: uart_clk {
	40	compatible = "fixed-clock";
	41	#clock-cells = <0>;
	42	clock-frequency = <81000000>;
	43	};
7bbe59dd JS	44
	45	upg_clk: upg_clk {
	46	compatible = "fixed-clock";
	47	#clock-cells = <0>;
	48	clock-frequency = <27000000>;
	49	};
8945e37e KC	50	};
	51
	52	rdb {
	53	#address-cells = <1>;
	54	#size-cells = <1>;
	55
	56	compatible = "simple-bus";
	57	ranges = <0 0x10000000 0x01000000>;
	58
a2c510a2	59	periph_intc: interrupt-controller@41a400 {
8945e37e KC	60	compatible = "brcm,bcm7038-l1-intc";
	61	reg = <0x41a400 0x30>, <0x41a600 0x30>;
	62
	63	interrupt-controller;
	64	#interrupt-cells = <1>;
	65
	66	interrupt-parent = <&cpu_intc>;
	67	interrupts = <2>, <3>;
	68	};
	69
a2c510a2	70	sun_l2_intc: interrupt-controller@403000 {
8945e37e KC	71	compatible = "brcm,l2-intc";
	72	reg = <0x403000 0x30>;
	73	interrupt-controller;
	74	#interrupt-cells = <1>;
	75	interrupt-parent = <&periph_intc>;
	76	interrupts = <47>;
	77	};
	78
	79	gisb-arb@400000 {
	80	compatible = "brcm,bcm7400-gisb-arb";
	81	reg = <0x400000 0xdc>;
	82	native-endian;
	83	interrupt-parent = <&sun_l2_intc>;
	84	interrupts = <0>, <2>;
	85	brcm,gisb-arb-master-mask = <0x177b>;
	86	brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "pcie_0",
	87	"bsp_0", "rdc_0",
	88	"raaga_0", "avd_1",
	89	"jtag_0", "svd_0",
	90	"vice_0";
	91	};
	92
a2c510a2	93	upg_irq0_intc: interrupt-controller@406780 {
8945e37e KC	94	compatible = "brcm,bcm7120-l2-intc";
	95	reg = <0x406780 0x8>;
	96
5c40d493	97	brcm,int-map-mask = <0x44>, <0x7000000>;
8945e37e KC	98	brcm,int-fwd-mask = <0x70000>;
	99
	100	interrupt-controller;
	101	#interrupt-cells = <1>;
	102
	103	interrupt-parent = <&periph_intc>;
5c40d493 JS	104	interrupts = <55>, <53>;
	105	interrupt-names = "upg_main", "upg_bsc";
	106	};
	107
a2c510a2	108	upg_aon_irq0_intc: interrupt-controller@409480 {
5c40d493 JS	109	compatible = "brcm,bcm7120-l2-intc";
	110	reg = <0x409480 0x8>;
	111
	112	brcm,int-map-mask = <0x40>, <0x18000000>, <0x100000>;
	113	brcm,int-fwd-mask = <0>;
	114	brcm,irq-can-wake;
	115
	116	interrupt-controller;
	117	#interrupt-cells = <1>;
	118
	119	interrupt-parent = <&periph_intc>;
	120	interrupts = <56>, <54>, <59>;
	121	interrupt-names = "upg_main_aon", "upg_bsc_aon",
	122	"upg_spi";
8945e37e KC	123	};
	124
	125	sun_top_ctrl: syscon@404000 {
	126	compatible = "brcm,bcm7425-sun-top-ctrl", "syscon";
	127	reg = <0x404000 0x51c>;
25d6463e	128	native-endian;
8945e37e KC	129	};
	130
	131	reboot {
	132	compatible = "brcm,brcmstb-reboot";
	133	syscon = <&sun_top_ctrl 0x304 0x308>;
	134	};
	135
	136	uart0: serial@406b00 {
	137	compatible = "ns16550a";
	138	reg = <0x406b00 0x20>;
	139	reg-io-width = <0x4>;
	140	reg-shift = <0x2>;
	141	interrupt-parent = <&periph_intc>;
	142	interrupts = <61>;
	143	clocks = <&uart_clk>;
	144	status = "disabled";
	145	};
	146
5c40d493 JS	147	uart1: serial@406b40 {
	148	compatible = "ns16550a";
	149	reg = <0x406b40 0x20>;
	150	reg-io-width = <0x4>;
	151	reg-shift = <0x2>;
	152	interrupt-parent = <&periph_intc>;
	153	interrupts = <62>;
	154	clocks = <&uart_clk>;
	155	status = "disabled";
	156	};
	157
	158	uart2: serial@406b80 {
	159	compatible = "ns16550a";
	160	reg = <0x406b80 0x20>;
	161	reg-io-width = <0x4>;
	162	reg-shift = <0x2>;
	163	interrupt-parent = <&periph_intc>;
	164	interrupts = <63>;
	165	clocks = <&uart_clk>;
	166	status = "disabled";
	167	};
	168
	169	bsca: i2c@409180 {
	170	clock-frequency = <390000>;
	171	compatible = "brcm,brcmstb-i2c";
	172	interrupt-parent = <&upg_aon_irq0_intc>;
	173	reg = <0x409180 0x58>;
	174	interrupts = <27>;
	175	interrupt-names = "upg_bsca";
	176	status = "disabled";
	177	};
	178
	179	bscb: i2c@409400 {
	180	clock-frequency = <390000>;
	181	compatible = "brcm,brcmstb-i2c";
	182	interrupt-parent = <&upg_aon_irq0_intc>;
	183	reg = <0x409400 0x58>;
	184	interrupts = <28>;
	185	interrupt-names = "upg_bscb";
	186	status = "disabled";
	187	};
	188
	189	bscc: i2c@406200 {
	190	clock-frequency = <390000>;
	191	compatible = "brcm,brcmstb-i2c";
	192	interrupt-parent = <&upg_irq0_intc>;
	193	reg = <0x406200 0x58>;
	194	interrupts = <24>;
	195	interrupt-names = "upg_bscc";
	196	status = "disabled";
	197	};
	198
	199	bscd: i2c@406280 {
	200	clock-frequency = <390000>;
	201	compatible = "brcm,brcmstb-i2c";
	202	interrupt-parent = <&upg_irq0_intc>;
	203	reg = <0x406280 0x58>;
	204	interrupts = <25>;
	205	interrupt-names = "upg_bscd";
	206	status = "disabled";
	207	};
	208
	209	bsce: i2c@406300 {
	210	clock-frequency = <390000>;
211	compatible = "brcm,brcmstb-i2c";
212	interrupt-parent = <&upg_irq0_intc>;
213	reg = <0x406300 0x58>;
214	interrupts = <26>;
215	interrupt-names = "upg_bsce";
216	status = "disabled";
217	};
218
7bbe59dd JS	219	pwma: pwm@406580 {
	220	compatible = "brcm,bcm7038-pwm";
	221	reg = <0x406580 0x28>;
	222	#pwm-cells = <2>;
	223	clocks = <&upg_clk>;
	224	status = "disabled";
	225	};
	226
	227	pwmb: pwm@406800 {
	228	compatible = "brcm,bcm7038-pwm";
	229	reg = <0x406800 0x28>;
	230	#pwm-cells = <2>;
	231	clocks = <&upg_clk>;
	232	status = "disabled";
	233	};
	234
c707844d JS	235	aon_pm_l2_intc: interrupt-controller@408440 {
	236	compatible = "brcm,l2-intc";
	237	reg = <0x408440 0x30>;
	238	interrupt-controller;
	239	#interrupt-cells = <1>;
	240	interrupt-parent = <&periph_intc>;
	241	interrupts = <49>;
	242	brcm,irq-can-wake;
	243	};
	244
	245	upg_gio: gpio@406700 {
	246	compatible = "brcm,brcmstb-gpio";
	247	reg = <0x406700 0x80>;
	248	#gpio-cells = <2>;
	249	#interrupt-cells = <2>;
	250	gpio-controller;
	251	interrupt-controller;
	252	interrupt-parent = <&upg_irq0_intc>;
	253	interrupts = <6>;
	254	brcm,gpio-bank-widths = <32 32 32 21>;
	255	};
	256
	257	upg_gio_aon: gpio@4094c0 {
	258	compatible = "brcm,brcmstb-gpio";
	259	reg = <0x4094c0 0x40>;
	260	#gpio-cells = <2>;
	261	#interrupt-cells = <2>;
	262	gpio-controller;
	263	interrupt-controller;
	264	interrupt-parent = <&upg_aon_irq0_intc>;
	265	interrupts = <6>;
	266	interrupts-extended = <&upg_aon_irq0_intc 6>,
	267	<&aon_pm_l2_intc 5>;
	268	wakeup-source;
	269	brcm,gpio-bank-widths = <18 4>;
	270	};
	271
8945e37e KC	272	enet0: ethernet@b80000 {
	273	phy-mode = "internal";
	274	phy-handle = <&phy1>;
	275	mac-address = [ 00 10 18 36 23 1a ];
	276	compatible = "brcm,genet-v3";
	277	#address-cells = <0x1>;
	278	#size-cells = <0x1>;
	279	reg = <0xb80000 0x11c88>;
	280	interrupts = <17>, <18>;
	281	interrupt-parent = <&periph_intc>;
	282	status = "disabled";
	283
	284	mdio@e14 {
	285	compatible = "brcm,genet-mdio-v3";
	286	#address-cells = <0x1>;
	287	#size-cells = <0x0>;
	288	reg = <0xe14 0x8>;
	289
	290	phy1: ethernet-phy@1 {
	291	max-speed = <100>;
	292	reg = <0x1>;
	293	compatible = "brcm,40nm-ephy",
	294	"ethernet-phy-ieee802.3-c22";
	295	};
	296	};
	297	};
	298
	299	ehci0: usb@480300 {
	300	compatible = "brcm,bcm7425-ehci", "generic-ehci";
	301	reg = <0x480300 0x100>;
	302	native-endian;
	303	interrupt-parent = <&periph_intc>;
	304	interrupts = <65>;
	305	status = "disabled";
	306	};
	307
	308	ohci0: usb@480400 {
	309	compatible = "brcm,bcm7425-ohci", "generic-ohci";
	310	reg = <0x480400 0x100>;
	311	native-endian;
	312	no-big-frame-no;
	313	interrupt-parent = <&periph_intc>;
	314	interrupts = <67>;
	315	status = "disabled";
	316	};
	317
	318	ehci1: usb@480500 {
	319	compatible = "brcm,bcm7425-ehci", "generic-ehci";
	320	reg = <0x480500 0x100>;
	321	native-endian;
	322	interrupt-parent = <&periph_intc>;
	323	interrupts = <66>;
	324	status = "disabled";
	325	};
	326
	327	ohci1: usb@480600 {
	328	compatible = "brcm,bcm7425-ohci", "generic-ohci";
	329	reg = <0x480600 0x100>;
	330	native-endian;
	331	no-big-frame-no;
	332	interrupt-parent = <&periph_intc>;
	333	interrupts = <68>;
	334	status = "disabled";
	335	};
336
337	ehci2: usb@490300 {
338	compatible = "brcm,bcm7425-ehci", "generic-ehci";
339	reg = <0x490300 0x100>;
340	native-endian;
341	interrupt-parent = <&periph_intc>;
342	interrupts = <70>;
343	status = "disabled";
344	};
345
346	ohci2: usb@490400 {
347	compatible = "brcm,bcm7425-ohci", "generic-ohci";
348	reg = <0x490400 0x100>;
349	native-endian;
350	no-big-frame-no;
351	interrupt-parent = <&periph_intc>;
352	interrupts = <72>;
353	status = "disabled";
354	};
355
356	ehci3: usb@490500 {
357	compatible = "brcm,bcm7425-ehci", "generic-ehci";
358	reg = <0x490500 0x100>;
359	native-endian;
360	interrupt-parent = <&periph_intc>;
361	interrupts = <71>;
362	status = "disabled";
363	};
364
365	ohci3: usb@490600 {
366	compatible = "brcm,bcm7425-ohci", "generic-ohci";
367	reg = <0x490600 0x100>;
368	native-endian;
369	no-big-frame-no;
370	interrupt-parent = <&periph_intc>;
371	interrupts = <73>;
372	status = "disabled";
373	};
ce6df637	374
cfc8be04 JS	375	hif_l2_intc: interrupt-controller@41a000 {
	376	compatible = "brcm,l2-intc";
	377	reg = <0x41a000 0x30>;
	378	interrupt-controller;
	379	#interrupt-cells = <1>;
	380	interrupt-parent = <&periph_intc>;
	381	interrupts = <24>;
	382	};
	383
	384	nand: nand@41b800 {
	385	compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
	386	#address-cells = <1>;
	387	#size-cells = <0>;
	388	reg-names = "nand";
	389	reg = <0x41b800 0x400>;
	390	interrupt-parent = <&hif_l2_intc>;
	391	interrupts = <24>;
	392	status = "disabled";
	393	};
	394
ce6df637 JS	395	sata: sata@181000 {
	396	compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
	397	reg-names = "ahci", "top-ctrl";
	398	reg = <0x181000 0xa9c>, <0x180020 0x1c>;
	399	interrupt-parent = <&periph_intc>;
69ca2b81	400	interrupts = <41>;
ce6df637 JS	401	#address-cells = <1>;
ce6df637 JS	402	#size-cells = <0>;
ce6df637 JS	403	status = "disabled";
	404
	405	sata0: sata-port@0 {
	406	reg = <0>;
	407	phys = <&sata_phy0>;
	408	};
	409
	410	sata1: sata-port@1 {
	411	reg = <1>;
	412	phys = <&sata_phy1>;
	413	};
	414	};
	415
69ca2b81	416	sata_phy: sata-phy@180100 {
ce6df637 JS	417	compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
	418	reg = <0x180100 0x0eff>;
	419	reg-names = "phy";
	420	#address-cells = <1>;
	421	#size-cells = <0>;
	422	status = "disabled";
	423
	424	sata_phy0: sata-phy@0 {
	425	reg = <0>;
	426	#phy-cells = <0>;
	427	};
	428
	429	sata_phy1: sata-phy@1 {
	430	reg = <1>;
	431	#phy-cells = <0>;
	432	};
	433	};
b2420e27 JS	434
	435	sdhci0: sdhci@419000 {
	436	compatible = "brcm,bcm7425-sdhci";
	437	reg = <0x419000 0x100>;
	438	interrupt-parent = <&periph_intc>;
	439	interrupts = <43>;
	440	sd-uhs-sdr50;
	441	mmc-hs200-1_8v;
	442	status = "disabled";
	443	};
	444
	445	sdhci1: sdhci@419200 {
	446	compatible = "brcm,bcm7425-sdhci";
	447	reg = <0x419200 0x100>;
	448	interrupt-parent = <&periph_intc>;
	449	interrupts = <44>;
	450	sd-uhs-sdr50;
	451	mmc-hs200-1_8v;
	452	status = "disabled";
	453	};
d783738c JS	454
	455	spi_l2_intc: interrupt-controller@41ad00 {
	456	compatible = "brcm,l2-intc";
	457	reg = <0x41ad00 0x30>;
	458	interrupt-controller;
	459	#interrupt-cells = <1>;
	460	interrupt-parent = <&periph_intc>;
	461	interrupts = <25>;
	462	};
	463
	464	qspi: spi@41c000 {
	465	#address-cells = <0x1>;
	466	#size-cells = <0x0>;
	467	compatible = "brcm,spi-bcm-qspi",
	468	"brcm,spi-brcmstb-qspi";
	469	clocks = <&upg_clk>;
	470	reg = <0x419920 0x4 0x41c200 0x188 0x41c000 0x50>;
	471	reg-names = "cs_reg", "hif_mspi", "bspi";
	472	interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
	473	interrupt-parent = <&spi_l2_intc>;
	474	interrupt-names = "spi_lr_fullness_reached",
	475	"spi_lr_session_aborted",
	476	"spi_lr_impatient",
	477	"spi_lr_session_done",
	478	"spi_lr_overread",
	479	"mspi_done",
	480	"mspi_halted";
	481	status = "disabled";
	482	};
	483
	484	mspi: spi@409200 {
	485	#address-cells = <1>;
	486	#size-cells = <0>;
	487	compatible = "brcm,spi-bcm-qspi",
	488	"brcm,spi-brcmstb-mspi";
	489	clocks = <&upg_clk>;
	490	reg = <0x409200 0x180>;
	491	reg-names = "mspi";
	492	interrupts = <0x14>;
	493	interrupt-parent = <&upg_aon_irq0_intc>;
	494	interrupt-names = "mspi_done";
	495	status = "disabled";
	496	};
8945e37e KC	497	};
8945e37e KC	498	};