[mirror_ubuntu-artful-kernel.git] / arch / mips / cavium-octeon / Kconfig

if CPU_CAVIUM_OCTEON

config CAVIUM_CN63XXP1
	bool "Enable CN63XXP1 errata workarounds"
	default "n"
	help
	  The CN63XXP1 chip requires build time workarounds to
	  function reliably, select this option to enable them.  These
	  workarounds will cause a slight decrease in performance on
	  non-CN63XXP1 hardware, so it is recommended to select "n"
	  unless it is known the workarounds are needed.

config CAVIUM_OCTEON_CVMSEG_SIZE
	int "Number of L1 cache lines reserved for CVMSEG memory"
	range 0 54
	default 1
	help
	  CVMSEG LM is a segment that accesses portions of the dcache as a
	  local memory; the larger CVMSEG is, the smaller the cache is.
	  This selects the size of CVMSEG LM, which is in cache blocks. The
	  legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
	  between zero and 6192 bytes).

endif # CPU_CAVIUM_OCTEON

if CAVIUM_OCTEON_SOC

config CAVIUM_OCTEON_LOCK_L2
	bool "Lock often used kernel code in the L2"
	default "y"
	help
	  Enable locking parts of the kernel into the L2 cache.

config CAVIUM_OCTEON_LOCK_L2_TLB
	bool "Lock the TLB handler in L2"
	depends on CAVIUM_OCTEON_LOCK_L2
	default "y"
	help
	  Lock the low level TLB fast path into L2.

config CAVIUM_OCTEON_LOCK_L2_EXCEPTION
	bool "Lock the exception handler in L2"
	depends on CAVIUM_OCTEON_LOCK_L2
	default "y"
	help
	  Lock the low level exception handler into L2.

config CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
	bool "Lock the interrupt handler in L2"
	depends on CAVIUM_OCTEON_LOCK_L2
	default "y"
	help
	  Lock the low level interrupt handler into L2.

config CAVIUM_OCTEON_LOCK_L2_INTERRUPT
	bool "Lock the 2nd level interrupt handler in L2"
	depends on CAVIUM_OCTEON_LOCK_L2
	default "y"
	help
	  Lock the 2nd level interrupt handler in L2.

config CAVIUM_OCTEON_LOCK_L2_MEMCPY
	bool "Lock memcpy() in L2"
	depends on CAVIUM_OCTEON_LOCK_L2
	default "y"
	help
	  Lock the kernel's implementation of memcpy() into L2.

config IOMMU_HELPER
	bool

config NEED_SG_DMA_LENGTH
	bool

config SWIOTLB
	def_bool y
	select IOMMU_HELPER
	select NEED_SG_DMA_LENGTH

config OCTEON_ILM
	tristate "Module to measure interrupt latency using Octeon CIU Timer"
	help
	  This driver is a module to measure interrupt latency using the
	  the CIU Timers on Octeon.

	  To compile this driver as a module, choose M here.  The module
	  will be called octeon-ilm

endif # CAVIUM_OCTEON_SOC
Commit	Line	Data
23a271ec	1	if CPU_CAVIUM_OCTEON
5b3b1688	2
c9941158	3	config CAVIUM_CN63XXP1
f54619f2	4	bool "Enable CN63XXP1 errata workarounds"
c9941158 DD	5	default "n"
	6	help
	7	The CN63XXP1 chip requires build time workarounds to
	8	function reliably, select this option to enable them. These
	9	workarounds will cause a slight decrease in performance on
	10	non-CN63XXP1 hardware, so it is recommended to select "n"
	11	unless it is known the workarounds are needed.
	12
8a837cdb DD	13	config CAVIUM_OCTEON_CVMSEG_SIZE
	14	int "Number of L1 cache lines reserved for CVMSEG memory"
	15	range 0 54
	16	default 1
	17	help
	18	CVMSEG LM is a segment that accesses portions of the dcache as a
	19	local memory; the larger CVMSEG is, the smaller the cache is.
	20	This selects the size of CVMSEG LM, which is in cache blocks. The
	21	legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
	22	between zero and 6192 bytes).
	23
9ddebc46 DD	24	endif # CPU_CAVIUM_OCTEON
	25
	26	if CAVIUM_OCTEON_SOC
	27
5b3b1688 DD	28	config CAVIUM_OCTEON_LOCK_L2
5b3b1688 DD	29	bool "Lock often used kernel code in the L2"
5b3b1688 DD	30	default "y"
	31	help
	32	Enable locking parts of the kernel into the L2 cache.
	33
	34	config CAVIUM_OCTEON_LOCK_L2_TLB
	35	bool "Lock the TLB handler in L2"
	36	depends on CAVIUM_OCTEON_LOCK_L2
	37	default "y"
	38	help
	39	Lock the low level TLB fast path into L2.
	40
	41	config CAVIUM_OCTEON_LOCK_L2_EXCEPTION
	42	bool "Lock the exception handler in L2"
	43	depends on CAVIUM_OCTEON_LOCK_L2
	44	default "y"
	45	help
	46	Lock the low level exception handler into L2.
	47
	48	config CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
	49	bool "Lock the interrupt handler in L2"
	50	depends on CAVIUM_OCTEON_LOCK_L2
	51	default "y"
	52	help
	53	Lock the low level interrupt handler into L2.
	54
	55	config CAVIUM_OCTEON_LOCK_L2_INTERRUPT
	56	bool "Lock the 2nd level interrupt handler in L2"
	57	depends on CAVIUM_OCTEON_LOCK_L2
	58	default "y"
	59	help
	60	Lock the 2nd level interrupt handler in L2.
	61
	62	config CAVIUM_OCTEON_LOCK_L2_MEMCPY
	63	bool "Lock memcpy() in L2"
	64	depends on CAVIUM_OCTEON_LOCK_L2
	65	default "y"
	66	help
	67	Lock the kernel's implementation of memcpy() into L2.
	68
b93b2abc DD	69	config IOMMU_HELPER
	70	bool
	71
	72	config NEED_SG_DMA_LENGTH
	73	bool
	74
	75	config SWIOTLB
	76	def_bool y
b93b2abc DD	77	select IOMMU_HELPER
b93b2abc DD	78	select NEED_SG_DMA_LENGTH
23a271ec	79
0e49caf6 VS	80	config OCTEON_ILM
	81	tristate "Module to measure interrupt latency using Octeon CIU Timer"
	82	help
	83	This driver is a module to measure interrupt latency using the
	84	the CIU Timers on Octeon.
	85
	86	To compile this driver as a module, choose M here. The module
	87	will be called octeon-ilm
	88
9ddebc46	89	endif # CAVIUM_OCTEON_SOC