[mirror_ubuntu-kernels.git] / arch / mips / cavium-octeon / dma-octeon.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2000  Ani Joshi <ajoshi@unixbox.com>
 * Copyright (C) 2000, 2001  Ralf Baechle <ralf@gnu.org>
 * Copyright (C) 2005 Ilya A. Volynets-Evenbakh <ilya@total-knowledge.com>
 * swiped from i386, and cloned for MIPS by Geert, polished by Ralf.
 * IP32 changes by Ilya.
 * Copyright (C) 2010 Cavium Networks, Inc.
 */
#include <linux/dma-direct.h>
#include <linux/memblock.h>
#include <linux/swiotlb.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/mm.h>

#include <asm/bootinfo.h>

#include <asm/octeon/octeon.h>

#ifdef CONFIG_PCI
#include <linux/pci.h>
#include <asm/octeon/pci-octeon.h>
#include <asm/octeon/cvmx-npi-defs.h>
#include <asm/octeon/cvmx-pci-defs.h>

struct octeon_dma_map_ops {
	dma_addr_t (*phys_to_dma)(struct device *dev, phys_addr_t paddr);
	phys_addr_t (*dma_to_phys)(struct device *dev, dma_addr_t daddr);
};

static dma_addr_t octeon_hole_phys_to_dma(phys_addr_t paddr)
{
	if (paddr >= CVMX_PCIE_BAR1_PHYS_BASE && paddr < (CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_PHYS_SIZE))
		return paddr - CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_RC_BASE;
	else
		return paddr;
}

static phys_addr_t octeon_hole_dma_to_phys(dma_addr_t daddr)
{
	if (daddr >= CVMX_PCIE_BAR1_RC_BASE)
		return daddr + CVMX_PCIE_BAR1_PHYS_BASE - CVMX_PCIE_BAR1_RC_BASE;
	else
		return daddr;
}

static dma_addr_t octeon_gen1_phys_to_dma(struct device *dev, phys_addr_t paddr)
{
	if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
		paddr -= 0x400000000ull;
	return octeon_hole_phys_to_dma(paddr);
}

static phys_addr_t octeon_gen1_dma_to_phys(struct device *dev, dma_addr_t daddr)
{
	daddr = octeon_hole_dma_to_phys(daddr);

	if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
		daddr += 0x400000000ull;

	return daddr;
}

static const struct octeon_dma_map_ops octeon_gen1_ops = {
	.phys_to_dma	= octeon_gen1_phys_to_dma,
	.dma_to_phys	= octeon_gen1_dma_to_phys,
};

static dma_addr_t octeon_gen2_phys_to_dma(struct device *dev, phys_addr_t paddr)
{
	return octeon_hole_phys_to_dma(paddr);
}

static phys_addr_t octeon_gen2_dma_to_phys(struct device *dev, dma_addr_t daddr)
{
	return octeon_hole_dma_to_phys(daddr);
}

static const struct octeon_dma_map_ops octeon_gen2_ops = {
	.phys_to_dma	= octeon_gen2_phys_to_dma,
	.dma_to_phys	= octeon_gen2_dma_to_phys,
};

static dma_addr_t octeon_big_phys_to_dma(struct device *dev, phys_addr_t paddr)
{
	if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
		paddr -= 0x400000000ull;

	/* Anything in the BAR1 hole or above goes via BAR2 */
	if (paddr >= 0xf0000000ull)
		paddr = OCTEON_BAR2_PCI_ADDRESS + paddr;

	return paddr;
}

static phys_addr_t octeon_big_dma_to_phys(struct device *dev, dma_addr_t daddr)
{
	if (daddr >= OCTEON_BAR2_PCI_ADDRESS)
		daddr -= OCTEON_BAR2_PCI_ADDRESS;

	if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
		daddr += 0x400000000ull;
	return daddr;
}

static const struct octeon_dma_map_ops octeon_big_ops = {
	.phys_to_dma	= octeon_big_phys_to_dma,
	.dma_to_phys	= octeon_big_dma_to_phys,
};

static dma_addr_t octeon_small_phys_to_dma(struct device *dev,
					   phys_addr_t paddr)
{
	if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
		paddr -= 0x400000000ull;

	/* Anything not in the BAR1 range goes via BAR2 */
	if (paddr >= octeon_bar1_pci_phys && paddr < octeon_bar1_pci_phys + 0x8000000ull)
		paddr = paddr - octeon_bar1_pci_phys;
	else
		paddr = OCTEON_BAR2_PCI_ADDRESS + paddr;

	return paddr;
}

static phys_addr_t octeon_small_dma_to_phys(struct device *dev,
					    dma_addr_t daddr)
{
	if (daddr >= OCTEON_BAR2_PCI_ADDRESS)
		daddr -= OCTEON_BAR2_PCI_ADDRESS;
	else
		daddr += octeon_bar1_pci_phys;

	if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
		daddr += 0x400000000ull;
	return daddr;
}

static const struct octeon_dma_map_ops octeon_small_ops = {
	.phys_to_dma	= octeon_small_phys_to_dma,
	.dma_to_phys	= octeon_small_dma_to_phys,
};

static const struct octeon_dma_map_ops *octeon_pci_dma_ops;

void __init octeon_pci_dma_init(void)
{
	switch (octeon_dma_bar_type) {
	case OCTEON_DMA_BAR_TYPE_PCIE:
		octeon_pci_dma_ops = &octeon_gen1_ops;
		break;
	case OCTEON_DMA_BAR_TYPE_PCIE2:
		octeon_pci_dma_ops = &octeon_gen2_ops;
		break;
	case OCTEON_DMA_BAR_TYPE_BIG:
		octeon_pci_dma_ops = &octeon_big_ops;
		break;
	case OCTEON_DMA_BAR_TYPE_SMALL:
		octeon_pci_dma_ops = &octeon_small_ops;
		break;
	default:
		BUG();
	}
}
#endif /* CONFIG_PCI */

dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
{
#ifdef CONFIG_PCI
	if (dev && dev_is_pci(dev))
		return octeon_pci_dma_ops->phys_to_dma(dev, paddr);
#endif
	return paddr;
}

phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr)
{
#ifdef CONFIG_PCI
	if (dev && dev_is_pci(dev))
		return octeon_pci_dma_ops->dma_to_phys(dev, daddr);
#endif
	return daddr;
}

char *octeon_swiotlb;

void __init plat_swiotlb_setup(void)
{
	int i;
	phys_addr_t max_addr;
	phys_addr_t addr_size;
	size_t swiotlbsize;
	unsigned long swiotlb_nslabs;

	max_addr = 0;
	addr_size = 0;

	for (i = 0 ; i < boot_mem_map.nr_map; i++) {
		struct boot_mem_map_entry *e = &boot_mem_map.map[i];
		if (e->type != BOOT_MEM_RAM && e->type != BOOT_MEM_INIT_RAM)
			continue;

		/* These addresses map low for PCI. */
		if (e->addr > 0x410000000ull && !OCTEON_IS_OCTEON2())
			continue;

		addr_size += e->size;

		if (max_addr < e->addr + e->size)
			max_addr = e->addr + e->size;

	}

	swiotlbsize = PAGE_SIZE;

#ifdef CONFIG_PCI
	/*
	 * For OCTEON_DMA_BAR_TYPE_SMALL, size the iotlb at 1/4 memory
	 * size to a maximum of 64MB
	 */
	if (OCTEON_IS_MODEL(OCTEON_CN31XX)
	    || OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) {
		swiotlbsize = addr_size / 4;
		if (swiotlbsize > 64 * (1<<20))
			swiotlbsize = 64 * (1<<20);
	} else if (max_addr > 0xf0000000ul) {
		/*
		 * Otherwise only allocate a big iotlb if there is
		 * memory past the BAR1 hole.
		 */
		swiotlbsize = 64 * (1<<20);
	}
#endif
#ifdef CONFIG_USB_OHCI_HCD_PLATFORM
	/* OCTEON II ohci is only 32-bit. */
	if (OCTEON_IS_OCTEON2() && max_addr >= 0x100000000ul)
		swiotlbsize = 64 * (1<<20);
#endif
	swiotlb_nslabs = swiotlbsize >> IO_TLB_SHIFT;
	swiotlb_nslabs = ALIGN(swiotlb_nslabs, IO_TLB_SEGSIZE);
	swiotlbsize = swiotlb_nslabs << IO_TLB_SHIFT;

	octeon_swiotlb = memblock_alloc_low(swiotlbsize, PAGE_SIZE);
	if (!octeon_swiotlb)
		panic("%s: Failed to allocate %zu bytes align=%lx\n",
		      __func__, swiotlbsize, PAGE_SIZE);

	if (swiotlb_init_with_tbl(octeon_swiotlb, swiotlb_nslabs, 1) == -ENOMEM)
		panic("Cannot allocate SWIOTLB buffer");
}
Commit	Line	Data
5b3b1688 DD	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2000 Ani Joshi <ajoshi@unixbox.com>
	7	* Copyright (C) 2000, 2001 Ralf Baechle <ralf@gnu.org>
	8	* Copyright (C) 2005 Ilya A. Volynets-Evenbakh <ilya@total-knowledge.com>
	9	* swiped from i386, and cloned for MIPS by Geert, polished by Ralf.
	10	* IP32 changes by Ilya.
b93b2abc	11	* Copyright (C) 2010 Cavium Networks, Inc.
5b3b1688	12	*/
b6e05477	13	#include <linux/dma-direct.h>
57c8a661	14	#include <linux/memblock.h>
b93b2abc DD	15	#include <linux/swiotlb.h>
	16	#include <linux/types.h>
	17	#include <linux/init.h>
	18	#include <linux/mm.h>
e8635b48	19
b93b2abc	20	#include <asm/bootinfo.h>
e8635b48 DD	21
e8635b48 DD	22	#include <asm/octeon/octeon.h>
b93b2abc DD	23
b93b2abc DD	24	#ifdef CONFIG_PCI
97f9f976	25	#include <linux/pci.h>
b93b2abc	26	#include <asm/octeon/pci-octeon.h>
e8635b48 DD	27	#include <asm/octeon/cvmx-npi-defs.h>
e8635b48 DD	28	#include <asm/octeon/cvmx-pci-defs.h>
5b3b1688	29
97f9f976 CH	30	struct octeon_dma_map_ops {
	31	dma_addr_t (phys_to_dma)(struct device dev, phys_addr_t paddr);
	32	phys_addr_t (dma_to_phys)(struct device dev, dma_addr_t daddr);
	33	};
	34
b93b2abc DD	35	static dma_addr_t octeon_hole_phys_to_dma(phys_addr_t paddr)
	36	{
	37	if (paddr >= CVMX_PCIE_BAR1_PHYS_BASE && paddr < (CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_PHYS_SIZE))
	38	return paddr - CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_RC_BASE;
	39	else
	40	return paddr;
	41	}
5b3b1688	42
b93b2abc DD	43	static phys_addr_t octeon_hole_dma_to_phys(dma_addr_t daddr)
	44	{
	45	if (daddr >= CVMX_PCIE_BAR1_RC_BASE)
	46	return daddr + CVMX_PCIE_BAR1_PHYS_BASE - CVMX_PCIE_BAR1_RC_BASE;
	47	else
	48	return daddr;
	49	}
	50
	51	static dma_addr_t octeon_gen1_phys_to_dma(struct device *dev, phys_addr_t paddr)
	52	{
	53	if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
	54	paddr -= 0x400000000ull;
	55	return octeon_hole_phys_to_dma(paddr);
	56	}
e8635b48	57
b93b2abc DD	58	static phys_addr_t octeon_gen1_dma_to_phys(struct device *dev, dma_addr_t daddr)
	59	{
	60	daddr = octeon_hole_dma_to_phys(daddr);
e8635b48	61
b93b2abc DD	62	if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
b93b2abc DD	63	daddr += 0x400000000ull;
e8635b48	64
b93b2abc DD	65	return daddr;
b93b2abc DD	66	}
e8635b48	67
97f9f976 CH	68	static const struct octeon_dma_map_ops octeon_gen1_ops = {
	69	.phys_to_dma = octeon_gen1_phys_to_dma,
	70	.dma_to_phys = octeon_gen1_dma_to_phys,
	71	};
	72
714c1f5c DD	73	static dma_addr_t octeon_gen2_phys_to_dma(struct device *dev, phys_addr_t paddr)
	74	{
	75	return octeon_hole_phys_to_dma(paddr);
	76	}
	77
	78	static phys_addr_t octeon_gen2_dma_to_phys(struct device *dev, dma_addr_t daddr)
	79	{
	80	return octeon_hole_dma_to_phys(daddr);
	81	}
	82
97f9f976 CH	83	static const struct octeon_dma_map_ops octeon_gen2_ops = {
	84	.phys_to_dma = octeon_gen2_phys_to_dma,
	85	.dma_to_phys = octeon_gen2_dma_to_phys,
	86	};
	87
b93b2abc	88	static dma_addr_t octeon_big_phys_to_dma(struct device *dev, phys_addr_t paddr)
5b3b1688	89	{
b93b2abc DD	90	if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
	91	paddr -= 0x400000000ull;
	92
	93	/* Anything in the BAR1 hole or above goes via BAR2 */
	94	if (paddr >= 0xf0000000ull)
	95	paddr = OCTEON_BAR2_PCI_ADDRESS + paddr;
	96
	97	return paddr;
	98	}
	99
	100	static phys_addr_t octeon_big_dma_to_phys(struct device *dev, dma_addr_t daddr)
	101	{
	102	if (daddr >= OCTEON_BAR2_PCI_ADDRESS)
	103	daddr -= OCTEON_BAR2_PCI_ADDRESS;
	104
	105	if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
	106	daddr += 0x400000000ull;
	107	return daddr;
	108	}
	109
97f9f976 CH	110	static const struct octeon_dma_map_ops octeon_big_ops = {
	111	.phys_to_dma = octeon_big_phys_to_dma,
	112	.dma_to_phys = octeon_big_dma_to_phys,
	113	};
	114
b93b2abc DD	115	static dma_addr_t octeon_small_phys_to_dma(struct device *dev,
	116	phys_addr_t paddr)
	117	{
	118	if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
	119	paddr -= 0x400000000ull;
	120
	121	/* Anything not in the BAR1 range goes via BAR2 */
	122	if (paddr >= octeon_bar1_pci_phys && paddr < octeon_bar1_pci_phys + 0x8000000ull)
	123	paddr = paddr - octeon_bar1_pci_phys;
	124	else
	125	paddr = OCTEON_BAR2_PCI_ADDRESS + paddr;
	126
	127	return paddr;
	128	}
	129
	130	static phys_addr_t octeon_small_dma_to_phys(struct device *dev,
	131	dma_addr_t daddr)
	132	{
	133	if (daddr >= OCTEON_BAR2_PCI_ADDRESS)
	134	daddr -= OCTEON_BAR2_PCI_ADDRESS;
	135	else
	136	daddr += octeon_bar1_pci_phys;
	137
	138	if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
	139	daddr += 0x400000000ull;
	140	return daddr;
	141	}
	142
97f9f976 CH	143	static const struct octeon_dma_map_ops octeon_small_ops = {
	144	.phys_to_dma = octeon_small_phys_to_dma,
	145	.dma_to_phys = octeon_small_dma_to_phys,
	146	};
	147
	148	static const struct octeon_dma_map_ops *octeon_pci_dma_ops;
	149
	150	void __init octeon_pci_dma_init(void)
	151	{
	152	switch (octeon_dma_bar_type) {
	153	case OCTEON_DMA_BAR_TYPE_PCIE:
	154	octeon_pci_dma_ops = &octeon_gen1_ops;
	155	break;
	156	case OCTEON_DMA_BAR_TYPE_PCIE2:
	157	octeon_pci_dma_ops = &octeon_gen2_ops;
	158	break;
	159	case OCTEON_DMA_BAR_TYPE_BIG:
	160	octeon_pci_dma_ops = &octeon_big_ops;
	161	break;
	162	case OCTEON_DMA_BAR_TYPE_SMALL:
	163	octeon_pci_dma_ops = &octeon_small_ops;
	164	break;
	165	default:
	166	BUG();
	167	}
	168	}
b93b2abc DD	169	#endif /* CONFIG_PCI */
b93b2abc DD	170
b6e05477	171	dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
b93b2abc	172	{
97f9f976 CH	173	#ifdef CONFIG_PCI
	174	if (dev && dev_is_pci(dev))
	175	return octeon_pci_dma_ops->phys_to_dma(dev, paddr);
	176	#endif
	177	return paddr;
b93b2abc	178	}
b93b2abc	179
b6e05477	180	phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t daddr)
b93b2abc	181	{
97f9f976 CH	182	#ifdef CONFIG_PCI
	183	if (dev && dev_is_pci(dev))
	184	return octeon_pci_dma_ops->dma_to_phys(dev, daddr);
	185	#endif
	186	return daddr;
b93b2abc	187	}
b93b2abc	188
b93b2abc DD	189	char *octeon_swiotlb;
	190
	191	void __init plat_swiotlb_setup(void)
	192	{
	193	int i;
15d45cce RB	194	phys_addr_t max_addr;
15d45cce RB	195	phys_addr_t addr_size;
b93b2abc DD	196	size_t swiotlbsize;
	197	unsigned long swiotlb_nslabs;
	198
	199	max_addr = 0;
	200	addr_size = 0;
	201
	202	for (i = 0 ; i < boot_mem_map.nr_map; i++) {
	203	struct boot_mem_map_entry *e = &boot_mem_map.map[i];
714c1f5c	204	if (e->type != BOOT_MEM_RAM && e->type != BOOT_MEM_INIT_RAM)
b93b2abc DD	205	continue;
	206
	207	/* These addresses map low for PCI. */
debe6a62	208	if (e->addr > 0x410000000ull && !OCTEON_IS_OCTEON2())
b93b2abc DD	209	continue;
	210
	211	addr_size += e->size;
	212
	213	if (max_addr < e->addr + e->size)
	214	max_addr = e->addr + e->size;
	215
	216	}
	217
	218	swiotlbsize = PAGE_SIZE;
	219
	220	#ifdef CONFIG_PCI
e8635b48	221	/*
b93b2abc DD	222	* For OCTEON_DMA_BAR_TYPE_SMALL, size the iotlb at 1/4 memory
b93b2abc DD	223	* size to a maximum of 64MB
e8635b48	224	*/
b93b2abc DD	225	if (OCTEON_IS_MODEL(OCTEON_CN31XX)
	226	\|\| OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) {
	227	swiotlbsize = addr_size / 4;
	228	if (swiotlbsize > 64 * (1<<20))
	229	swiotlbsize = 64 * (1<<20);
	230	} else if (max_addr > 0xf0000000ul) {
	231	/*
	232	* Otherwise only allocate a big iotlb if there is
	233	* memory past the BAR1 hole.
	234	*/
	235	swiotlbsize = 64 * (1<<20);
	236	}
714c1f5c	237	#endif
a8667d70	238	#ifdef CONFIG_USB_OHCI_HCD_PLATFORM
714c1f5c	239	/* OCTEON II ohci is only 32-bit. */
debe6a62	240	if (OCTEON_IS_OCTEON2() && max_addr >= 0x100000000ul)
714c1f5c	241	swiotlbsize = 64 * (1<<20);
b93b2abc DD	242	#endif
	243	swiotlb_nslabs = swiotlbsize >> IO_TLB_SHIFT;
	244	swiotlb_nslabs = ALIGN(swiotlb_nslabs, IO_TLB_SEGSIZE);
	245	swiotlbsize = swiotlb_nslabs << IO_TLB_SHIFT;
	246
e8625dce	247	octeon_swiotlb = memblock_alloc_low(swiotlbsize, PAGE_SIZE);
8a7f97b9 MR	248	if (!octeon_swiotlb)
	249	panic("%s: Failed to allocate %zu bytes align=%lx\n",
	250	__func__, swiotlbsize, PAGE_SIZE);
e8635b48	251
ac2cbab2 YL	252	if (swiotlb_init_with_tbl(octeon_swiotlb, swiotlb_nslabs, 1) == -ENOMEM)
ac2cbab2 YL	253	panic("Cannot allocate SWIOTLB buffer");
b93b2abc	254	}