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80ff0fd3 DD |
1 | /***********************license start*************** |
2 | * Author: Cavium Networks | |
3 | * | |
4 | * Contact: support@caviumnetworks.com | |
5 | * This file is part of the OCTEON SDK | |
6 | * | |
7 | * Copyright (c) 2003-2008 Cavium Networks | |
8 | * | |
9 | * This file is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License, Version 2, as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This file is distributed in the hope that it will be useful, but | |
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | |
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | |
16 | * NONINFRINGEMENT. See the GNU General Public License for more | |
17 | * details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this file; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
22 | * or visit http://www.gnu.org/licenses/. | |
23 | * | |
24 | * This file may also be available under a different license from Cavium. | |
25 | * Contact Cavium Networks for more information | |
26 | ***********************license end**************************************/ | |
27 | ||
28 | /* | |
29 | * | |
30 | * Helper functions to abstract board specific data about | |
31 | * network ports from the rest of the cvmx-helper files. | |
32 | */ | |
33 | ||
34 | #include <asm/octeon/octeon.h> | |
35 | #include <asm/octeon/cvmx-bootinfo.h> | |
36 | ||
af866496 | 37 | #include <asm/octeon/cvmx-config.h> |
80ff0fd3 | 38 | |
af866496 | 39 | #include <asm/octeon/cvmx-mdio.h> |
80ff0fd3 | 40 | |
af866496 DD |
41 | #include <asm/octeon/cvmx-helper.h> |
42 | #include <asm/octeon/cvmx-helper-util.h> | |
43 | #include <asm/octeon/cvmx-helper-board.h> | |
80ff0fd3 | 44 | |
af866496 DD |
45 | #include <asm/octeon/cvmx-gmxx-defs.h> |
46 | #include <asm/octeon/cvmx-asxx-defs.h> | |
80ff0fd3 DD |
47 | |
48 | /** | |
49 | * cvmx_override_board_link_get(int ipd_port) is a function | |
50 | * pointer. It is meant to allow customization of the process of | |
51 | * talking to a PHY to determine link speed. It is called every | |
52 | * time a PHY must be polled for link status. Users should set | |
53 | * this pointer to a function before calling any cvmx-helper | |
54 | * operations. | |
55 | */ | |
56 | cvmx_helper_link_info_t(*cvmx_override_board_link_get) (int ipd_port) = | |
57 | NULL; | |
58 | ||
59 | /** | |
60 | * Return the MII PHY address associated with the given IPD | |
61 | * port. A result of -1 means there isn't a MII capable PHY | |
62 | * connected to this port. On chips supporting multiple MII | |
63 | * busses the bus number is encoded in bits <15:8>. | |
64 | * | |
65 | * This function must be modified for every new Octeon board. | |
66 | * Internally it uses switch statements based on the cvmx_sysinfo | |
67 | * data to determine board types and revisions. It replies on the | |
68 | * fact that every Octeon board receives a unique board type | |
69 | * enumeration from the bootloader. | |
70 | * | |
71 | * @ipd_port: Octeon IPD port to get the MII address for. | |
72 | * | |
73 | * Returns MII PHY address and bus number or -1. | |
74 | */ | |
75 | int cvmx_helper_board_get_mii_address(int ipd_port) | |
76 | { | |
77 | switch (cvmx_sysinfo_get()->board_type) { | |
78 | case CVMX_BOARD_TYPE_SIM: | |
79 | /* Simulator doesn't have MII */ | |
80 | return -1; | |
81 | case CVMX_BOARD_TYPE_EBT3000: | |
82 | case CVMX_BOARD_TYPE_EBT5800: | |
83 | case CVMX_BOARD_TYPE_THUNDER: | |
84 | case CVMX_BOARD_TYPE_NICPRO2: | |
85 | /* Interface 0 is SPI4, interface 1 is RGMII */ | |
86 | if ((ipd_port >= 16) && (ipd_port < 20)) | |
87 | return ipd_port - 16; | |
88 | else | |
89 | return -1; | |
90 | case CVMX_BOARD_TYPE_KODAMA: | |
91 | case CVMX_BOARD_TYPE_EBH3100: | |
92 | case CVMX_BOARD_TYPE_HIKARI: | |
93 | case CVMX_BOARD_TYPE_CN3010_EVB_HS5: | |
94 | case CVMX_BOARD_TYPE_CN3005_EVB_HS5: | |
95 | case CVMX_BOARD_TYPE_CN3020_EVB_HS5: | |
96 | /* | |
97 | * Port 0 is WAN connected to a PHY, Port 1 is GMII | |
98 | * connected to a switch | |
99 | */ | |
100 | if (ipd_port == 0) | |
101 | return 4; | |
102 | else if (ipd_port == 1) | |
103 | return 9; | |
104 | else | |
105 | return -1; | |
106 | case CVMX_BOARD_TYPE_NAC38: | |
107 | /* Board has 8 RGMII ports PHYs are 0-7 */ | |
108 | if ((ipd_port >= 0) && (ipd_port < 4)) | |
109 | return ipd_port; | |
110 | else if ((ipd_port >= 16) && (ipd_port < 20)) | |
111 | return ipd_port - 16 + 4; | |
112 | else | |
113 | return -1; | |
114 | case CVMX_BOARD_TYPE_EBH3000: | |
115 | /* Board has dual SPI4 and no PHYs */ | |
116 | return -1; | |
117 | case CVMX_BOARD_TYPE_EBH5200: | |
118 | case CVMX_BOARD_TYPE_EBH5201: | |
119 | case CVMX_BOARD_TYPE_EBT5200: | |
ada11a33 DD |
120 | /* Board has 2 management ports */ |
121 | if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) && | |
122 | (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2))) | |
123 | return ipd_port - CVMX_HELPER_BOARD_MGMT_IPD_PORT; | |
80ff0fd3 DD |
124 | /* |
125 | * Board has 4 SGMII ports. The PHYs start right after the MII | |
126 | * ports MII0 = 0, MII1 = 1, SGMII = 2-5. | |
127 | */ | |
128 | if ((ipd_port >= 0) && (ipd_port < 4)) | |
129 | return ipd_port + 2; | |
130 | else | |
131 | return -1; | |
132 | case CVMX_BOARD_TYPE_EBH5600: | |
133 | case CVMX_BOARD_TYPE_EBH5601: | |
134 | case CVMX_BOARD_TYPE_EBH5610: | |
ada11a33 DD |
135 | /* Board has 1 management port */ |
136 | if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT) | |
137 | return 0; | |
80ff0fd3 DD |
138 | /* |
139 | * Board has 8 SGMII ports. 4 connect out, two connect | |
140 | * to a switch, and 2 loop to each other | |
141 | */ | |
142 | if ((ipd_port >= 0) && (ipd_port < 4)) | |
143 | return ipd_port + 1; | |
144 | else | |
145 | return -1; | |
146 | case CVMX_BOARD_TYPE_CUST_NB5: | |
147 | if (ipd_port == 2) | |
148 | return 4; | |
149 | else | |
150 | return -1; | |
151 | case CVMX_BOARD_TYPE_NIC_XLE_4G: | |
152 | /* Board has 4 SGMII ports. connected QLM3(interface 1) */ | |
153 | if ((ipd_port >= 16) && (ipd_port < 20)) | |
154 | return ipd_port - 16 + 1; | |
155 | else | |
156 | return -1; | |
ada11a33 DD |
157 | case CVMX_BOARD_TYPE_NIC_XLE_10G: |
158 | case CVMX_BOARD_TYPE_NIC10E: | |
159 | return -1; | |
160 | case CVMX_BOARD_TYPE_NIC4E: | |
161 | if (ipd_port >= 0 && ipd_port <= 3) | |
162 | return (ipd_port + 0x1f) & 0x1f; | |
163 | else | |
164 | return -1; | |
165 | case CVMX_BOARD_TYPE_NIC2E: | |
166 | if (ipd_port >= 0 && ipd_port <= 1) | |
167 | return ipd_port + 1; | |
168 | else | |
169 | return -1; | |
80ff0fd3 DD |
170 | case CVMX_BOARD_TYPE_BBGW_REF: |
171 | /* | |
172 | * No PHYs are connected to Octeon, everything is | |
173 | * through switch. | |
174 | */ | |
175 | return -1; | |
9dd14746 DD |
176 | |
177 | case CVMX_BOARD_TYPE_CUST_WSX16: | |
178 | if (ipd_port >= 0 && ipd_port <= 3) | |
179 | return ipd_port; | |
180 | else if (ipd_port >= 16 && ipd_port <= 19) | |
181 | return ipd_port - 16 + 4; | |
182 | else | |
183 | return -1; | |
a135a9b5 AK |
184 | case CVMX_BOARD_TYPE_UBNT_E100: |
185 | if (ipd_port >= 0 && ipd_port <= 2) | |
186 | return 7 - ipd_port; | |
187 | else | |
188 | return -1; | |
cef232ec AK |
189 | case CVMX_BOARD_TYPE_KONTRON_S1901: |
190 | if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT) | |
191 | return 1; | |
192 | else | |
193 | return -1; | |
194 | ||
80ff0fd3 DD |
195 | } |
196 | ||
197 | /* Some unknown board. Somebody forgot to update this function... */ | |
198 | cvmx_dprintf | |
199 | ("cvmx_helper_board_get_mii_address: Unknown board type %d\n", | |
200 | cvmx_sysinfo_get()->board_type); | |
201 | return -1; | |
202 | } | |
203 | ||
204 | /** | |
205 | * This function is the board specific method of determining an | |
206 | * ethernet ports link speed. Most Octeon boards have Marvell PHYs | |
207 | * and are handled by the fall through case. This function must be | |
208 | * updated for boards that don't have the normal Marvell PHYs. | |
209 | * | |
210 | * This function must be modified for every new Octeon board. | |
211 | * Internally it uses switch statements based on the cvmx_sysinfo | |
212 | * data to determine board types and revisions. It relies on the | |
213 | * fact that every Octeon board receives a unique board type | |
214 | * enumeration from the bootloader. | |
215 | * | |
216 | * @ipd_port: IPD input port associated with the port we want to get link | |
70342287 | 217 | * status for. |
80ff0fd3 DD |
218 | * |
219 | * Returns The ports link status. If the link isn't fully resolved, this must | |
70342287 | 220 | * return zero. |
80ff0fd3 DD |
221 | */ |
222 | cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port) | |
223 | { | |
224 | cvmx_helper_link_info_t result; | |
225 | int phy_addr; | |
226 | int is_broadcom_phy = 0; | |
227 | ||
228 | /* Give the user a chance to override the processing of this function */ | |
229 | if (cvmx_override_board_link_get) | |
230 | return cvmx_override_board_link_get(ipd_port); | |
231 | ||
232 | /* Unless we fix it later, all links are defaulted to down */ | |
233 | result.u64 = 0; | |
234 | ||
235 | /* | |
236 | * This switch statement should handle all ports that either don't use | |
237 | * Marvell PHYS, or don't support in-band status. | |
238 | */ | |
239 | switch (cvmx_sysinfo_get()->board_type) { | |
240 | case CVMX_BOARD_TYPE_SIM: | |
241 | /* The simulator gives you a simulated 1Gbps full duplex link */ | |
242 | result.s.link_up = 1; | |
243 | result.s.full_duplex = 1; | |
244 | result.s.speed = 1000; | |
245 | return result; | |
246 | case CVMX_BOARD_TYPE_EBH3100: | |
247 | case CVMX_BOARD_TYPE_CN3010_EVB_HS5: | |
248 | case CVMX_BOARD_TYPE_CN3005_EVB_HS5: | |
249 | case CVMX_BOARD_TYPE_CN3020_EVB_HS5: | |
250 | /* Port 1 on these boards is always Gigabit */ | |
251 | if (ipd_port == 1) { | |
252 | result.s.link_up = 1; | |
253 | result.s.full_duplex = 1; | |
254 | result.s.speed = 1000; | |
255 | return result; | |
256 | } | |
257 | /* Fall through to the generic code below */ | |
258 | break; | |
259 | case CVMX_BOARD_TYPE_CUST_NB5: | |
260 | /* Port 1 on these boards is always Gigabit */ | |
261 | if (ipd_port == 1) { | |
262 | result.s.link_up = 1; | |
263 | result.s.full_duplex = 1; | |
264 | result.s.speed = 1000; | |
265 | return result; | |
266 | } else /* The other port uses a broadcom PHY */ | |
267 | is_broadcom_phy = 1; | |
268 | break; | |
269 | case CVMX_BOARD_TYPE_BBGW_REF: | |
270 | /* Port 1 on these boards is always Gigabit */ | |
271 | if (ipd_port == 2) { | |
272 | /* Port 2 is not hooked up */ | |
273 | result.u64 = 0; | |
274 | return result; | |
275 | } else { | |
276 | /* Ports 0 and 1 connect to the switch */ | |
277 | result.s.link_up = 1; | |
278 | result.s.full_duplex = 1; | |
279 | result.s.speed = 1000; | |
280 | return result; | |
281 | } | |
282 | break; | |
283 | } | |
284 | ||
285 | phy_addr = cvmx_helper_board_get_mii_address(ipd_port); | |
286 | if (phy_addr != -1) { | |
287 | if (is_broadcom_phy) { | |
288 | /* | |
289 | * Below we are going to read SMI/MDIO | |
290 | * register 0x19 which works on Broadcom | |
291 | * parts | |
292 | */ | |
293 | int phy_status = | |
294 | cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, | |
295 | 0x19); | |
296 | switch ((phy_status >> 8) & 0x7) { | |
297 | case 0: | |
298 | result.u64 = 0; | |
299 | break; | |
300 | case 1: | |
301 | result.s.link_up = 1; | |
302 | result.s.full_duplex = 0; | |
303 | result.s.speed = 10; | |
304 | break; | |
305 | case 2: | |
306 | result.s.link_up = 1; | |
307 | result.s.full_duplex = 1; | |
308 | result.s.speed = 10; | |
309 | break; | |
310 | case 3: | |
311 | result.s.link_up = 1; | |
312 | result.s.full_duplex = 0; | |
313 | result.s.speed = 100; | |
314 | break; | |
315 | case 4: | |
316 | result.s.link_up = 1; | |
317 | result.s.full_duplex = 1; | |
318 | result.s.speed = 100; | |
319 | break; | |
320 | case 5: | |
321 | result.s.link_up = 1; | |
322 | result.s.full_duplex = 1; | |
323 | result.s.speed = 100; | |
324 | break; | |
325 | case 6: | |
326 | result.s.link_up = 1; | |
327 | result.s.full_duplex = 0; | |
328 | result.s.speed = 1000; | |
329 | break; | |
330 | case 7: | |
331 | result.s.link_up = 1; | |
332 | result.s.full_duplex = 1; | |
333 | result.s.speed = 1000; | |
334 | break; | |
335 | } | |
336 | } else { | |
337 | /* | |
338 | * This code assumes we are using a Marvell | |
339 | * Gigabit PHY. All the speed information can | |
340 | * be read from register 17 in one | |
341 | * go. Somebody using a different PHY will | |
342 | * need to handle it above in the board | |
343 | * specific area. | |
344 | */ | |
345 | int phy_status = | |
346 | cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 17); | |
347 | ||
348 | /* | |
349 | * If the resolve bit 11 isn't set, see if | |
350 | * autoneg is turned off (bit 12, reg 0). The | |
351 | * resolve bit doesn't get set properly when | |
352 | * autoneg is off, so force it. | |
353 | */ | |
354 | if ((phy_status & (1 << 11)) == 0) { | |
355 | int auto_status = | |
356 | cvmx_mdio_read(phy_addr >> 8, | |
357 | phy_addr & 0xff, 0); | |
358 | if ((auto_status & (1 << 12)) == 0) | |
359 | phy_status |= 1 << 11; | |
360 | } | |
361 | ||
362 | /* | |
363 | * Only return a link if the PHY has finished | |
364 | * auto negotiation and set the resolved bit | |
365 | * (bit 11) | |
366 | */ | |
367 | if (phy_status & (1 << 11)) { | |
368 | result.s.link_up = 1; | |
369 | result.s.full_duplex = ((phy_status >> 13) & 1); | |
370 | switch ((phy_status >> 14) & 3) { | |
70342287 | 371 | case 0: /* 10 Mbps */ |
80ff0fd3 DD |
372 | result.s.speed = 10; |
373 | break; | |
70342287 | 374 | case 1: /* 100 Mbps */ |
80ff0fd3 DD |
375 | result.s.speed = 100; |
376 | break; | |
70342287 | 377 | case 2: /* 1 Gbps */ |
80ff0fd3 DD |
378 | result.s.speed = 1000; |
379 | break; | |
70342287 | 380 | case 3: /* Illegal */ |
80ff0fd3 DD |
381 | result.u64 = 0; |
382 | break; | |
383 | } | |
384 | } | |
385 | } | |
386 | } else if (OCTEON_IS_MODEL(OCTEON_CN3XXX) | |
387 | || OCTEON_IS_MODEL(OCTEON_CN58XX) | |
388 | || OCTEON_IS_MODEL(OCTEON_CN50XX)) { | |
389 | /* | |
390 | * We don't have a PHY address, so attempt to use | |
391 | * in-band status. It is really important that boards | |
392 | * not supporting in-band status never get | |
393 | * here. Reading broken in-band status tends to do bad | |
394 | * things | |
395 | */ | |
396 | union cvmx_gmxx_rxx_rx_inbnd inband_status; | |
397 | int interface = cvmx_helper_get_interface_num(ipd_port); | |
398 | int index = cvmx_helper_get_interface_index_num(ipd_port); | |
399 | inband_status.u64 = | |
400 | cvmx_read_csr(CVMX_GMXX_RXX_RX_INBND(index, interface)); | |
401 | ||
402 | result.s.link_up = inband_status.s.status; | |
403 | result.s.full_duplex = inband_status.s.duplex; | |
404 | switch (inband_status.s.speed) { | |
70342287 | 405 | case 0: /* 10 Mbps */ |
80ff0fd3 DD |
406 | result.s.speed = 10; |
407 | break; | |
70342287 | 408 | case 1: /* 100 Mbps */ |
80ff0fd3 DD |
409 | result.s.speed = 100; |
410 | break; | |
70342287 | 411 | case 2: /* 1 Gbps */ |
80ff0fd3 DD |
412 | result.s.speed = 1000; |
413 | break; | |
70342287 | 414 | case 3: /* Illegal */ |
80ff0fd3 DD |
415 | result.u64 = 0; |
416 | break; | |
417 | } | |
418 | } else { | |
419 | /* | |
420 | * We don't have a PHY address and we don't have | |
421 | * in-band status. There is no way to determine the | |
422 | * link speed. Return down assuming this port isn't | |
423 | * wired | |
424 | */ | |
425 | result.u64 = 0; | |
426 | } | |
427 | ||
428 | /* If link is down, return all fields as zero. */ | |
429 | if (!result.s.link_up) | |
430 | result.u64 = 0; | |
431 | ||
432 | return result; | |
433 | } | |
434 | ||
435 | /** | |
436 | * This function as a board specific method of changing the PHY | |
437 | * speed, duplex, and auto-negotiation. This programs the PHY and | |
438 | * not Octeon. This can be used to force Octeon's links to | |
439 | * specific settings. | |
440 | * | |
441 | * @phy_addr: The address of the PHY to program | |
442 | * @enable_autoneg: | |
70342287 | 443 | * Non zero if you want to enable auto-negotiation. |
80ff0fd3 | 444 | * @link_info: Link speed to program. If the speed is zero and auto-negotiation |
70342287 | 445 | * is enabled, all possible negotiation speeds are advertised. |
80ff0fd3 DD |
446 | * |
447 | * Returns Zero on success, negative on failure | |
448 | */ | |
449 | int cvmx_helper_board_link_set_phy(int phy_addr, | |
450 | cvmx_helper_board_set_phy_link_flags_types_t | |
451 | link_flags, | |
452 | cvmx_helper_link_info_t link_info) | |
453 | { | |
454 | ||
455 | /* Set the flow control settings based on link_flags */ | |
456 | if ((link_flags & set_phy_link_flags_flow_control_mask) != | |
457 | set_phy_link_flags_flow_control_dont_touch) { | |
458 | cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver; | |
459 | reg_autoneg_adver.u16 = | |
460 | cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, | |
461 | CVMX_MDIO_PHY_REG_AUTONEG_ADVER); | |
462 | reg_autoneg_adver.s.asymmetric_pause = | |
463 | (link_flags & set_phy_link_flags_flow_control_mask) == | |
464 | set_phy_link_flags_flow_control_enable; | |
465 | reg_autoneg_adver.s.pause = | |
466 | (link_flags & set_phy_link_flags_flow_control_mask) == | |
467 | set_phy_link_flags_flow_control_enable; | |
468 | cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, | |
469 | CVMX_MDIO_PHY_REG_AUTONEG_ADVER, | |
470 | reg_autoneg_adver.u16); | |
471 | } | |
472 | ||
473 | /* If speed isn't set and autoneg is on advertise all supported modes */ | |
474 | if ((link_flags & set_phy_link_flags_autoneg) | |
475 | && (link_info.s.speed == 0)) { | |
476 | cvmx_mdio_phy_reg_control_t reg_control; | |
477 | cvmx_mdio_phy_reg_status_t reg_status; | |
478 | cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver; | |
479 | cvmx_mdio_phy_reg_extended_status_t reg_extended_status; | |
480 | cvmx_mdio_phy_reg_control_1000_t reg_control_1000; | |
481 | ||
482 | reg_status.u16 = | |
483 | cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, | |
484 | CVMX_MDIO_PHY_REG_STATUS); | |
485 | reg_autoneg_adver.u16 = | |
486 | cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, | |
487 | CVMX_MDIO_PHY_REG_AUTONEG_ADVER); | |
488 | reg_autoneg_adver.s.advert_100base_t4 = | |
489 | reg_status.s.capable_100base_t4; | |
490 | reg_autoneg_adver.s.advert_10base_tx_full = | |
491 | reg_status.s.capable_10_full; | |
492 | reg_autoneg_adver.s.advert_10base_tx_half = | |
493 | reg_status.s.capable_10_half; | |
494 | reg_autoneg_adver.s.advert_100base_tx_full = | |
495 | reg_status.s.capable_100base_x_full; | |
496 | reg_autoneg_adver.s.advert_100base_tx_half = | |
497 | reg_status.s.capable_100base_x_half; | |
498 | cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, | |
499 | CVMX_MDIO_PHY_REG_AUTONEG_ADVER, | |
500 | reg_autoneg_adver.u16); | |
501 | if (reg_status.s.capable_extended_status) { | |
502 | reg_extended_status.u16 = | |
503 | cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, | |
504 | CVMX_MDIO_PHY_REG_EXTENDED_STATUS); | |
505 | reg_control_1000.u16 = | |
506 | cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, | |
507 | CVMX_MDIO_PHY_REG_CONTROL_1000); | |
508 | reg_control_1000.s.advert_1000base_t_full = | |
509 | reg_extended_status.s.capable_1000base_t_full; | |
510 | reg_control_1000.s.advert_1000base_t_half = | |
511 | reg_extended_status.s.capable_1000base_t_half; | |
512 | cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, | |
513 | CVMX_MDIO_PHY_REG_CONTROL_1000, | |
514 | reg_control_1000.u16); | |
515 | } | |
516 | reg_control.u16 = | |
517 | cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, | |
518 | CVMX_MDIO_PHY_REG_CONTROL); | |
519 | reg_control.s.autoneg_enable = 1; | |
520 | reg_control.s.restart_autoneg = 1; | |
521 | cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, | |
522 | CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16); | |
523 | } else if ((link_flags & set_phy_link_flags_autoneg)) { | |
524 | cvmx_mdio_phy_reg_control_t reg_control; | |
525 | cvmx_mdio_phy_reg_status_t reg_status; | |
526 | cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver; | |
80ff0fd3 DD |
527 | cvmx_mdio_phy_reg_control_1000_t reg_control_1000; |
528 | ||
529 | reg_status.u16 = | |
530 | cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, | |
531 | CVMX_MDIO_PHY_REG_STATUS); | |
532 | reg_autoneg_adver.u16 = | |
533 | cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, | |
534 | CVMX_MDIO_PHY_REG_AUTONEG_ADVER); | |
535 | reg_autoneg_adver.s.advert_100base_t4 = 0; | |
536 | reg_autoneg_adver.s.advert_10base_tx_full = 0; | |
537 | reg_autoneg_adver.s.advert_10base_tx_half = 0; | |
538 | reg_autoneg_adver.s.advert_100base_tx_full = 0; | |
539 | reg_autoneg_adver.s.advert_100base_tx_half = 0; | |
540 | if (reg_status.s.capable_extended_status) { | |
80ff0fd3 DD |
541 | reg_control_1000.u16 = |
542 | cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, | |
543 | CVMX_MDIO_PHY_REG_CONTROL_1000); | |
544 | reg_control_1000.s.advert_1000base_t_full = 0; | |
545 | reg_control_1000.s.advert_1000base_t_half = 0; | |
546 | } | |
547 | switch (link_info.s.speed) { | |
548 | case 10: | |
549 | reg_autoneg_adver.s.advert_10base_tx_full = | |
550 | link_info.s.full_duplex; | |
551 | reg_autoneg_adver.s.advert_10base_tx_half = | |
552 | !link_info.s.full_duplex; | |
553 | break; | |
554 | case 100: | |
555 | reg_autoneg_adver.s.advert_100base_tx_full = | |
556 | link_info.s.full_duplex; | |
557 | reg_autoneg_adver.s.advert_100base_tx_half = | |
558 | !link_info.s.full_duplex; | |
559 | break; | |
560 | case 1000: | |
561 | reg_control_1000.s.advert_1000base_t_full = | |
562 | link_info.s.full_duplex; | |
563 | reg_control_1000.s.advert_1000base_t_half = | |
564 | !link_info.s.full_duplex; | |
565 | break; | |
566 | } | |
567 | cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, | |
568 | CVMX_MDIO_PHY_REG_AUTONEG_ADVER, | |
569 | reg_autoneg_adver.u16); | |
570 | if (reg_status.s.capable_extended_status) | |
571 | cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, | |
572 | CVMX_MDIO_PHY_REG_CONTROL_1000, | |
573 | reg_control_1000.u16); | |
574 | reg_control.u16 = | |
575 | cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, | |
576 | CVMX_MDIO_PHY_REG_CONTROL); | |
577 | reg_control.s.autoneg_enable = 1; | |
578 | reg_control.s.restart_autoneg = 1; | |
579 | cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, | |
580 | CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16); | |
581 | } else { | |
582 | cvmx_mdio_phy_reg_control_t reg_control; | |
583 | reg_control.u16 = | |
584 | cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, | |
585 | CVMX_MDIO_PHY_REG_CONTROL); | |
586 | reg_control.s.autoneg_enable = 0; | |
587 | reg_control.s.restart_autoneg = 1; | |
588 | reg_control.s.duplex = link_info.s.full_duplex; | |
589 | if (link_info.s.speed == 1000) { | |
590 | reg_control.s.speed_msb = 1; | |
591 | reg_control.s.speed_lsb = 0; | |
592 | } else if (link_info.s.speed == 100) { | |
593 | reg_control.s.speed_msb = 0; | |
594 | reg_control.s.speed_lsb = 1; | |
595 | } else if (link_info.s.speed == 10) { | |
596 | reg_control.s.speed_msb = 0; | |
597 | reg_control.s.speed_lsb = 0; | |
598 | } | |
599 | cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, | |
600 | CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16); | |
601 | } | |
602 | return 0; | |
603 | } | |
604 | ||
605 | /** | |
606 | * This function is called by cvmx_helper_interface_probe() after it | |
607 | * determines the number of ports Octeon can support on a specific | |
608 | * interface. This function is the per board location to override | |
609 | * this value. It is called with the number of ports Octeon might | |
610 | * support and should return the number of actual ports on the | |
611 | * board. | |
612 | * | |
613 | * This function must be modifed for every new Octeon board. | |
614 | * Internally it uses switch statements based on the cvmx_sysinfo | |
615 | * data to determine board types and revisions. It relys on the | |
616 | * fact that every Octeon board receives a unique board type | |
617 | * enumeration from the bootloader. | |
618 | * | |
619 | * @interface: Interface to probe | |
620 | * @supported_ports: | |
70342287 | 621 | * Number of ports Octeon supports. |
80ff0fd3 DD |
622 | * |
623 | * Returns Number of ports the actual board supports. Many times this will | |
70342287 | 624 | * simple be "support_ports". |
80ff0fd3 DD |
625 | */ |
626 | int __cvmx_helper_board_interface_probe(int interface, int supported_ports) | |
627 | { | |
628 | switch (cvmx_sysinfo_get()->board_type) { | |
629 | case CVMX_BOARD_TYPE_CN3005_EVB_HS5: | |
630 | if (interface == 0) | |
631 | return 2; | |
632 | break; | |
633 | case CVMX_BOARD_TYPE_BBGW_REF: | |
634 | if (interface == 0) | |
635 | return 2; | |
636 | break; | |
637 | case CVMX_BOARD_TYPE_NIC_XLE_4G: | |
638 | if (interface == 0) | |
639 | return 0; | |
640 | break; | |
641 | /* The 2nd interface on the EBH5600 is connected to the Marvel switch, | |
642 | which we don't support. Disable ports connected to it */ | |
643 | case CVMX_BOARD_TYPE_EBH5600: | |
644 | if (interface == 1) | |
645 | return 0; | |
646 | break; | |
647 | } | |
648 | return supported_ports; | |
649 | } | |
650 | ||
651 | /** | |
652 | * Enable packet input/output from the hardware. This function is | |
653 | * called after by cvmx_helper_packet_hardware_enable() to | |
654 | * perform board specific initialization. For most boards | |
655 | * nothing is needed. | |
656 | * | |
657 | * @interface: Interface to enable | |
658 | * | |
659 | * Returns Zero on success, negative on failure | |
660 | */ | |
661 | int __cvmx_helper_board_hardware_enable(int interface) | |
662 | { | |
663 | if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3005_EVB_HS5) { | |
664 | if (interface == 0) { | |
665 | /* Different config for switch port */ | |
666 | cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(1, interface), 0); | |
667 | cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(1, interface), 0); | |
668 | /* | |
669 | * Boards with gigabit WAN ports need a | |
670 | * different setting that is compatible with | |
671 | * 100 Mbit settings | |
672 | */ | |
673 | cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface), | |
674 | 0xc); | |
675 | cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), | |
676 | 0xc); | |
677 | } | |
678 | } else if (cvmx_sysinfo_get()->board_type == | |
679 | CVMX_BOARD_TYPE_CN3010_EVB_HS5) { | |
680 | /* | |
681 | * Broadcom PHYs require differnet ASX | |
682 | * clocks. Unfortunately many boards don't define a | |
683 | * new board Id and simply mangle the | |
684 | * CN3010_EVB_HS5 | |
685 | */ | |
686 | if (interface == 0) { | |
687 | /* | |
688 | * Some boards use a hacked up bootloader that | |
689 | * identifies them as CN3010_EVB_HS5 | |
690 | * evaluation boards. This leads to all kinds | |
691 | * of configuration problems. Detect one | |
692 | * case, and print warning, while trying to do | |
693 | * the right thing. | |
694 | */ | |
695 | int phy_addr = cvmx_helper_board_get_mii_address(0); | |
696 | if (phy_addr != -1) { | |
697 | int phy_identifier = | |
698 | cvmx_mdio_read(phy_addr >> 8, | |
699 | phy_addr & 0xff, 0x2); | |
700 | /* Is it a Broadcom PHY? */ | |
701 | if (phy_identifier == 0x0143) { | |
702 | cvmx_dprintf("\n"); | |
703 | cvmx_dprintf("ERROR:\n"); | |
704 | cvmx_dprintf | |
705 | ("ERROR: Board type is CVMX_BOARD_TYPE_CN3010_EVB_HS5, but Broadcom PHY found.\n"); | |
706 | cvmx_dprintf | |
707 | ("ERROR: The board type is mis-configured, and software malfunctions are likely.\n"); | |
708 | cvmx_dprintf | |
709 | ("ERROR: All boards require a unique board type to identify them.\n"); | |
710 | cvmx_dprintf("ERROR:\n"); | |
711 | cvmx_dprintf("\n"); | |
712 | cvmx_wait(1000000000); | |
713 | cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX | |
714 | (0, interface), 5); | |
715 | cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX | |
716 | (0, interface), 5); | |
717 | } | |
718 | } | |
719 | } | |
a135a9b5 AK |
720 | } else if (cvmx_sysinfo_get()->board_type == |
721 | CVMX_BOARD_TYPE_UBNT_E100) { | |
722 | cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), 0); | |
723 | cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface), 0x10); | |
724 | cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(1, interface), 0); | |
725 | cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(1, interface), 0x10); | |
726 | cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(2, interface), 0); | |
727 | cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(2, interface), 0x10); | |
80ff0fd3 DD |
728 | } |
729 | return 0; | |
730 | } | |
d617f9e9 DD |
731 | |
732 | /** | |
733 | * Get the clock type used for the USB block based on board type. | |
734 | * Used by the USB code for auto configuration of clock type. | |
735 | * | |
736 | * Return USB clock type enumeration | |
737 | */ | |
738 | enum cvmx_helper_board_usb_clock_types __cvmx_helper_board_usb_get_clock_type(void) | |
739 | { | |
740 | switch (cvmx_sysinfo_get()->board_type) { | |
741 | case CVMX_BOARD_TYPE_BBGW_REF: | |
742 | case CVMX_BOARD_TYPE_LANAI2_A: | |
743 | case CVMX_BOARD_TYPE_LANAI2_U: | |
744 | case CVMX_BOARD_TYPE_LANAI2_G: | |
745 | case CVMX_BOARD_TYPE_NIC10E_66: | |
746 | case CVMX_BOARD_TYPE_UBNT_E100: | |
747 | return USB_CLOCK_TYPE_CRYSTAL_12; | |
748 | case CVMX_BOARD_TYPE_NIC10E: | |
749 | return USB_CLOCK_TYPE_REF_12; | |
750 | default: | |
751 | break; | |
752 | } | |
753 | /* Most boards except NIC10e use a 12MHz crystal */ | |
debe6a62 | 754 | if (OCTEON_IS_OCTEON2()) |
d617f9e9 DD |
755 | return USB_CLOCK_TYPE_CRYSTAL_12; |
756 | return USB_CLOCK_TYPE_REF_48; | |
757 | } |