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MIPS: Octeon: device_tree_init: use separate pass to fill mac addresses
[mirror_ubuntu-hirsute-kernel.git] / arch / mips / cavium-octeon / octeon-platform.c
CommitLineData
512254ba
DD		 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
7ed18152 6 * Copyright (C) 2004-2011 Cavium Networks
512254ba
DD		 7 * Copyright (C) 2008 Wind River Systems
8 */
9
2193dda5 10#include <linux/delay.h>
512254ba
DD		 11#include <linux/init.h>
12#include <linux/irq.h>
d9577054 13#include <linux/i2c.h>
340fbb8b 14#include <linux/usb.h>
f1299072 15#include <linux/dma-mapping.h>
512254ba 16#include <linux/module.h>
2193dda5 17#include <linux/mutex.h>
7ed18152 18#include <linux/slab.h>
512254ba 19#include <linux/platform_device.h>
7ed18152
DD		 20#include <linux/of_platform.h>
21#include <linux/of_fdt.h>
22#include <linux/libfdt.h>
2193dda5
AS		 23#include <linux/usb/ehci_pdriver.h>
24#include <linux/usb/ohci_pdriver.h>
512254ba
DD		 25
26#include <asm/octeon/octeon.h>
27#include <asm/octeon/cvmx-rnm-defs.h>
7ed18152
DD		 28#include <asm/octeon/cvmx-helper.h>
29#include <asm/octeon/cvmx-helper-board.h>
2193dda5 30#include <asm/octeon/cvmx-uctlx-defs.h>
512254ba 31
512254ba
DD		 32/* Octeon Random Number Generator. */
33static int __init octeon_rng_device_init(void)
34{
35 struct platform_device *pd;
36 int ret = 0;
37
38 struct resource rng_resources[] = {
39 {
40 .flags = IORESOURCE_MEM,
41 .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
42 .end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
43 }, {
44 .flags = IORESOURCE_MEM,
45 .start = cvmx_build_io_address(8, 0),
46 .end = cvmx_build_io_address(8, 0) + 0x7
47 }
48 };
49
50 pd = platform_device_alloc("octeon_rng", -1);
51 if (!pd) {
52 ret = -ENOMEM;
53 goto out;
54 }
55
56 ret = platform_device_add_resources(pd, rng_resources,
57 ARRAY_SIZE(rng_resources));
58 if (ret)
59 goto fail;
60
61 ret = platform_device_add(pd);
62 if (ret)
63 goto fail;
64
65 return ret;
66fail:
67 platform_device_put(pd);
68
69out:
70 return ret;
71}
72device_initcall(octeon_rng_device_init);
73
340fbb8b
DD		 74#ifdef CONFIG_USB
75
2193dda5
AS		 76static DEFINE_MUTEX(octeon2_usb_clocks_mutex);
77
78static int octeon2_usb_clock_start_cnt;
79
a95cfa6b 80static void octeon2_usb_clocks_start(struct device *dev)
2193dda5
AS		 81{
82 u64 div;
83 union cvmx_uctlx_if_ena if_ena;
84 union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
85 union cvmx_uctlx_uphy_ctl_status uphy_ctl_status;
86 union cvmx_uctlx_uphy_portx_ctl_status port_ctl_status;
87 int i;
88 unsigned long io_clk_64_to_ns;
a95cfa6b
AH		 89 u32 clock_rate = 12000000;
90 bool is_crystal_clock = false;
2193dda5
AS		 91
92
93 mutex_lock(&octeon2_usb_clocks_mutex);
94
95 octeon2_usb_clock_start_cnt++;
96 if (octeon2_usb_clock_start_cnt != 1)
97 goto exit;
98
99 io_clk_64_to_ns = 64000000000ull / octeon_get_io_clock_rate();
100
a95cfa6b
AH		 101 if (dev->of_node) {
102 struct device_node *uctl_node;
103 const char *clock_type;
104
105 uctl_node = of_get_parent(dev->of_node);
106 if (!uctl_node) {
107 dev_err(dev, "No UCTL device node\n");
108 goto exit;
109 }
110 i = of_property_read_u32(uctl_node,
111 "refclk-frequency", &clock_rate);
112 if (i) {
113 dev_err(dev, "No UCTL \"refclk-frequency\"\n");
114 goto exit;
115 }
116 i = of_property_read_string(uctl_node,
117 "refclk-type", &clock_type);
118
119 if (!i && strcmp("crystal", clock_type) == 0)
120 is_crystal_clock = true;
121 }
122
2193dda5
AS		 123 /*
124 * Step 1: Wait for voltages stable. That surely happened
125 * before starting the kernel.
126 *
127 * Step 2: Enable SCLK of UCTL by writing UCTL0_IF_ENA[EN] = 1
128 */
129 if_ena.u64 = 0;
130 if_ena.s.en = 1;
131 cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64);
132
133 /* Step 3: Configure the reference clock, PHY, and HCLK */
134 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
135
136 /*
137 * If the UCTL looks like it has already been started, skip
138 * the initialization, otherwise bus errors are obtained.
139 */
140 if (clk_rst_ctl.s.hrst)
141 goto end_clock;
142 /* 3a */
143 clk_rst_ctl.s.p_por = 1;
144 clk_rst_ctl.s.hrst = 0;
145 clk_rst_ctl.s.p_prst = 0;
146 clk_rst_ctl.s.h_clkdiv_rst = 0;
147 clk_rst_ctl.s.o_clkdiv_rst = 0;
148 clk_rst_ctl.s.h_clkdiv_en = 0;
149 clk_rst_ctl.s.o_clkdiv_en = 0;
150 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
151
152 /* 3b */
a95cfa6b
AH		 153 clk_rst_ctl.s.p_refclk_sel = is_crystal_clock ? 0 : 1;
154 switch (clock_rate) {
155 default:
156 pr_err("Invalid UCTL clock rate of %u, using 12000000 instead\n",
157 clock_rate);
158 /* Fall through */
159 case 12000000:
160 clk_rst_ctl.s.p_refclk_div = 0;
161 break;
162 case 24000000:
163 clk_rst_ctl.s.p_refclk_div = 1;
164 break;
165 case 48000000:
166 clk_rst_ctl.s.p_refclk_div = 2;
167 break;
168 }
2193dda5
AS		 169 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
170
171 /* 3c */
172 div = octeon_get_io_clock_rate() / 130000000ull;
173
174 switch (div) {
175 case 0:
176 div = 1;
177 break;
178 case 1:
179 case 2:
180 case 3:
181 case 4:
182 break;
183 case 5:
184 div = 4;
185 break;
186 case 6:
187 case 7:
188 div = 6;
189 break;
190 case 8:
191 case 9:
192 case 10:
193 case 11:
194 div = 8;
195 break;
196 default:
197 div = 12;
198 break;
199 }
200 clk_rst_ctl.s.h_div = div;
201 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
202 /* Read it back, */
203 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
204 clk_rst_ctl.s.h_clkdiv_en = 1;
205 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
206 /* 3d */
207 clk_rst_ctl.s.h_clkdiv_rst = 1;
208 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
209
210 /* 3e: delay 64 io clocks */
211 ndelay(io_clk_64_to_ns);
212
213 /*
214 * Step 4: Program the power-on reset field in the UCTL
215 * clock-reset-control register.
216 */
217 clk_rst_ctl.s.p_por = 0;
218 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
219
220 /* Step 5: Wait 1 ms for the PHY clock to start. */
221 mdelay(1);
222
223 /*
224 * Step 6: Program the reset input from automatic test
225 * equipment field in the UPHY CSR
226 */
227 uphy_ctl_status.u64 = cvmx_read_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0));
228 uphy_ctl_status.s.ate_reset = 1;
229 cvmx_write_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0), uphy_ctl_status.u64);
230
231 /* Step 7: Wait for at least 10ns. */
232 ndelay(10);
233
234 /* Step 8: Clear the ATE_RESET field in the UPHY CSR. */
235 uphy_ctl_status.s.ate_reset = 0;
236 cvmx_write_csr(CVMX_UCTLX_UPHY_CTL_STATUS(0), uphy_ctl_status.u64);
237
238 /*
239 * Step 9: Wait for at least 20ns for UPHY to output PHY clock
240 * signals and OHCI_CLK48
241 */
242 ndelay(20);
243
244 /* Step 10: Configure the OHCI_CLK48 and OHCI_CLK12 clocks. */
245 /* 10a */
246 clk_rst_ctl.s.o_clkdiv_rst = 1;
247 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
248
249 /* 10b */
250 clk_rst_ctl.s.o_clkdiv_en = 1;
251 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
252
253 /* 10c */
254 ndelay(io_clk_64_to_ns);
255
256 /*
257 * Step 11: Program the PHY reset field:
258 * UCTL0_CLK_RST_CTL[P_PRST] = 1
259 */
260 clk_rst_ctl.s.p_prst = 1;
261 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
262
263 /* Step 12: Wait 1 uS. */
264 udelay(1);
265
266 /* Step 13: Program the HRESET_N field: UCTL0_CLK_RST_CTL[HRST] = 1 */
267 clk_rst_ctl.s.hrst = 1;
268 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
269
270end_clock:
271 /* Now we can set some other registers. */
272
273 for (i = 0; i <= 1; i++) {
274 port_ctl_status.u64 =
275 cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0));
276 /* Set txvreftune to 15 to obtain compliant 'eye' diagram. */
277 port_ctl_status.s.txvreftune = 15;
278 port_ctl_status.s.txrisetune = 1;
279 port_ctl_status.s.txpreemphasistune = 1;
280 cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0),
281 port_ctl_status.u64);
282 }
283
284 /* Set uSOF cycle period to 60,000 bits. */
285 cvmx_write_csr(CVMX_UCTLX_EHCI_FLA(0), 0x20ull);
286exit:
287 mutex_unlock(&octeon2_usb_clocks_mutex);
288}
289
290static void octeon2_usb_clocks_stop(void)
291{
292 mutex_lock(&octeon2_usb_clocks_mutex);
293 octeon2_usb_clock_start_cnt--;
294 mutex_unlock(&octeon2_usb_clocks_mutex);
295}
296
297static int octeon_ehci_power_on(struct platform_device *pdev)
298{
a95cfa6b 299 octeon2_usb_clocks_start(&pdev->dev);
2193dda5
AS		 300 return 0;
301}
302
303static void octeon_ehci_power_off(struct platform_device *pdev)
304{
305 octeon2_usb_clocks_stop();
306}
307
308static struct usb_ehci_pdata octeon_ehci_pdata = {
309 /* Octeon EHCI matches CPU endianness. */
310#ifdef __BIG_ENDIAN
311 .big_endian_mmio = 1,
312#endif
c99e76c5 313 .dma_mask_64 = 1,
2193dda5
AS		 314 .power_on = octeon_ehci_power_on,
315 .power_off = octeon_ehci_power_off,
316};
317
a95cfa6b 318static void __init octeon_ehci_hw_start(struct device *dev)
2193dda5
AS		 319{
320 union cvmx_uctlx_ehci_ctl ehci_ctl;
321
a95cfa6b 322 octeon2_usb_clocks_start(dev);
2193dda5
AS		 323
324 ehci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_EHCI_CTL(0));
325 /* Use 64-bit addressing. */
326 ehci_ctl.s.ehci_64b_addr_en = 1;
327 ehci_ctl.s.l2c_addr_msb = 0;
b0abf36f 328#ifdef __BIG_ENDIAN
2193dda5
AS		 329 ehci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
330 ehci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
b0abf36f
PM		 331#else
332 ehci_ctl.s.l2c_buff_emod = 0; /* not swapped. */
333 ehci_ctl.s.l2c_desc_emod = 0; /* not swapped. */
334 ehci_ctl.s.inv_reg_a2 = 1;
335#endif
2193dda5
AS		 336 cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64);
337
338 octeon2_usb_clocks_stop();
339}
340
340fbb8b
DD		 341static int __init octeon_ehci_device_init(void)
342{
343 struct platform_device *pd;
a95cfa6b 344 struct device_node *ehci_node;
340fbb8b
DD		 345 int ret = 0;
346
a95cfa6b
AH		 347 ehci_node = of_find_node_by_name(NULL, "ehci");
348 if (!ehci_node)
340fbb8b
DD		 349 return 0;
350
a95cfa6b
AH		 351 pd = of_find_device_by_node(ehci_node);
352 if (!pd)
353 return 0;
340fbb8b 354
2193dda5 355 pd->dev.platform_data = &octeon_ehci_pdata;
a95cfa6b 356 octeon_ehci_hw_start(&pd->dev);
340fbb8b 357
340fbb8b
DD		 358 return ret;
359}
360device_initcall(octeon_ehci_device_init);
361
2193dda5
AS		 362static int octeon_ohci_power_on(struct platform_device *pdev)
363{
a95cfa6b 364 octeon2_usb_clocks_start(&pdev->dev);
2193dda5
AS		 365 return 0;
366}
367
368static void octeon_ohci_power_off(struct platform_device *pdev)
369{
370 octeon2_usb_clocks_stop();
371}
372
373static struct usb_ohci_pdata octeon_ohci_pdata = {
374 /* Octeon OHCI matches CPU endianness. */
375#ifdef __BIG_ENDIAN
376 .big_endian_mmio = 1,
377#endif
378 .power_on = octeon_ohci_power_on,
379 .power_off = octeon_ohci_power_off,
380};
381
a95cfa6b 382static void __init octeon_ohci_hw_start(struct device *dev)
2193dda5
AS		 383{
384 union cvmx_uctlx_ohci_ctl ohci_ctl;
385
a95cfa6b 386 octeon2_usb_clocks_start(dev);
2193dda5
AS		 387
388 ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0));
389 ohci_ctl.s.l2c_addr_msb = 0;
b0abf36f 390#ifdef __BIG_ENDIAN
2193dda5
AS		 391 ohci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
392 ohci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
b0abf36f
PM		 393#else
394 ohci_ctl.s.l2c_buff_emod = 0; /* not swapped. */
395 ohci_ctl.s.l2c_desc_emod = 0; /* not swapped. */
396 ohci_ctl.s.inv_reg_a2 = 1;
397#endif
2193dda5
AS		 398 cvmx_write_csr(CVMX_UCTLX_OHCI_CTL(0), ohci_ctl.u64);
399
400 octeon2_usb_clocks_stop();
401}
402
340fbb8b
DD		 403static int __init octeon_ohci_device_init(void)
404{
405 struct platform_device *pd;
a95cfa6b 406 struct device_node *ohci_node;
340fbb8b
DD		 407 int ret = 0;
408
a95cfa6b
AH		 409 ohci_node = of_find_node_by_name(NULL, "ohci");
410 if (!ohci_node)
340fbb8b
DD		 411 return 0;
412
a95cfa6b
AH		 413 pd = of_find_device_by_node(ohci_node);
414 if (!pd)
415 return 0;
340fbb8b 416
2193dda5 417 pd->dev.platform_data = &octeon_ohci_pdata;
a95cfa6b 418 octeon_ohci_hw_start(&pd->dev);
340fbb8b 419
340fbb8b
DD		 420 return ret;
421}
422device_initcall(octeon_ohci_device_init);
423
424#endif /* CONFIG_USB */
425
a95cfa6b 426
7ed18152
DD		 427static struct of_device_id __initdata octeon_ids[] = {
428 { .compatible = "simple-bus", },
429 { .compatible = "cavium,octeon-6335-uctl", },
d617f9e9 430 { .compatible = "cavium,octeon-5750-usbn", },
7ed18152
DD		 431 { .compatible = "cavium,octeon-3860-bootbus", },
432 { .compatible = "cavium,mdio-mux", },
433 { .compatible = "gpio-leds", },
434 {},
435};
436
437static bool __init octeon_has_88e1145(void)
438{
439 return !OCTEON_IS_MODEL(OCTEON_CN52XX) &&
440 !OCTEON_IS_MODEL(OCTEON_CN6XXX) &&
441 !OCTEON_IS_MODEL(OCTEON_CN56XX);
442}
443
444static void __init octeon_fdt_set_phy(int eth, int phy_addr)
445{
446 const __be32 *phy_handle;
447 const __be32 *alt_phy_handle;
448 const __be32 *reg;
449 u32 phandle;
450 int phy;
451 int alt_phy;
452 const char *p;
453 int current_len;
454 char new_name[20];
455
456 phy_handle = fdt_getprop(initial_boot_params, eth, "phy-handle", NULL);
457 if (!phy_handle)
458 return;
459
460 phandle = be32_to_cpup(phy_handle);
461 phy = fdt_node_offset_by_phandle(initial_boot_params, phandle);
462
463 alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
464 if (alt_phy_handle) {
465 u32 alt_phandle = be32_to_cpup(alt_phy_handle);
466 alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle);
467 } else {
468 alt_phy = -1;
469 }
470
471 if (phy_addr < 0 || phy < 0) {
472 /* Delete the PHY things */
473 fdt_nop_property(initial_boot_params, eth, "phy-handle");
474 /* This one may fail */
475 fdt_nop_property(initial_boot_params, eth, "cavium,alt-phy-handle");
476 if (phy >= 0)
477 fdt_nop_node(initial_boot_params, phy);
478 if (alt_phy >= 0)
479 fdt_nop_node(initial_boot_params, alt_phy);
480 return;
481 }
482
483 if (phy_addr >= 256 && alt_phy > 0) {
484 const struct fdt_property *phy_prop;
485 struct fdt_property *alt_prop;
486 u32 phy_handle_name;
487
488 /* Use the alt phy node instead.*/
489 phy_prop = fdt_get_property(initial_boot_params, eth, "phy-handle", NULL);
490 phy_handle_name = phy_prop->nameoff;
491 fdt_nop_node(initial_boot_params, phy);
492 fdt_nop_property(initial_boot_params, eth, "phy-handle");
493 alt_prop = fdt_get_property_w(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
494 alt_prop->nameoff = phy_handle_name;
495 phy = alt_phy;
496 }
497
498 phy_addr &= 0xff;
499
500 if (octeon_has_88e1145()) {
501 fdt_nop_property(initial_boot_params, phy, "marvell,reg-init");
502 memset(new_name, 0, sizeof(new_name));
503 strcpy(new_name, "marvell,88e1145");
504 p = fdt_getprop(initial_boot_params, phy, "compatible",
505 &current_len);
506 if (p && current_len >= strlen(new_name))
507 fdt_setprop_inplace(initial_boot_params, phy,
508 "compatible", new_name, current_len);
509 }
510
511 reg = fdt_getprop(initial_boot_params, phy, "reg", NULL);
512 if (phy_addr == be32_to_cpup(reg))
513 return;
514
515 fdt_setprop_inplace_cell(initial_boot_params, phy, "reg", phy_addr);
516
517 snprintf(new_name, sizeof(new_name), "ethernet-phy@%x", phy_addr);
518
519 p = fdt_get_name(initial_boot_params, phy, &current_len);
520 if (p && current_len == strlen(new_name))
521 fdt_set_name(initial_boot_params, phy, new_name);
522 else
523 pr_err("Error: could not rename ethernet phy: <%s>", p);
524}
525
526static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac)
527{
528 u8 new_mac[6];
529 u64 mac = *pmac;
530 int r;
531
532 new_mac[0] = (mac >> 40) & 0xff;
533 new_mac[1] = (mac >> 32) & 0xff;
534 new_mac[2] = (mac >> 24) & 0xff;
535 new_mac[3] = (mac >> 16) & 0xff;
536 new_mac[4] = (mac >> 8) & 0xff;
537 new_mac[5] = mac & 0xff;
538
539 r = fdt_setprop_inplace(initial_boot_params, n, "local-mac-address",
540 new_mac, sizeof(new_mac));
541
542 if (r) {
543 pr_err("Setting \"local-mac-address\" failed %d", r);
544 return;
545 }
546 *pmac = mac + 1;
547}
548
549static void __init octeon_fdt_rm_ethernet(int node)
550{
551 const __be32 *phy_handle;
552
553 phy_handle = fdt_getprop(initial_boot_params, node, "phy-handle", NULL);
554 if (phy_handle) {
555 u32 ph = be32_to_cpup(phy_handle);
556 int p = fdt_node_offset_by_phandle(initial_boot_params, ph);
557 if (p >= 0)
558 fdt_nop_node(initial_boot_params, p);
559 }
560 fdt_nop_node(initial_boot_params, node);
561}
562
43349b9e 563static void __init octeon_fdt_pip_port(int iface, int i, int p, int max)
7ed18152
DD		 564{
565 char name_buffer[20];
566 int eth;
567 int phy_addr;
568 int ipd_port;
569
570 snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p);
571 eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer);
572 if (eth < 0)
573 return;
574 if (p > max) {
575 pr_debug("Deleting port %x:%x\n", i, p);
576 octeon_fdt_rm_ethernet(eth);
577 return;
578 }
579 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
580 ipd_port = (0x100 * i) + (0x10 * p) + 0x800;
581 else
582 ipd_port = 16 * i + p;
583
584 phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
585 octeon_fdt_set_phy(eth, phy_addr);
7ed18152
DD		 586}
587
43349b9e 588static void __init octeon_fdt_pip_iface(int pip, int idx)
7ed18152
DD		 589{
590 char name_buffer[20];
591 int iface;
592 int p;
ab2bb148 593 int count = 0;
7ed18152 594
7ed18152
DD		 595 snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx);
596 iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer);
597 if (iface < 0)
598 return;
599
b2e4f156
AK		 600 if (cvmx_helper_interface_enumerate(idx) == 0)
601 count = cvmx_helper_ports_on_interface(idx);
602
7ed18152 603 for (p = 0; p < 16; p++)
43349b9e
AK		 604 octeon_fdt_pip_port(iface, idx, p, count - 1);
605}
606
607void __init octeon_fill_mac_addresses(void)
608{
609 const char *alias_prop;
610 char name_buffer[20];
611 u64 mac_addr_base;
612 int aliases;
613 int pip;
614 int i;
615
616 aliases = fdt_path_offset(initial_boot_params, "/aliases");
617 if (aliases < 0)
618 return;
619
620 mac_addr_base =
621 ((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 |
622 ((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 |
623 ((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 |
624 ((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 |
625 ((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 |
626 (octeon_bootinfo->mac_addr_base[5] & 0xffull);
627
628 for (i = 0; i < 2; i++) {
629 int mgmt;
630
631 snprintf(name_buffer, sizeof(name_buffer), "mix%d", i);
632 alias_prop = fdt_getprop(initial_boot_params, aliases,
633 name_buffer, NULL);
634 if (!alias_prop)
635 continue;
636 mgmt = fdt_path_offset(initial_boot_params, alias_prop);
637 if (mgmt < 0)
638 continue;
639 octeon_fdt_set_mac_addr(mgmt, &mac_addr_base);
640 }
641
642 alias_prop = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
643 if (!alias_prop)
644 return;
645
646 pip = fdt_path_offset(initial_boot_params, alias_prop);
647 if (pip < 0)
648 return;
649
650 for (i = 0; i <= 4; i++) {
651 int iface;
652 int p;
653
654 snprintf(name_buffer, sizeof(name_buffer), "interface@%d", i);
655 iface = fdt_subnode_offset(initial_boot_params, pip,
656 name_buffer);
657 if (iface < 0)
658 continue;
659 for (p = 0; p < 16; p++) {
660 int eth;
661
662 snprintf(name_buffer, sizeof(name_buffer),
663 "ethernet@%x", p);
664 eth = fdt_subnode_offset(initial_boot_params, iface,
665 name_buffer);
666 if (eth < 0)
667 continue;
668 octeon_fdt_set_mac_addr(eth, &mac_addr_base);
669 }
670 }
7ed18152
DD		 671}
672
673int __init octeon_prune_device_tree(void)
674{
675 int i, max_port, uart_mask;
676 const char *pip_path;
677 const char *alias_prop;
678 char name_buffer[20];
679 int aliases;
7ed18152
DD		 680
681 if (fdt_check_header(initial_boot_params))
682 panic("Corrupt Device Tree.");
683
684 aliases = fdt_path_offset(initial_boot_params, "/aliases");
685 if (aliases < 0) {
686 pr_err("Error: No /aliases node in device tree.");
687 return -EINVAL;
688 }
689
7ed18152
DD		 690 if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
691 max_port = 2;
692 else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))
693 max_port = 1;
694 else
695 max_port = 0;
696
697 if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E)
698 max_port = 0;
699
700 for (i = 0; i < 2; i++) {
701 int mgmt;
702 snprintf(name_buffer, sizeof(name_buffer),
703 "mix%d", i);
704 alias_prop = fdt_getprop(initial_boot_params, aliases,
705 name_buffer, NULL);
706 if (alias_prop) {
707 mgmt = fdt_path_offset(initial_boot_params, alias_prop);
708 if (mgmt < 0)
709 continue;
710 if (i >= max_port) {
711 pr_debug("Deleting mix%d\n", i);
712 octeon_fdt_rm_ethernet(mgmt);
713 fdt_nop_property(initial_boot_params, aliases,
714 name_buffer);
715 } else {
716 int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i);
717 octeon_fdt_set_phy(mgmt, phy_addr);
7ed18152
DD		 718 }
719 }
720 }
721
722 pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
723 if (pip_path) {
724 int pip = fdt_path_offset(initial_boot_params, pip_path);
70342287 725 if (pip >= 0)
7ed18152 726 for (i = 0; i <= 4; i++)
43349b9e 727 octeon_fdt_pip_iface(pip, i);
7ed18152
DD		 728 }
729
730 /* I2C */
731 if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
732 OCTEON_IS_MODEL(OCTEON_CN63XX) ||
733 OCTEON_IS_MODEL(OCTEON_CN68XX) ||
734 OCTEON_IS_MODEL(OCTEON_CN56XX))
735 max_port = 2;
736 else
737 max_port = 1;
738
739 for (i = 0; i < 2; i++) {
740 int i2c;
741 snprintf(name_buffer, sizeof(name_buffer),
742 "twsi%d", i);
743 alias_prop = fdt_getprop(initial_boot_params, aliases,
744 name_buffer, NULL);
745
746 if (alias_prop) {
747 i2c = fdt_path_offset(initial_boot_params, alias_prop);
748 if (i2c < 0)
749 continue;
750 if (i >= max_port) {
751 pr_debug("Deleting twsi%d\n", i);
752 fdt_nop_node(initial_boot_params, i2c);
753 fdt_nop_property(initial_boot_params, aliases,
754 name_buffer);
755 }
756 }
757 }
758
759 /* SMI/MDIO */
760 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
761 max_port = 4;
762 else if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
763 OCTEON_IS_MODEL(OCTEON_CN63XX) ||
764 OCTEON_IS_MODEL(OCTEON_CN56XX))
765 max_port = 2;
766 else
767 max_port = 1;
768
769 for (i = 0; i < 2; i++) {
770 int i2c;
771 snprintf(name_buffer, sizeof(name_buffer),
772 "smi%d", i);
773 alias_prop = fdt_getprop(initial_boot_params, aliases,
774 name_buffer, NULL);
775
776 if (alias_prop) {
777 i2c = fdt_path_offset(initial_boot_params, alias_prop);
778 if (i2c < 0)
779 continue;
780 if (i >= max_port) {
781 pr_debug("Deleting smi%d\n", i);
782 fdt_nop_node(initial_boot_params, i2c);
783 fdt_nop_property(initial_boot_params, aliases,
784 name_buffer);
785 }
786 }
787 }
788
789 /* Serial */
790 uart_mask = 3;
791
792 /* Right now CN52XX is the only chip with a third uart */
793 if (OCTEON_IS_MODEL(OCTEON_CN52XX))
794 uart_mask |= 4; /* uart2 */
795
796 for (i = 0; i < 3; i++) {
797 int uart;
798 snprintf(name_buffer, sizeof(name_buffer),
799 "uart%d", i);
800 alias_prop = fdt_getprop(initial_boot_params, aliases,
801 name_buffer, NULL);
802
803 if (alias_prop) {
804 uart = fdt_path_offset(initial_boot_params, alias_prop);
5219343f
DD		 805 if (uart_mask & (1 << i)) {
806 __be32 f;
807
808 f = cpu_to_be32(octeon_get_io_clock_rate());
809 fdt_setprop_inplace(initial_boot_params,
810 uart, "clock-frequency",
811 &f, sizeof(f));
7ed18152 812 continue;
5219343f 813 }
7ed18152
DD		 814 pr_debug("Deleting uart%d\n", i);
815 fdt_nop_node(initial_boot_params, uart);
816 fdt_nop_property(initial_boot_params, aliases,
817 name_buffer);
818 }
819 }
820
821 /* Compact Flash */
822 alias_prop = fdt_getprop(initial_boot_params, aliases,
823 "cf0", NULL);
824 if (alias_prop) {
825 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
826 unsigned long base_ptr, region_base, region_size;
827 unsigned long region1_base = 0;
828 unsigned long region1_size = 0;
829 int cs, bootbus;
830 bool is_16bit = false;
831 bool is_true_ide = false;
832 __be32 new_reg[6];
833 __be32 *ranges;
834 int len;
835
836 int cf = fdt_path_offset(initial_boot_params, alias_prop);
837 base_ptr = 0;
838 if (octeon_bootinfo->major_version == 1
839 && octeon_bootinfo->minor_version >= 1) {
840 if (octeon_bootinfo->compact_flash_common_base_addr)
841 base_ptr = octeon_bootinfo->compact_flash_common_base_addr;
842 } else {
843 base_ptr = 0x1d000800;
844 }
845
846 if (!base_ptr)
847 goto no_cf;
848
849 /* Find CS0 region. */
850 for (cs = 0; cs < 8; cs++) {
851 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
852 region_base = mio_boot_reg_cfg.s.base << 16;
853 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
854 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
855 && base_ptr < region_base + region_size) {
856 is_16bit = mio_boot_reg_cfg.s.width;
857 break;
858 }
859 }
860 if (cs >= 7) {
861 /* cs and cs + 1 are CS0 and CS1, both must be less than 8. */
862 goto no_cf;
863 }
864
865 if (!(base_ptr & 0xfffful)) {
866 /*
867 * Boot loader signals availability of DMA (true_ide
868 * mode) by setting low order bits of base_ptr to
869 * zero.
870 */
871
872 /* Asume that CS1 immediately follows. */
873 mio_boot_reg_cfg.u64 =
874 cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1));
875 region1_base = mio_boot_reg_cfg.s.base << 16;
876 region1_size = (mio_boot_reg_cfg.s.size + 1) << 16;
877 if (!mio_boot_reg_cfg.s.en)
878 goto no_cf;
879 is_true_ide = true;
880
881 } else {
882 fdt_nop_property(initial_boot_params, cf, "cavium,true-ide");
883 fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle");
884 if (!is_16bit) {
885 __be32 width = cpu_to_be32(8);
886 fdt_setprop_inplace(initial_boot_params, cf,
887 "cavium,bus-width", &width, sizeof(width));
888 }
889 }
890 new_reg[0] = cpu_to_be32(cs);
891 new_reg[1] = cpu_to_be32(0);
892 new_reg[2] = cpu_to_be32(0x10000);
893 new_reg[3] = cpu_to_be32(cs + 1);
894 new_reg[4] = cpu_to_be32(0);
895 new_reg[5] = cpu_to_be32(0x10000);
896 fdt_setprop_inplace(initial_boot_params, cf,
897 "reg", new_reg, sizeof(new_reg));
898
899 bootbus = fdt_parent_offset(initial_boot_params, cf);
900 if (bootbus < 0)
901 goto no_cf;
902 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
903 if (!ranges || len < (5 * 8 * sizeof(__be32)))
904 goto no_cf;
905
906 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
907 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
908 ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
909 if (is_true_ide) {
910 cs++;
911 ranges[(cs * 5) + 2] = cpu_to_be32(region1_base >> 32);
912 ranges[(cs * 5) + 3] = cpu_to_be32(region1_base & 0xffffffff);
913 ranges[(cs * 5) + 4] = cpu_to_be32(region1_size);
914 }
915 goto end_cf;
916no_cf:
917 fdt_nop_node(initial_boot_params, cf);
918
919end_cf:
920 ;
921 }
922
923 /* 8 char LED */
924 alias_prop = fdt_getprop(initial_boot_params, aliases,
925 "led0", NULL);
926 if (alias_prop) {
927 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
928 unsigned long base_ptr, region_base, region_size;
929 int cs, bootbus;
930 __be32 new_reg[6];
931 __be32 *ranges;
932 int len;
933 int led = fdt_path_offset(initial_boot_params, alias_prop);
934
935 base_ptr = octeon_bootinfo->led_display_base_addr;
936 if (base_ptr == 0)
937 goto no_led;
938 /* Find CS0 region. */
939 for (cs = 0; cs < 8; cs++) {
940 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
941 region_base = mio_boot_reg_cfg.s.base << 16;
942 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
943 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
944 && base_ptr < region_base + region_size)
945 break;
946 }
947
948 if (cs > 7)
949 goto no_led;
950
951 new_reg[0] = cpu_to_be32(cs);
952 new_reg[1] = cpu_to_be32(0x20);
953 new_reg[2] = cpu_to_be32(0x20);
954 new_reg[3] = cpu_to_be32(cs);
955 new_reg[4] = cpu_to_be32(0);
956 new_reg[5] = cpu_to_be32(0x20);
957 fdt_setprop_inplace(initial_boot_params, led,
958 "reg", new_reg, sizeof(new_reg));
959
960 bootbus = fdt_parent_offset(initial_boot_params, led);
961 if (bootbus < 0)
962 goto no_led;
963 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
964 if (!ranges || len < (5 * 8 * sizeof(__be32)))
965 goto no_led;
966
967 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
968 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
969 ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
970 goto end_led;
971
972no_led:
973 fdt_nop_node(initial_boot_params, led);
974end_led:
975 ;
976 }
977
978 /* OHCI/UHCI USB */
979 alias_prop = fdt_getprop(initial_boot_params, aliases,
980 "uctl", NULL);
981 if (alias_prop) {
982 int uctl = fdt_path_offset(initial_boot_params, alias_prop);
983
984 if (uctl >= 0 && (!OCTEON_IS_MODEL(OCTEON_CN6XXX) ||
985 octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC2E)) {
986 pr_debug("Deleting uctl\n");
987 fdt_nop_node(initial_boot_params, uctl);
988 fdt_nop_property(initial_boot_params, aliases, "uctl");
989 } else if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E ||
990 octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC4E) {
991 /* Missing "refclk-type" defaults to crystal. */
992 fdt_nop_property(initial_boot_params, uctl, "refclk-type");
993 }
994 }
995
d617f9e9
DD		 996 /* DWC2 USB */
997 alias_prop = fdt_getprop(initial_boot_params, aliases,
998 "usbn", NULL);
999 if (alias_prop) {
1000 int usbn = fdt_path_offset(initial_boot_params, alias_prop);
1001
1002 if (usbn >= 0 && (current_cpu_type() == CPU_CAVIUM_OCTEON2 ||
1003 !octeon_has_feature(OCTEON_FEATURE_USB))) {
1004 pr_debug("Deleting usbn\n");
1005 fdt_nop_node(initial_boot_params, usbn);
1006 fdt_nop_property(initial_boot_params, aliases, "usbn");
1007 } else {
1008 __be32 new_f[1];
1009 enum cvmx_helper_board_usb_clock_types c;
1010 c = __cvmx_helper_board_usb_get_clock_type();
1011 switch (c) {
1012 case USB_CLOCK_TYPE_REF_48:
1013 new_f[0] = cpu_to_be32(48000000);
1014 fdt_setprop_inplace(initial_boot_params, usbn,
1015 "refclk-frequency", new_f, sizeof(new_f));
1016 /* Fall through ...*/
1017 case USB_CLOCK_TYPE_REF_12:
1018 /* Missing "refclk-type" defaults to external. */
1019 fdt_nop_property(initial_boot_params, usbn, "refclk-type");
1020 break;
1021 default:
1022 break;
1023 }
1024 }
1025 }
1026
05f5507f
AK		 1027 if (octeon_bootinfo->board_type != CVMX_BOARD_TYPE_CUST_DSR1000N) {
1028 int dsr1000n_leds = fdt_path_offset(initial_boot_params,
1029 "/dsr1000n-leds");
1030 if (dsr1000n_leds >= 0)
1031 fdt_nop_node(initial_boot_params, dsr1000n_leds);
1032 }
1033
7ed18152
DD		 1034 return 0;
1035}
1036
1037static int __init octeon_publish_devices(void)
1038{
1039 return of_platform_bus_probe(NULL, octeon_ids, NULL);
1040}
1041device_initcall(octeon_publish_devices);
1042
512254ba
DD		 1043MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
1044MODULE_LICENSE("GPL");
1045MODULE_DESCRIPTION("Platform driver for Octeon SOC");
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