[mirror_ubuntu-artful-kernel.git] / arch / mips / cavium-octeon / smp.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
 */
#include <linux/cpu.h>
#include <linux/delay.h>
#include <linux/smp.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/sched.h>
#include <linux/module.h>

#include <asm/mmu_context.h>
#include <asm/time.h>
#include <asm/setup.h>

#include <asm/octeon/octeon.h>

#include "octeon_boot.h"

volatile unsigned long octeon_processor_boot = 0xff;
volatile unsigned long octeon_processor_sp;
volatile unsigned long octeon_processor_gp;

#ifdef CONFIG_HOTPLUG_CPU
uint64_t octeon_bootloader_entry_addr;
EXPORT_SYMBOL(octeon_bootloader_entry_addr);
#endif

static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
{
	const int coreid = cvmx_get_core_num();
	uint64_t action;

	/* Load the mailbox register to figure out what we're supposed to do */
	action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(coreid)) & 0xffff;

	/* Clear the mailbox to clear the interrupt */
	cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), action);

	if (action & SMP_CALL_FUNCTION)
		generic_smp_call_function_interrupt();
	if (action & SMP_RESCHEDULE_YOURSELF)
		scheduler_ipi();

	/* Check if we've been told to flush the icache */
	if (action & SMP_ICACHE_FLUSH)
		asm volatile ("synci 0($0)\n");
	return IRQ_HANDLED;
}

/**
 * Cause the function described by call_data to be executed on the passed
 * cpu.	 When the function has finished, increment the finished field of
 * call_data.
 */
void octeon_send_ipi_single(int cpu, unsigned int action)
{
	int coreid = cpu_logical_map(cpu);
	/*
	pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu,
	       coreid, action);
	*/
	cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action);
}

static inline void octeon_send_ipi_mask(const struct cpumask *mask,
					unsigned int action)
{
	unsigned int i;

	for_each_cpu(i, mask)
		octeon_send_ipi_single(i, action);
}

/**
 * Detect available CPUs, populate cpu_possible_mask
 */
static void octeon_smp_hotplug_setup(void)
{
#ifdef CONFIG_HOTPLUG_CPU
	struct linux_app_boot_info *labi;

	if (!setup_max_cpus)
		return;

	labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
	if (labi->labi_signature != LABI_SIGNATURE) {
		pr_info("The bootloader on this board does not support HOTPLUG_CPU.");
		return;
	}

	octeon_bootloader_entry_addr = labi->InitTLBStart_addr;
#endif
}

static void octeon_smp_setup(void)
{
	const int coreid = cvmx_get_core_num();
	int cpus;
	int id;
	int core_mask = octeon_get_boot_coremask();
	struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get();

#ifdef CONFIG_HOTPLUG_CPU
	unsigned int num_cores = cvmx_octeon_num_cores();
#endif

	/* The present CPUs are initially just the boot cpu (CPU 0). */
	for (id = 0; id < NR_CPUS; id++) {
		set_cpu_possible(id, id == 0);
		set_cpu_present(id, id == 0);
	}

	__cpu_number_map[coreid] = 0;
	__cpu_logical_map[0] = coreid;

	/* The present CPUs get the lowest CPU numbers. */
	cpus = 1;
	for (id = 0; id < NR_CPUS; id++) {
		if ((id != coreid) && cvmx_coremask_is_core_set(&sysinfo->core_mask, id)) {
			set_cpu_possible(cpus, true);
			set_cpu_present(cpus, true);
			__cpu_number_map[id] = cpus;
			__cpu_logical_map[cpus] = id;
			cpus++;
		}
	}

#ifdef CONFIG_HOTPLUG_CPU
	/*
	 * The possible CPUs are all those present on the chip.	 We
	 * will assign CPU numbers for possible cores as well.	Cores
	 * are always consecutively numberd from 0.
	 */
	for (id = 0; setup_max_cpus && octeon_bootloader_entry_addr &&
		     id < num_cores && id < NR_CPUS; id++) {
		if (!(core_mask & (1 << id))) {
			set_cpu_possible(cpus, true);
			__cpu_number_map[id] = cpus;
			__cpu_logical_map[cpus] = id;
			cpus++;
		}
	}
#endif

	octeon_smp_hotplug_setup();
}

/**
 * Firmware CPU startup hook
 *
 */
static void octeon_boot_secondary(int cpu, struct task_struct *idle)
{
	int count;

	pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu,
		cpu_logical_map(cpu));

	octeon_processor_sp = __KSTK_TOS(idle);
	octeon_processor_gp = (unsigned long)(task_thread_info(idle));
	octeon_processor_boot = cpu_logical_map(cpu);
	mb();

	count = 10000;
	while (octeon_processor_sp && count) {
		/* Waiting for processor to get the SP and GP */
		udelay(1);
		count--;
	}
	if (count == 0)
		pr_err("Secondary boot timeout\n");
}

/**
 * After we've done initial boot, this function is called to allow the
 * board code to clean up state, if needed
 */
static void octeon_init_secondary(void)
{
	unsigned int sr;

	sr = set_c0_status(ST0_BEV);
	write_c0_ebase((u32)ebase);
	write_c0_status(sr);

	octeon_check_cpu_bist();
	octeon_init_cvmcount();

	octeon_irq_setup_secondary();
}

/**
 * Callout to firmware before smp_init
 *
 */
void octeon_prepare_cpus(unsigned int max_cpus)
{
	/*
	 * Only the low order mailbox bits are used for IPIs, leave
	 * the other bits alone.
	 */
	cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff);
	if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt,
			IRQF_PERCPU | IRQF_NO_THREAD, "SMP-IPI",
			mailbox_interrupt)) {
		panic("Cannot request_irq(OCTEON_IRQ_MBOX0)");
	}
}

/**
 * Last chance for the board code to finish SMP initialization before
 * the CPU is "online".
 */
static void octeon_smp_finish(void)
{
	octeon_user_io_init();

	/* to generate the first CPU timer interrupt */
	write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
	local_irq_enable();
}

#ifdef CONFIG_HOTPLUG_CPU

/* State of each CPU. */
DEFINE_PER_CPU(int, cpu_state);

static int octeon_cpu_disable(void)
{
	unsigned int cpu = smp_processor_id();

	if (cpu == 0)
		return -EBUSY;

	if (!octeon_bootloader_entry_addr)
		return -ENOTSUPP;

	set_cpu_online(cpu, false);
	cpumask_clear_cpu(cpu, &cpu_callin_map);
	octeon_fixup_irqs();

	__flush_cache_all();
	local_flush_tlb_all();

	return 0;
}

static void octeon_cpu_die(unsigned int cpu)
{
	int coreid = cpu_logical_map(cpu);
	uint32_t mask, new_mask;
	const struct cvmx_bootmem_named_block_desc *block_desc;

	while (per_cpu(cpu_state, cpu) != CPU_DEAD)
		cpu_relax();

	/*
	 * This is a bit complicated strategics of getting/settig available
	 * cores mask, copied from bootloader
	 */

	mask = 1 << coreid;
	/* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */
	block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);

	if (!block_desc) {
		struct linux_app_boot_info *labi;

		labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);

		labi->avail_coremask |= mask;
		new_mask = labi->avail_coremask;
	} else {		       /* alternative, already initialized */
		uint32_t *p = (uint32_t *)PHYS_TO_XKSEG_CACHED(block_desc->base_addr +
							       AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
		*p |= mask;
		new_mask = *p;
	}

	pr_info("Reset core %d. Available Coremask = 0x%x \n", coreid, new_mask);
	mb();
	cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
	cvmx_write_csr(CVMX_CIU_PP_RST, 0);
}

void play_dead(void)
{
	int cpu = cpu_number_map(cvmx_get_core_num());

	idle_task_exit();
	octeon_processor_boot = 0xff;
	per_cpu(cpu_state, cpu) = CPU_DEAD;

	mb();

	while (1)	/* core will be reset here */
		;
}

extern void kernel_entry(unsigned long arg1, ...);

static void start_after_reset(void)
{
	kernel_entry(0, 0, 0);	/* set a2 = 0 for secondary core */
}

static int octeon_update_boot_vector(unsigned int cpu)
{

	int coreid = cpu_logical_map(cpu);
	uint32_t avail_coremask;
	const struct cvmx_bootmem_named_block_desc *block_desc;
	struct boot_init_vector *boot_vect =
		(struct boot_init_vector *)PHYS_TO_XKSEG_CACHED(BOOTLOADER_BOOT_VECTOR);

	block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);

	if (!block_desc) {
		struct linux_app_boot_info *labi;

		labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);

		avail_coremask = labi->avail_coremask;
		labi->avail_coremask &= ~(1 << coreid);
	} else {		       /* alternative, already initialized */
		avail_coremask = *(uint32_t *)PHYS_TO_XKSEG_CACHED(
			block_desc->base_addr + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
	}

	if (!(avail_coremask & (1 << coreid))) {
		/* core not available, assume, that caught by simple-executive */
		cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
		cvmx_write_csr(CVMX_CIU_PP_RST, 0);
	}

	boot_vect[coreid].app_start_func_addr =
		(uint32_t) (unsigned long) start_after_reset;
	boot_vect[coreid].code_addr = octeon_bootloader_entry_addr;

	mb();

	cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask);

	return 0;
}

static int octeon_cpu_callback(struct notifier_block *nfb,
	unsigned long action, void *hcpu)
{
	unsigned int cpu = (unsigned long)hcpu;

	switch (action) {
	case CPU_UP_PREPARE:
		octeon_update_boot_vector(cpu);
		break;
	case CPU_ONLINE:
		pr_info("Cpu %d online\n", cpu);
		break;
	case CPU_DEAD:
		break;
	}

	return NOTIFY_OK;
}

static int register_cavium_notifier(void)
{
	hotcpu_notifier(octeon_cpu_callback, 0);
	return 0;
}
late_initcall(register_cavium_notifier);

#endif	/* CONFIG_HOTPLUG_CPU */

struct plat_smp_ops octeon_smp_ops = {
	.send_ipi_single	= octeon_send_ipi_single,
	.send_ipi_mask		= octeon_send_ipi_mask,
	.init_secondary		= octeon_init_secondary,
	.smp_finish		= octeon_smp_finish,
	.boot_secondary		= octeon_boot_secondary,
	.smp_setup		= octeon_smp_setup,
	.prepare_cpus		= octeon_prepare_cpus,
#ifdef CONFIG_HOTPLUG_CPU
	.cpu_disable		= octeon_cpu_disable,
	.cpu_die		= octeon_cpu_die,
#endif
};
Commit	Line	Data
5b3b1688 DD	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
edfcbb8c	6	* Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
5b3b1688	7	*/
773cb77d	8	#include <linux/cpu.h>
5b3b1688 DD	9	#include <linux/delay.h>
	10	#include <linux/smp.h>
	11	#include <linux/interrupt.h>
	12	#include <linux/kernel_stat.h>
	13	#include <linux/sched.h>
	14	#include <linux/module.h>
	15
	16	#include <asm/mmu_context.h>
5b3b1688	17	#include <asm/time.h>
b81947c6	18	#include <asm/setup.h>
5b3b1688 DD	19
	20	#include <asm/octeon/octeon.h>
	21
773cb77d RB	22	#include "octeon_boot.h"
773cb77d RB	23
5b3b1688 DD	24	volatile unsigned long octeon_processor_boot = 0xff;
	25	volatile unsigned long octeon_processor_sp;
	26	volatile unsigned long octeon_processor_gp;
	27
773cb77d	28	#ifdef CONFIG_HOTPLUG_CPU
babba4f1 DD	29	uint64_t octeon_bootloader_entry_addr;
babba4f1 DD	30	EXPORT_SYMBOL(octeon_bootloader_entry_addr);
773cb77d RB	31	#endif
773cb77d RB	32
5b3b1688 DD	33	static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
	34	{
	35	const int coreid = cvmx_get_core_num();
	36	uint64_t action;
	37
	38	/* Load the mailbox register to figure out what we're supposed to do */
e650ce0f	39	action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(coreid)) & 0xffff;
5b3b1688 DD	40
	41	/* Clear the mailbox to clear the interrupt */
	42	cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), action);
	43
	44	if (action & SMP_CALL_FUNCTION)
4ace6139	45	generic_smp_call_function_interrupt();
184748cc PZ	46	if (action & SMP_RESCHEDULE_YOURSELF)
184748cc PZ	47	scheduler_ipi();
5b3b1688 DD	48
	49	/* Check if we've been told to flush the icache */
	50	if (action & SMP_ICACHE_FLUSH)
	51	asm volatile ("synci 0($0)\n");
	52	return IRQ_HANDLED;
	53	}
	54
	55	/**
	56	* Cause the function described by call_data to be executed on the passed
70342287	57	* cpu. When the function has finished, increment the finished field of
5b3b1688 DD	58	* call_data.
	59	*/
	60	void octeon_send_ipi_single(int cpu, unsigned int action)
	61	{
	62	int coreid = cpu_logical_map(cpu);
	63	/*
	64	pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu,
	65	coreid, action);
	66	*/
	67	cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action);
	68	}
	69
067f3290 DD	70	static inline void octeon_send_ipi_mask(const struct cpumask *mask,
067f3290 DD	71	unsigned int action)
5b3b1688 DD	72	{
	73	unsigned int i;
	74
8dd92891	75	for_each_cpu(i, mask)
5b3b1688 DD	76	octeon_send_ipi_single(i, action);
	77	}
	78
	79	/**
5f054e31	80	* Detect available CPUs, populate cpu_possible_mask
5b3b1688	81	*/
773cb77d RB	82	static void octeon_smp_hotplug_setup(void)
	83	{
	84	#ifdef CONFIG_HOTPLUG_CPU
babba4f1 DD	85	struct linux_app_boot_info *labi;
babba4f1 DD	86
5ca0e377 AK	87	if (!setup_max_cpus)
	88	return;
	89
babba4f1	90	labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
eac44d9c AK	91	if (labi->labi_signature != LABI_SIGNATURE) {
	92	pr_info("The bootloader on this board does not support HOTPLUG_CPU.");
	93	return;
	94	}
babba4f1 DD	95
babba4f1 DD	96	octeon_bootloader_entry_addr = labi->InitTLBStart_addr;
773cb77d RB	97	#endif
	98	}
	99
5b3b1688 DD	100	static void octeon_smp_setup(void)
	101	{
	102	const int coreid = cvmx_get_core_num();
	103	int cpus;
	104	int id;
5b3b1688	105	int core_mask = octeon_get_boot_coremask();
7d52ab16 DD	106	struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get();
7d52ab16 DD	107
edfcbb8c DD	108	#ifdef CONFIG_HOTPLUG_CPU
	109	unsigned int num_cores = cvmx_octeon_num_cores();
	110	#endif
	111
	112	/* The present CPUs are initially just the boot cpu (CPU 0). */
	113	for (id = 0; id < NR_CPUS; id++) {
	114	set_cpu_possible(id, id == 0);
	115	set_cpu_present(id, id == 0);
	116	}
5b3b1688	117
5b3b1688 DD	118	__cpu_number_map[coreid] = 0;
5b3b1688 DD	119	__cpu_logical_map[0] = coreid;
5b3b1688	120
edfcbb8c	121	/* The present CPUs get the lowest CPU numbers. */
5b3b1688	122	cpus = 1;
edfcbb8c	123	for (id = 0; id < NR_CPUS; id++) {
7d52ab16	124	if ((id != coreid) && cvmx_coremask_is_core_set(&sysinfo->core_mask, id)) {
edfcbb8c DD	125	set_cpu_possible(cpus, true);
	126	set_cpu_present(cpus, true);
	127	__cpu_number_map[id] = cpus;
	128	__cpu_logical_map[cpus] = id;
	129	cpus++;
	130	}
	131	}
	132
	133	#ifdef CONFIG_HOTPLUG_CPU
	134	/*
70342287 RB	135	* The possible CPUs are all those present on the chip. We
70342287 RB	136	* will assign CPU numbers for possible cores as well. Cores
edfcbb8c DD	137	* are always consecutively numberd from 0.
edfcbb8c DD	138	*/
eac44d9c AK	139	for (id = 0; setup_max_cpus && octeon_bootloader_entry_addr &&
eac44d9c AK	140	id < num_cores && id < NR_CPUS; id++) {
edfcbb8c DD	141	if (!(core_mask & (1 << id))) {
edfcbb8c DD	142	set_cpu_possible(cpus, true);
5b3b1688 DD	143	__cpu_number_map[id] = cpus;
	144	__cpu_logical_map[cpus] = id;
	145	cpus++;
	146	}
	147	}
edfcbb8c	148	#endif
773cb77d RB	149
773cb77d RB	150	octeon_smp_hotplug_setup();
5b3b1688 DD	151	}
	152
	153	/**
	154	* Firmware CPU startup hook
	155	*
	156	*/
	157	static void octeon_boot_secondary(int cpu, struct task_struct *idle)
	158	{
	159	int count;
	160
	161	pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu,
	162	cpu_logical_map(cpu));
	163
	164	octeon_processor_sp = __KSTK_TOS(idle);
	165	octeon_processor_gp = (unsigned long)(task_thread_info(idle));
	166	octeon_processor_boot = cpu_logical_map(cpu);
	167	mb();
	168
	169	count = 10000;
	170	while (octeon_processor_sp && count) {
	171	/* Waiting for processor to get the SP and GP */
	172	udelay(1);
	173	count--;
	174	}
	175	if (count == 0)
	176	pr_err("Secondary boot timeout\n");
	177	}
	178
	179	/**
	180	* After we've done initial boot, this function is called to allow the
	181	* board code to clean up state, if needed
	182	*/
078a55fc	183	static void octeon_init_secondary(void)
5b3b1688	184	{
babba4f1	185	unsigned int sr;
5b3b1688	186
babba4f1 DD	187	sr = set_c0_status(ST0_BEV);
	188	write_c0_ebase((u32)ebase);
	189	write_c0_status(sr);
	190
5b3b1688 DD	191	octeon_check_cpu_bist();
5b3b1688 DD	192	octeon_init_cvmcount();
0c326387 DD	193
0c326387 DD	194	octeon_irq_setup_secondary();
5b3b1688 DD	195	}
	196
	197	/**
	198	* Callout to firmware before smp_init
	199	*
	200	*/
	201	void octeon_prepare_cpus(unsigned int max_cpus)
	202	{
e650ce0f DD	203	/*
	204	* Only the low order mailbox bits are used for IPIs, leave
	205	* the other bits alone.
	206	*/
	207	cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff);
e63fb7a9 VS	208	if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt,
	209	IRQF_PERCPU \| IRQF_NO_THREAD, "SMP-IPI",
	210	mailbox_interrupt)) {
ab75dc02	211	panic("Cannot request_irq(OCTEON_IRQ_MBOX0)");
5b3b1688	212	}
5b3b1688 DD	213	}
	214
	215	/**
	216	* Last chance for the board code to finish SMP initialization before
	217	* the CPU is "online".
	218	*/
	219	static void octeon_smp_finish(void)
	220	{
5b3b1688 DD	221	octeon_user_io_init();
	222
	223	/* to generate the first CPU timer interrupt */
	224	write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
1bcfecc0	225	local_irq_enable();
5b3b1688 DD	226	}
5b3b1688 DD	227
773cb77d RB	228	#ifdef CONFIG_HOTPLUG_CPU
	229
	230	/* State of each CPU. */
	231	DEFINE_PER_CPU(int, cpu_state);
	232
773cb77d RB	233	static int octeon_cpu_disable(void)
	234	{
	235	unsigned int cpu = smp_processor_id();
	236
	237	if (cpu == 0)
	238	return -EBUSY;
	239
eac44d9c AK	240	if (!octeon_bootloader_entry_addr)
	241	return -ENOTSUPP;
	242
0b5f9c00	243	set_cpu_online(cpu, false);
8dd92891	244	cpumask_clear_cpu(cpu, &cpu_callin_map);
17efb59a	245	octeon_fixup_irqs();
773cb77d	246
9329c154	247	__flush_cache_all();
773cb77d RB	248	local_flush_tlb_all();
773cb77d RB	249
773cb77d RB	250	return 0;
	251	}
	252
	253	static void octeon_cpu_die(unsigned int cpu)
	254	{
	255	int coreid = cpu_logical_map(cpu);
babba4f1 DD	256	uint32_t mask, new_mask;
babba4f1 DD	257	const struct cvmx_bootmem_named_block_desc *block_desc;
773cb77d	258
773cb77d RB	259	while (per_cpu(cpu_state, cpu) != CPU_DEAD)
	260	cpu_relax();
	261
	262	/*
	263	* This is a bit complicated strategics of getting/settig available
	264	* cores mask, copied from bootloader
	265	*/
babba4f1 DD	266
babba4f1 DD	267	mask = 1 << coreid;
773cb77d RB	268	/* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */
	269	block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
	270
	271	if (!block_desc) {
babba4f1	272	struct linux_app_boot_info *labi;
773cb77d	273
babba4f1	274	labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
773cb77d	275
babba4f1 DD	276	labi->avail_coremask \|= mask;
	277	new_mask = labi->avail_coremask;
	278	} else { /* alternative, already initialized */
	279	uint32_t p = (uint32_t )PHYS_TO_XKSEG_CACHED(block_desc->base_addr +
	280	AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
	281	*p \|= mask;
	282	new_mask = *p;
773cb77d RB	283	}
773cb77d RB	284
babba4f1 DD	285	pr_info("Reset core %d. Available Coremask = 0x%x \n", coreid, new_mask);
babba4f1 DD	286	mb();
773cb77d RB	287	cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
	288	cvmx_write_csr(CVMX_CIU_PP_RST, 0);
	289	}
	290
	291	void play_dead(void)
	292	{
babba4f1	293	int cpu = cpu_number_map(cvmx_get_core_num());
773cb77d RB	294
	295	idle_task_exit();
	296	octeon_processor_boot = 0xff;
babba4f1 DD	297	per_cpu(cpu_state, cpu) = CPU_DEAD;
	298
	299	mb();
773cb77d RB	300
	301	while (1) /* core will be reset here */
	302	;
	303	}
	304
	305	extern void kernel_entry(unsigned long arg1, ...);
	306
	307	static void start_after_reset(void)
	308	{
70342287	309	kernel_entry(0, 0, 0); /* set a2 = 0 for secondary core */
773cb77d RB	310	}
773cb77d RB	311
babba4f1	312	static int octeon_update_boot_vector(unsigned int cpu)
773cb77d RB	313	{
	314
	315	int coreid = cpu_logical_map(cpu);
babba4f1 DD	316	uint32_t avail_coremask;
babba4f1 DD	317	const struct cvmx_bootmem_named_block_desc *block_desc;
773cb77d	318	struct boot_init_vector *boot_vect =
babba4f1	319	(struct boot_init_vector *)PHYS_TO_XKSEG_CACHED(BOOTLOADER_BOOT_VECTOR);
773cb77d RB	320
	321	block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
	322
	323	if (!block_desc) {
babba4f1 DD	324	struct linux_app_boot_info *labi;
	325
	326	labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
	327
	328	avail_coremask = labi->avail_coremask;
	329	labi->avail_coremask &= ~(1 << coreid);
773cb77d	330	} else { /* alternative, already initialized */
babba4f1 DD	331	avail_coremask = (uint32_t )PHYS_TO_XKSEG_CACHED(
babba4f1 DD	332	block_desc->base_addr + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
773cb77d RB	333	}
	334
	335	if (!(avail_coremask & (1 << coreid))) {
92a76f6d	336	/* core not available, assume, that caught by simple-executive */
773cb77d RB	337	cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
	338	cvmx_write_csr(CVMX_CIU_PP_RST, 0);
	339	}
	340
	341	boot_vect[coreid].app_start_func_addr =
	342	(uint32_t) (unsigned long) start_after_reset;
babba4f1	343	boot_vect[coreid].code_addr = octeon_bootloader_entry_addr;
773cb77d	344
babba4f1	345	mb();
773cb77d RB	346
	347	cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask);
	348
	349	return 0;
	350	}
	351
078a55fc	352	static int octeon_cpu_callback(struct notifier_block *nfb,
773cb77d RB	353	unsigned long action, void *hcpu)
	354	{
	355	unsigned int cpu = (unsigned long)hcpu;
	356
	357	switch (action) {
	358	case CPU_UP_PREPARE:
	359	octeon_update_boot_vector(cpu);
	360	break;
	361	case CPU_ONLINE:
	362	pr_info("Cpu %d online\n", cpu);
	363	break;
	364	case CPU_DEAD:
	365	break;
	366	}
	367
	368	return NOTIFY_OK;
	369	}
	370
078a55fc	371	static int register_cavium_notifier(void)
773cb77d	372	{
442f2012	373	hotcpu_notifier(octeon_cpu_callback, 0);
773cb77d RB	374	return 0;
773cb77d RB	375	}
773cb77d RB	376	late_initcall(register_cavium_notifier);
773cb77d RB	377
70342287	378	#endif /* CONFIG_HOTPLUG_CPU */
773cb77d	379
5b3b1688 DD	380	struct plat_smp_ops octeon_smp_ops = {
	381	.send_ipi_single = octeon_send_ipi_single,
	382	.send_ipi_mask = octeon_send_ipi_mask,
	383	.init_secondary = octeon_init_secondary,
	384	.smp_finish = octeon_smp_finish,
5b3b1688 DD	385	.boot_secondary = octeon_boot_secondary,
	386	.smp_setup = octeon_smp_setup,
	387	.prepare_cpus = octeon_prepare_cpus,
773cb77d RB	388	#ifdef CONFIG_HOTPLUG_CPU
	389	.cpu_disable = octeon_cpu_disable,
	390	.cpu_die = octeon_cpu_die,
	391	#endif
5b3b1688	392	};