[mirror_ubuntu-eoan-kernel.git] / arch / mips / cavium-octeon / smp.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
 */
#include <linux/cpu.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/smp.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/sched.h>
#include <linux/module.h>

#include <asm/mmu_context.h>
#include <asm/time.h>
#include <asm/setup.h>

#include <asm/octeon/octeon.h>

#include "octeon_boot.h"

volatile unsigned long octeon_processor_boot = 0xff;
volatile unsigned long octeon_processor_sp;
volatile unsigned long octeon_processor_gp;

#ifdef CONFIG_HOTPLUG_CPU
uint64_t octeon_bootloader_entry_addr;
EXPORT_SYMBOL(octeon_bootloader_entry_addr);
#endif

static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
{
	const int coreid = cvmx_get_core_num();
	uint64_t action;

	/* Load the mailbox register to figure out what we're supposed to do */
	action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(coreid)) & 0xffff;

	/* Clear the mailbox to clear the interrupt */
	cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), action);

	if (action & SMP_CALL_FUNCTION)
		smp_call_function_interrupt();
	if (action & SMP_RESCHEDULE_YOURSELF)
		scheduler_ipi();

	/* Check if we've been told to flush the icache */
	if (action & SMP_ICACHE_FLUSH)
		asm volatile ("synci 0($0)\n");
	return IRQ_HANDLED;
}

/**
 * Cause the function described by call_data to be executed on the passed
 * cpu.	 When the function has finished, increment the finished field of
 * call_data.
 */
void octeon_send_ipi_single(int cpu, unsigned int action)
{
	int coreid = cpu_logical_map(cpu);
	/*
	pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu,
	       coreid, action);
	*/
	cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action);
}

static inline void octeon_send_ipi_mask(const struct cpumask *mask,
					unsigned int action)
{
	unsigned int i;

	for_each_cpu_mask(i, *mask)
		octeon_send_ipi_single(i, action);
}

/**
 * Detect available CPUs, populate cpu_possible_mask
 */
static void octeon_smp_hotplug_setup(void)
{
#ifdef CONFIG_HOTPLUG_CPU
	struct linux_app_boot_info *labi;

	labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
	if (labi->labi_signature != LABI_SIGNATURE)
		panic("The bootloader version on this board is incorrect.");

	octeon_bootloader_entry_addr = labi->InitTLBStart_addr;
#endif
}

static void octeon_smp_setup(void)
{
	const int coreid = cvmx_get_core_num();
	int cpus;
	int id;
	int core_mask = octeon_get_boot_coremask();
#ifdef CONFIG_HOTPLUG_CPU
	unsigned int num_cores = cvmx_octeon_num_cores();
#endif

	/* The present CPUs are initially just the boot cpu (CPU 0). */
	for (id = 0; id < NR_CPUS; id++) {
		set_cpu_possible(id, id == 0);
		set_cpu_present(id, id == 0);
	}

	__cpu_number_map[coreid] = 0;
	__cpu_logical_map[0] = coreid;

	/* The present CPUs get the lowest CPU numbers. */
	cpus = 1;
	for (id = 0; id < NR_CPUS; id++) {
		if ((id != coreid) && (core_mask & (1 << id))) {
			set_cpu_possible(cpus, true);
			set_cpu_present(cpus, true);
			__cpu_number_map[id] = cpus;
			__cpu_logical_map[cpus] = id;
			cpus++;
		}
	}

#ifdef CONFIG_HOTPLUG_CPU
	/*
	 * The possible CPUs are all those present on the chip.	 We
	 * will assign CPU numbers for possible cores as well.	Cores
	 * are always consecutively numberd from 0.
	 */
	for (id = 0; id < num_cores && id < NR_CPUS; id++) {
		if (!(core_mask & (1 << id))) {
			set_cpu_possible(cpus, true);
			__cpu_number_map[id] = cpus;
			__cpu_logical_map[cpus] = id;
			cpus++;
		}
	}
#endif

	octeon_smp_hotplug_setup();
}

/**
 * Firmware CPU startup hook
 *
 */
static void octeon_boot_secondary(int cpu, struct task_struct *idle)
{
	int count;

	pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu,
		cpu_logical_map(cpu));

	octeon_processor_sp = __KSTK_TOS(idle);
	octeon_processor_gp = (unsigned long)(task_thread_info(idle));
	octeon_processor_boot = cpu_logical_map(cpu);
	mb();

	count = 10000;
	while (octeon_processor_sp && count) {
		/* Waiting for processor to get the SP and GP */
		udelay(1);
		count--;
	}
	if (count == 0)
		pr_err("Secondary boot timeout\n");
}

/**
 * After we've done initial boot, this function is called to allow the
 * board code to clean up state, if needed
 */
static void octeon_init_secondary(void)
{
	unsigned int sr;

	sr = set_c0_status(ST0_BEV);
	write_c0_ebase((u32)ebase);
	write_c0_status(sr);

	octeon_check_cpu_bist();
	octeon_init_cvmcount();

	octeon_irq_setup_secondary();
}

/**
 * Callout to firmware before smp_init
 *
 */
void octeon_prepare_cpus(unsigned int max_cpus)
{
#ifdef CONFIG_HOTPLUG_CPU
	struct linux_app_boot_info *labi;

	labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);

	if (labi->labi_signature != LABI_SIGNATURE)
		panic("The bootloader version on this board is incorrect.");
#endif
	/*
	 * Only the low order mailbox bits are used for IPIs, leave
	 * the other bits alone.
	 */
	cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff);
	if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt,
			IRQF_PERCPU | IRQF_NO_THREAD, "SMP-IPI",
			mailbox_interrupt)) {
		panic("Cannot request_irq(OCTEON_IRQ_MBOX0)");
	}
}

/**
 * Last chance for the board code to finish SMP initialization before
 * the CPU is "online".
 */
static void octeon_smp_finish(void)
{
#ifdef CONFIG_CAVIUM_GDB
	unsigned long tmp;
	/* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also set the MCD0
	   to be not masked by this core so we know the signal is received by
	   someone */
	asm volatile ("dmfc0 %0, $22\n"
		      "ori   %0, %0, 0x9100\n" "dmtc0 %0, $22\n" : "=r" (tmp));
#endif

	octeon_user_io_init();

	/* to generate the first CPU timer interrupt */
	write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
	local_irq_enable();
}

/**
 * Hook for after all CPUs are online
 */
static void octeon_cpus_done(void)
{
#ifdef CONFIG_CAVIUM_GDB
	unsigned long tmp;
	/* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also set the MCD0
	   to be not masked by this core so we know the signal is received by
	   someone */
	asm volatile ("dmfc0 %0, $22\n"
		      "ori   %0, %0, 0x9100\n" "dmtc0 %0, $22\n" : "=r" (tmp));
#endif
}

#ifdef CONFIG_HOTPLUG_CPU

/* State of each CPU. */
DEFINE_PER_CPU(int, cpu_state);

static int octeon_cpu_disable(void)
{
	unsigned int cpu = smp_processor_id();

	if (cpu == 0)
		return -EBUSY;

	set_cpu_online(cpu, false);
	cpu_clear(cpu, cpu_callin_map);
	local_irq_disable();
	octeon_fixup_irqs();
	local_irq_enable();

	flush_cache_all();
	local_flush_tlb_all();

	return 0;
}

static void octeon_cpu_die(unsigned int cpu)
{
	int coreid = cpu_logical_map(cpu);
	uint32_t mask, new_mask;
	const struct cvmx_bootmem_named_block_desc *block_desc;

	while (per_cpu(cpu_state, cpu) != CPU_DEAD)
		cpu_relax();

	/*
	 * This is a bit complicated strategics of getting/settig available
	 * cores mask, copied from bootloader
	 */

	mask = 1 << coreid;
	/* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */
	block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);

	if (!block_desc) {
		struct linux_app_boot_info *labi;

		labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);

		labi->avail_coremask |= mask;
		new_mask = labi->avail_coremask;
	} else {		       /* alternative, already initialized */
		uint32_t *p = (uint32_t *)PHYS_TO_XKSEG_CACHED(block_desc->base_addr +
							       AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
		*p |= mask;
		new_mask = *p;
	}

	pr_info("Reset core %d. Available Coremask = 0x%x \n", coreid, new_mask);
	mb();
	cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
	cvmx_write_csr(CVMX_CIU_PP_RST, 0);
}

void play_dead(void)
{
	int cpu = cpu_number_map(cvmx_get_core_num());

	idle_task_exit();
	octeon_processor_boot = 0xff;
	per_cpu(cpu_state, cpu) = CPU_DEAD;

	mb();

	while (1)	/* core will be reset here */
		;
}

extern void kernel_entry(unsigned long arg1, ...);

static void start_after_reset(void)
{
	kernel_entry(0, 0, 0);	/* set a2 = 0 for secondary core */
}

static int octeon_update_boot_vector(unsigned int cpu)
{

	int coreid = cpu_logical_map(cpu);
	uint32_t avail_coremask;
	const struct cvmx_bootmem_named_block_desc *block_desc;
	struct boot_init_vector *boot_vect =
		(struct boot_init_vector *)PHYS_TO_XKSEG_CACHED(BOOTLOADER_BOOT_VECTOR);

	block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);

	if (!block_desc) {
		struct linux_app_boot_info *labi;

		labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);

		avail_coremask = labi->avail_coremask;
		labi->avail_coremask &= ~(1 << coreid);
	} else {		       /* alternative, already initialized */
		avail_coremask = *(uint32_t *)PHYS_TO_XKSEG_CACHED(
			block_desc->base_addr + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
	}

	if (!(avail_coremask & (1 << coreid))) {
		/* core not available, assume, that catched by simple-executive */
		cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
		cvmx_write_csr(CVMX_CIU_PP_RST, 0);
	}

	boot_vect[coreid].app_start_func_addr =
		(uint32_t) (unsigned long) start_after_reset;
	boot_vect[coreid].code_addr = octeon_bootloader_entry_addr;

	mb();

	cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask);

	return 0;
}

static int octeon_cpu_callback(struct notifier_block *nfb,
	unsigned long action, void *hcpu)
{
	unsigned int cpu = (unsigned long)hcpu;

	switch (action) {
	case CPU_UP_PREPARE:
		octeon_update_boot_vector(cpu);
		break;
	case CPU_ONLINE:
		pr_info("Cpu %d online\n", cpu);
		break;
	case CPU_DEAD:
		break;
	}

	return NOTIFY_OK;
}

static int register_cavium_notifier(void)
{
	hotcpu_notifier(octeon_cpu_callback, 0);
	return 0;
}
late_initcall(register_cavium_notifier);

#endif	/* CONFIG_HOTPLUG_CPU */

struct plat_smp_ops octeon_smp_ops = {
	.send_ipi_single	= octeon_send_ipi_single,
	.send_ipi_mask		= octeon_send_ipi_mask,
	.init_secondary		= octeon_init_secondary,
	.smp_finish		= octeon_smp_finish,
	.cpus_done		= octeon_cpus_done,
	.boot_secondary		= octeon_boot_secondary,
	.smp_setup		= octeon_smp_setup,
	.prepare_cpus		= octeon_prepare_cpus,
#ifdef CONFIG_HOTPLUG_CPU
	.cpu_disable		= octeon_cpu_disable,
	.cpu_die		= octeon_cpu_die,
#endif
};
Commit	Line	Data
5b3b1688 DD	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
edfcbb8c	6	* Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
5b3b1688	7	*/
773cb77d	8	#include <linux/cpu.h>
5b3b1688 DD	9	#include <linux/init.h>
	10	#include <linux/delay.h>
	11	#include <linux/smp.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/kernel_stat.h>
	14	#include <linux/sched.h>
	15	#include <linux/module.h>
	16
	17	#include <asm/mmu_context.h>
5b3b1688	18	#include <asm/time.h>
b81947c6	19	#include <asm/setup.h>
5b3b1688 DD	20
	21	#include <asm/octeon/octeon.h>
	22
773cb77d RB	23	#include "octeon_boot.h"
773cb77d RB	24
5b3b1688 DD	25	volatile unsigned long octeon_processor_boot = 0xff;
	26	volatile unsigned long octeon_processor_sp;
	27	volatile unsigned long octeon_processor_gp;
	28
773cb77d	29	#ifdef CONFIG_HOTPLUG_CPU
babba4f1 DD	30	uint64_t octeon_bootloader_entry_addr;
babba4f1 DD	31	EXPORT_SYMBOL(octeon_bootloader_entry_addr);
773cb77d RB	32	#endif
773cb77d RB	33
5b3b1688 DD	34	static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
	35	{
	36	const int coreid = cvmx_get_core_num();
	37	uint64_t action;
	38
	39	/* Load the mailbox register to figure out what we're supposed to do */
e650ce0f	40	action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(coreid)) & 0xffff;
5b3b1688 DD	41
	42	/* Clear the mailbox to clear the interrupt */
	43	cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), action);
	44
	45	if (action & SMP_CALL_FUNCTION)
	46	smp_call_function_interrupt();
184748cc PZ	47	if (action & SMP_RESCHEDULE_YOURSELF)
184748cc PZ	48	scheduler_ipi();
5b3b1688 DD	49
	50	/* Check if we've been told to flush the icache */
	51	if (action & SMP_ICACHE_FLUSH)
	52	asm volatile ("synci 0($0)\n");
	53	return IRQ_HANDLED;
	54	}
	55
	56	/**
	57	* Cause the function described by call_data to be executed on the passed
70342287	58	* cpu. When the function has finished, increment the finished field of
5b3b1688 DD	59	* call_data.
	60	*/
	61	void octeon_send_ipi_single(int cpu, unsigned int action)
	62	{
	63	int coreid = cpu_logical_map(cpu);
	64	/*
	65	pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu,
	66	coreid, action);
	67	*/
	68	cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action);
	69	}
	70
067f3290 DD	71	static inline void octeon_send_ipi_mask(const struct cpumask *mask,
067f3290 DD	72	unsigned int action)
5b3b1688 DD	73	{
	74	unsigned int i;
	75
067f3290	76	for_each_cpu_mask(i, *mask)
5b3b1688 DD	77	octeon_send_ipi_single(i, action);
	78	}
	79
	80	/**
5f054e31	81	* Detect available CPUs, populate cpu_possible_mask
5b3b1688	82	*/
773cb77d RB	83	static void octeon_smp_hotplug_setup(void)
	84	{
	85	#ifdef CONFIG_HOTPLUG_CPU
babba4f1 DD	86	struct linux_app_boot_info *labi;
	87
	88	labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
	89	if (labi->labi_signature != LABI_SIGNATURE)
	90	panic("The bootloader version on this board is incorrect.");
	91
	92	octeon_bootloader_entry_addr = labi->InitTLBStart_addr;
773cb77d RB	93	#endif
	94	}
	95
5b3b1688 DD	96	static void octeon_smp_setup(void)
	97	{
	98	const int coreid = cvmx_get_core_num();
	99	int cpus;
	100	int id;
5b3b1688	101	int core_mask = octeon_get_boot_coremask();
edfcbb8c DD	102	#ifdef CONFIG_HOTPLUG_CPU
	103	unsigned int num_cores = cvmx_octeon_num_cores();
	104	#endif
	105
	106	/* The present CPUs are initially just the boot cpu (CPU 0). */
	107	for (id = 0; id < NR_CPUS; id++) {
	108	set_cpu_possible(id, id == 0);
	109	set_cpu_present(id, id == 0);
	110	}
5b3b1688	111
5b3b1688 DD	112	__cpu_number_map[coreid] = 0;
5b3b1688 DD	113	__cpu_logical_map[0] = coreid;
5b3b1688	114
edfcbb8c	115	/* The present CPUs get the lowest CPU numbers. */
5b3b1688	116	cpus = 1;
edfcbb8c	117	for (id = 0; id < NR_CPUS; id++) {
5b3b1688	118	if ((id != coreid) && (core_mask & (1 << id))) {
edfcbb8c DD	119	set_cpu_possible(cpus, true);
	120	set_cpu_present(cpus, true);
	121	__cpu_number_map[id] = cpus;
	122	__cpu_logical_map[cpus] = id;
	123	cpus++;
	124	}
	125	}
	126
	127	#ifdef CONFIG_HOTPLUG_CPU
	128	/*
70342287 RB	129	* The possible CPUs are all those present on the chip. We
70342287 RB	130	* will assign CPU numbers for possible cores as well. Cores
edfcbb8c DD	131	* are always consecutively numberd from 0.
	132	*/
	133	for (id = 0; id < num_cores && id < NR_CPUS; id++) {
	134	if (!(core_mask & (1 << id))) {
	135	set_cpu_possible(cpus, true);
5b3b1688 DD	136	__cpu_number_map[id] = cpus;
	137	__cpu_logical_map[cpus] = id;
	138	cpus++;
	139	}
	140	}
edfcbb8c	141	#endif
773cb77d RB	142
773cb77d RB	143	octeon_smp_hotplug_setup();
5b3b1688 DD	144	}
	145
	146	/**
	147	* Firmware CPU startup hook
	148	*
	149	*/
	150	static void octeon_boot_secondary(int cpu, struct task_struct *idle)
	151	{
	152	int count;
	153
	154	pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu,
	155	cpu_logical_map(cpu));
	156
	157	octeon_processor_sp = __KSTK_TOS(idle);
	158	octeon_processor_gp = (unsigned long)(task_thread_info(idle));
	159	octeon_processor_boot = cpu_logical_map(cpu);
	160	mb();
	161
	162	count = 10000;
	163	while (octeon_processor_sp && count) {
	164	/* Waiting for processor to get the SP and GP */
	165	udelay(1);
	166	count--;
	167	}
	168	if (count == 0)
	169	pr_err("Secondary boot timeout\n");
	170	}
	171
	172	/**
	173	* After we've done initial boot, this function is called to allow the
	174	* board code to clean up state, if needed
	175	*/
078a55fc	176	static void octeon_init_secondary(void)
5b3b1688	177	{
babba4f1	178	unsigned int sr;
5b3b1688	179
babba4f1 DD	180	sr = set_c0_status(ST0_BEV);
	181	write_c0_ebase((u32)ebase);
	182	write_c0_status(sr);
	183
5b3b1688 DD	184	octeon_check_cpu_bist();
5b3b1688 DD	185	octeon_init_cvmcount();
0c326387 DD	186
0c326387 DD	187	octeon_irq_setup_secondary();
5b3b1688 DD	188	}
	189
	190	/**
	191	* Callout to firmware before smp_init
	192	*
	193	*/
	194	void octeon_prepare_cpus(unsigned int max_cpus)
	195	{
0c326387 DD	196	#ifdef CONFIG_HOTPLUG_CPU
	197	struct linux_app_boot_info *labi;
	198
	199	labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
	200
	201	if (labi->labi_signature != LABI_SIGNATURE)
	202	panic("The bootloader version on this board is incorrect.");
	203	#endif
e650ce0f DD	204	/*
	205	* Only the low order mailbox bits are used for IPIs, leave
	206	* the other bits alone.
	207	*/
	208	cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff);
e63fb7a9 VS	209	if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt,
	210	IRQF_PERCPU \| IRQF_NO_THREAD, "SMP-IPI",
	211	mailbox_interrupt)) {
ab75dc02	212	panic("Cannot request_irq(OCTEON_IRQ_MBOX0)");
5b3b1688	213	}
5b3b1688 DD	214	}
	215
	216	/**
	217	* Last chance for the board code to finish SMP initialization before
	218	* the CPU is "online".
	219	*/
	220	static void octeon_smp_finish(void)
	221	{
	222	#ifdef CONFIG_CAVIUM_GDB
	223	unsigned long tmp;
	224	/* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also set the MCD0
	225	to be not masked by this core so we know the signal is received by
	226	someone */
	227	asm volatile ("dmfc0 %0, $22\n"
	228	"ori %0, %0, 0x9100\n" "dmtc0 %0, $22\n" : "=r" (tmp));
	229	#endif
	230
	231	octeon_user_io_init();
	232
	233	/* to generate the first CPU timer interrupt */
	234	write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
1bcfecc0	235	local_irq_enable();
5b3b1688 DD	236	}
	237
	238	/**
	239	* Hook for after all CPUs are online
	240	*/
	241	static void octeon_cpus_done(void)
	242	{
	243	#ifdef CONFIG_CAVIUM_GDB
	244	unsigned long tmp;
	245	/* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also set the MCD0
	246	to be not masked by this core so we know the signal is received by
	247	someone */
	248	asm volatile ("dmfc0 %0, $22\n"
	249	"ori %0, %0, 0x9100\n" "dmtc0 %0, $22\n" : "=r" (tmp));
	250	#endif
	251	}
	252
773cb77d RB	253	#ifdef CONFIG_HOTPLUG_CPU
	254
	255	/* State of each CPU. */
	256	DEFINE_PER_CPU(int, cpu_state);
	257
773cb77d RB	258	static int octeon_cpu_disable(void)
	259	{
	260	unsigned int cpu = smp_processor_id();
	261
	262	if (cpu == 0)
	263	return -EBUSY;
	264
0b5f9c00	265	set_cpu_online(cpu, false);
773cb77d RB	266	cpu_clear(cpu, cpu_callin_map);
773cb77d RB	267	local_irq_disable();
17efb59a	268	octeon_fixup_irqs();
773cb77d RB	269	local_irq_enable();
	270
	271	flush_cache_all();
	272	local_flush_tlb_all();
	273
773cb77d RB	274	return 0;
	275	}
	276
	277	static void octeon_cpu_die(unsigned int cpu)
	278	{
	279	int coreid = cpu_logical_map(cpu);
babba4f1 DD	280	uint32_t mask, new_mask;
babba4f1 DD	281	const struct cvmx_bootmem_named_block_desc *block_desc;
773cb77d	282
773cb77d RB	283	while (per_cpu(cpu_state, cpu) != CPU_DEAD)
	284	cpu_relax();
	285
	286	/*
	287	* This is a bit complicated strategics of getting/settig available
	288	* cores mask, copied from bootloader
	289	*/
babba4f1 DD	290
babba4f1 DD	291	mask = 1 << coreid;
773cb77d RB	292	/* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */
	293	block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
	294
	295	if (!block_desc) {
babba4f1	296	struct linux_app_boot_info *labi;
773cb77d	297
babba4f1	298	labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
773cb77d	299
babba4f1 DD	300	labi->avail_coremask \|= mask;
	301	new_mask = labi->avail_coremask;
	302	} else { /* alternative, already initialized */
	303	uint32_t p = (uint32_t )PHYS_TO_XKSEG_CACHED(block_desc->base_addr +
	304	AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
	305	*p \|= mask;
	306	new_mask = *p;
773cb77d RB	307	}
773cb77d RB	308
babba4f1 DD	309	pr_info("Reset core %d. Available Coremask = 0x%x \n", coreid, new_mask);
babba4f1 DD	310	mb();
773cb77d RB	311	cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
	312	cvmx_write_csr(CVMX_CIU_PP_RST, 0);
	313	}
	314
	315	void play_dead(void)
	316	{
babba4f1	317	int cpu = cpu_number_map(cvmx_get_core_num());
773cb77d RB	318
	319	idle_task_exit();
	320	octeon_processor_boot = 0xff;
babba4f1 DD	321	per_cpu(cpu_state, cpu) = CPU_DEAD;
	322
	323	mb();
773cb77d RB	324
	325	while (1) /* core will be reset here */
	326	;
	327	}
	328
	329	extern void kernel_entry(unsigned long arg1, ...);
	330
	331	static void start_after_reset(void)
	332	{
70342287	333	kernel_entry(0, 0, 0); /* set a2 = 0 for secondary core */
773cb77d RB	334	}
773cb77d RB	335
babba4f1	336	static int octeon_update_boot_vector(unsigned int cpu)
773cb77d RB	337	{
	338
	339	int coreid = cpu_logical_map(cpu);
babba4f1 DD	340	uint32_t avail_coremask;
babba4f1 DD	341	const struct cvmx_bootmem_named_block_desc *block_desc;
773cb77d	342	struct boot_init_vector *boot_vect =
babba4f1	343	(struct boot_init_vector *)PHYS_TO_XKSEG_CACHED(BOOTLOADER_BOOT_VECTOR);
773cb77d RB	344
	345	block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
	346
	347	if (!block_desc) {
babba4f1 DD	348	struct linux_app_boot_info *labi;
	349
	350	labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
	351
	352	avail_coremask = labi->avail_coremask;
	353	labi->avail_coremask &= ~(1 << coreid);
773cb77d	354	} else { /* alternative, already initialized */
babba4f1 DD	355	avail_coremask = (uint32_t )PHYS_TO_XKSEG_CACHED(
babba4f1 DD	356	block_desc->base_addr + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
773cb77d RB	357	}
	358
	359	if (!(avail_coremask & (1 << coreid))) {
	360	/* core not available, assume, that catched by simple-executive */
	361	cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
	362	cvmx_write_csr(CVMX_CIU_PP_RST, 0);
	363	}
	364
	365	boot_vect[coreid].app_start_func_addr =
	366	(uint32_t) (unsigned long) start_after_reset;
babba4f1	367	boot_vect[coreid].code_addr = octeon_bootloader_entry_addr;
773cb77d	368
babba4f1	369	mb();
773cb77d RB	370
	371	cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask);
	372
	373	return 0;
	374	}
	375
078a55fc	376	static int octeon_cpu_callback(struct notifier_block *nfb,
773cb77d RB	377	unsigned long action, void *hcpu)
	378	{
	379	unsigned int cpu = (unsigned long)hcpu;
	380
	381	switch (action) {
	382	case CPU_UP_PREPARE:
	383	octeon_update_boot_vector(cpu);
	384	break;
	385	case CPU_ONLINE:
	386	pr_info("Cpu %d online\n", cpu);
	387	break;
	388	case CPU_DEAD:
	389	break;
	390	}
	391
	392	return NOTIFY_OK;
	393	}
	394
078a55fc	395	static int register_cavium_notifier(void)
773cb77d	396	{
442f2012	397	hotcpu_notifier(octeon_cpu_callback, 0);
773cb77d RB	398	return 0;
773cb77d RB	399	}
773cb77d RB	400	late_initcall(register_cavium_notifier);
773cb77d RB	401
70342287	402	#endif /* CONFIG_HOTPLUG_CPU */
773cb77d	403
5b3b1688 DD	404	struct plat_smp_ops octeon_smp_ops = {
	405	.send_ipi_single = octeon_send_ipi_single,
	406	.send_ipi_mask = octeon_send_ipi_mask,
	407	.init_secondary = octeon_init_secondary,
	408	.smp_finish = octeon_smp_finish,
	409	.cpus_done = octeon_cpus_done,
	410	.boot_secondary = octeon_boot_secondary,
	411	.smp_setup = octeon_smp_setup,
	412	.prepare_cpus = octeon_prepare_cpus,
773cb77d RB	413	#ifdef CONFIG_HOTPLUG_CPU
	414	.cpu_disable = octeon_cpu_disable,
	415	.cpu_die = octeon_cpu_die,
	416	#endif
5b3b1688	417	};