[mirror_ubuntu-artful-kernel.git] / arch / mips / cavium-octeon / smp.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
 */
#include <linux/cpu.h>
#include <linux/delay.h>
#include <linux/smp.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/sched.h>
#include <linux/sched/hotplug.h>
#include <linux/sched/task_stack.h>
#include <linux/init.h>
#include <linux/export.h>

#include <asm/mmu_context.h>
#include <asm/time.h>
#include <asm/setup.h>

#include <asm/octeon/octeon.h>

#include "octeon_boot.h"

volatile unsigned long octeon_processor_boot = 0xff;
volatile unsigned long octeon_processor_sp;
volatile unsigned long octeon_processor_gp;
#ifdef CONFIG_RELOCATABLE
volatile unsigned long octeon_processor_relocated_kernel_entry;
#endif /* CONFIG_RELOCATABLE */

#ifdef CONFIG_HOTPLUG_CPU
uint64_t octeon_bootloader_entry_addr;
EXPORT_SYMBOL(octeon_bootloader_entry_addr);
#endif

extern void kernel_entry(unsigned long arg1, ...);

static void octeon_icache_flush(void)
{
	asm volatile ("synci 0($0)\n");
}

static void (*octeon_message_functions[8])(void) = {
	scheduler_ipi,
	generic_smp_call_function_interrupt,
	octeon_icache_flush,
};

static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
{
	u64 mbox_clrx = CVMX_CIU_MBOX_CLRX(cvmx_get_core_num());
	u64 action;
	int i;

	/*
	 * Make sure the function array initialization remains
	 * correct.
	 */
	BUILD_BUG_ON(SMP_RESCHEDULE_YOURSELF != (1 << 0));
	BUILD_BUG_ON(SMP_CALL_FUNCTION       != (1 << 1));
	BUILD_BUG_ON(SMP_ICACHE_FLUSH        != (1 << 2));

	/*
	 * Load the mailbox register to figure out what we're supposed
	 * to do.
	 */
	action = cvmx_read_csr(mbox_clrx);

	if (OCTEON_IS_MODEL(OCTEON_CN68XX))
		action &= 0xff;
	else
		action &= 0xffff;

	/* Clear the mailbox to clear the interrupt */
	cvmx_write_csr(mbox_clrx, action);

	for (i = 0; i < ARRAY_SIZE(octeon_message_functions) && action;) {
		if (action & 1) {
			void (*fn)(void) = octeon_message_functions[i];

			if (fn)
				fn();
		}
		action >>= 1;
		i++;
	}
	return IRQ_HANDLED;
}

/**
 * Cause the function described by call_data to be executed on the passed
 * cpu.	 When the function has finished, increment the finished field of
 * call_data.
 */
void octeon_send_ipi_single(int cpu, unsigned int action)
{
	int coreid = cpu_logical_map(cpu);
	/*
	pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu,
	       coreid, action);
	*/
	cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action);
}

static inline void octeon_send_ipi_mask(const struct cpumask *mask,
					unsigned int action)
{
	unsigned int i;

	for_each_cpu(i, mask)
		octeon_send_ipi_single(i, action);
}

/**
 * Detect available CPUs, populate cpu_possible_mask
 */
static void octeon_smp_hotplug_setup(void)
{
#ifdef CONFIG_HOTPLUG_CPU
	struct linux_app_boot_info *labi;

	if (!setup_max_cpus)
		return;

	labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
	if (labi->labi_signature != LABI_SIGNATURE) {
		pr_info("The bootloader on this board does not support HOTPLUG_CPU.");
		return;
	}

	octeon_bootloader_entry_addr = labi->InitTLBStart_addr;
#endif
}

static void __init octeon_smp_setup(void)
{
	const int coreid = cvmx_get_core_num();
	int cpus;
	int id;
	struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get();

#ifdef CONFIG_HOTPLUG_CPU
	int core_mask = octeon_get_boot_coremask();
	unsigned int num_cores = cvmx_octeon_num_cores();
#endif

	/* The present CPUs are initially just the boot cpu (CPU 0). */
	for (id = 0; id < NR_CPUS; id++) {
		set_cpu_possible(id, id == 0);
		set_cpu_present(id, id == 0);
	}

	__cpu_number_map[coreid] = 0;
	__cpu_logical_map[0] = coreid;

	/* The present CPUs get the lowest CPU numbers. */
	cpus = 1;
	for (id = 0; id < NR_CPUS; id++) {
		if ((id != coreid) && cvmx_coremask_is_core_set(&sysinfo->core_mask, id)) {
			set_cpu_possible(cpus, true);
			set_cpu_present(cpus, true);
			__cpu_number_map[id] = cpus;
			__cpu_logical_map[cpus] = id;
			cpus++;
		}
	}

#ifdef CONFIG_HOTPLUG_CPU
	/*
	 * The possible CPUs are all those present on the chip.	 We
	 * will assign CPU numbers for possible cores as well.	Cores
	 * are always consecutively numberd from 0.
	 */
	for (id = 0; setup_max_cpus && octeon_bootloader_entry_addr &&
		     id < num_cores && id < NR_CPUS; id++) {
		if (!(core_mask & (1 << id))) {
			set_cpu_possible(cpus, true);
			__cpu_number_map[id] = cpus;
			__cpu_logical_map[cpus] = id;
			cpus++;
		}
	}
#endif

	octeon_smp_hotplug_setup();
}


#ifdef CONFIG_RELOCATABLE
int plat_post_relocation(long offset)
{
	unsigned long entry = (unsigned long)kernel_entry;

	/* Send secondaries into relocated kernel */
	octeon_processor_relocated_kernel_entry = entry + offset;

	return 0;
}
#endif /* CONFIG_RELOCATABLE */

/**
 * Firmware CPU startup hook
 *
 */
static void octeon_boot_secondary(int cpu, struct task_struct *idle)
{
	int count;

	pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu,
		cpu_logical_map(cpu));

	octeon_processor_sp = __KSTK_TOS(idle);
	octeon_processor_gp = (unsigned long)(task_thread_info(idle));
	octeon_processor_boot = cpu_logical_map(cpu);
	mb();

	count = 10000;
	while (octeon_processor_sp && count) {
		/* Waiting for processor to get the SP and GP */
		udelay(1);
		count--;
	}
	if (count == 0)
		pr_err("Secondary boot timeout\n");
}

/**
 * After we've done initial boot, this function is called to allow the
 * board code to clean up state, if needed
 */
static void octeon_init_secondary(void)
{
	unsigned int sr;

	sr = set_c0_status(ST0_BEV);
	write_c0_ebase((u32)ebase);
	write_c0_status(sr);

	octeon_check_cpu_bist();
	octeon_init_cvmcount();

	octeon_irq_setup_secondary();
}

/**
 * Callout to firmware before smp_init
 *
 */
static void __init octeon_prepare_cpus(unsigned int max_cpus)
{
	/*
	 * Only the low order mailbox bits are used for IPIs, leave
	 * the other bits alone.
	 */
	cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff);
	if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt,
			IRQF_PERCPU | IRQF_NO_THREAD, "SMP-IPI",
			mailbox_interrupt)) {
		panic("Cannot request_irq(OCTEON_IRQ_MBOX0)");
	}
}

/**
 * Last chance for the board code to finish SMP initialization before
 * the CPU is "online".
 */
static void octeon_smp_finish(void)
{
	octeon_user_io_init();

	/* to generate the first CPU timer interrupt */
	write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
	local_irq_enable();
}

#ifdef CONFIG_HOTPLUG_CPU

/* State of each CPU. */
DEFINE_PER_CPU(int, cpu_state);

static int octeon_cpu_disable(void)
{
	unsigned int cpu = smp_processor_id();

	if (cpu == 0)
		return -EBUSY;

	if (!octeon_bootloader_entry_addr)
		return -ENOTSUPP;

	set_cpu_online(cpu, false);
	calculate_cpu_foreign_map();
	octeon_fixup_irqs();

	__flush_cache_all();
	local_flush_tlb_all();

	return 0;
}

static void octeon_cpu_die(unsigned int cpu)
{
	int coreid = cpu_logical_map(cpu);
	uint32_t mask, new_mask;
	const struct cvmx_bootmem_named_block_desc *block_desc;

	while (per_cpu(cpu_state, cpu) != CPU_DEAD)
		cpu_relax();

	/*
	 * This is a bit complicated strategics of getting/settig available
	 * cores mask, copied from bootloader
	 */

	mask = 1 << coreid;
	/* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */
	block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);

	if (!block_desc) {
		struct linux_app_boot_info *labi;

		labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);

		labi->avail_coremask |= mask;
		new_mask = labi->avail_coremask;
	} else {		       /* alternative, already initialized */
		uint32_t *p = (uint32_t *)PHYS_TO_XKSEG_CACHED(block_desc->base_addr +
							       AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
		*p |= mask;
		new_mask = *p;
	}

	pr_info("Reset core %d. Available Coremask = 0x%x \n", coreid, new_mask);
	mb();
	cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
	cvmx_write_csr(CVMX_CIU_PP_RST, 0);
}

void play_dead(void)
{
	int cpu = cpu_number_map(cvmx_get_core_num());

	idle_task_exit();
	octeon_processor_boot = 0xff;
	per_cpu(cpu_state, cpu) = CPU_DEAD;

	mb();

	while (1)	/* core will be reset here */
		;
}

static void start_after_reset(void)
{
	kernel_entry(0, 0, 0);	/* set a2 = 0 for secondary core */
}

static int octeon_update_boot_vector(unsigned int cpu)
{

	int coreid = cpu_logical_map(cpu);
	uint32_t avail_coremask;
	const struct cvmx_bootmem_named_block_desc *block_desc;
	struct boot_init_vector *boot_vect =
		(struct boot_init_vector *)PHYS_TO_XKSEG_CACHED(BOOTLOADER_BOOT_VECTOR);

	block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);

	if (!block_desc) {
		struct linux_app_boot_info *labi;

		labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);

		avail_coremask = labi->avail_coremask;
		labi->avail_coremask &= ~(1 << coreid);
	} else {		       /* alternative, already initialized */
		avail_coremask = *(uint32_t *)PHYS_TO_XKSEG_CACHED(
			block_desc->base_addr + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
	}

	if (!(avail_coremask & (1 << coreid))) {
		/* core not available, assume, that caught by simple-executive */
		cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
		cvmx_write_csr(CVMX_CIU_PP_RST, 0);
	}

	boot_vect[coreid].app_start_func_addr =
		(uint32_t) (unsigned long) start_after_reset;
	boot_vect[coreid].code_addr = octeon_bootloader_entry_addr;

	mb();

	cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask);

	return 0;
}

static int register_cavium_notifier(void)
{
	return cpuhp_setup_state_nocalls(CPUHP_MIPS_SOC_PREPARE,
					 "mips/cavium:prepare",
					 octeon_update_boot_vector, NULL);
}
late_initcall(register_cavium_notifier);

#endif	/* CONFIG_HOTPLUG_CPU */

struct plat_smp_ops octeon_smp_ops = {
	.send_ipi_single	= octeon_send_ipi_single,
	.send_ipi_mask		= octeon_send_ipi_mask,
	.init_secondary		= octeon_init_secondary,
	.smp_finish		= octeon_smp_finish,
	.boot_secondary		= octeon_boot_secondary,
	.smp_setup		= octeon_smp_setup,
	.prepare_cpus		= octeon_prepare_cpus,
#ifdef CONFIG_HOTPLUG_CPU
	.cpu_disable		= octeon_cpu_disable,
	.cpu_die		= octeon_cpu_die,
#endif
};

static irqreturn_t octeon_78xx_reched_interrupt(int irq, void *dev_id)
{
	scheduler_ipi();
	return IRQ_HANDLED;
}

static irqreturn_t octeon_78xx_call_function_interrupt(int irq, void *dev_id)
{
	generic_smp_call_function_interrupt();
	return IRQ_HANDLED;
}

static irqreturn_t octeon_78xx_icache_flush_interrupt(int irq, void *dev_id)
{
	octeon_icache_flush();
	return IRQ_HANDLED;
}

/*
 * Callout to firmware before smp_init
 */
static void octeon_78xx_prepare_cpus(unsigned int max_cpus)
{
	if (request_irq(OCTEON_IRQ_MBOX0 + 0,
			octeon_78xx_reched_interrupt,
			IRQF_PERCPU | IRQF_NO_THREAD, "Scheduler",
			octeon_78xx_reched_interrupt)) {
		panic("Cannot request_irq for SchedulerIPI");
	}
	if (request_irq(OCTEON_IRQ_MBOX0 + 1,
			octeon_78xx_call_function_interrupt,
			IRQF_PERCPU | IRQF_NO_THREAD, "SMP-Call",
			octeon_78xx_call_function_interrupt)) {
		panic("Cannot request_irq for SMP-Call");
	}
	if (request_irq(OCTEON_IRQ_MBOX0 + 2,
			octeon_78xx_icache_flush_interrupt,
			IRQF_PERCPU | IRQF_NO_THREAD, "ICache-Flush",
			octeon_78xx_icache_flush_interrupt)) {
		panic("Cannot request_irq for ICache-Flush");
	}
}

static void octeon_78xx_send_ipi_single(int cpu, unsigned int action)
{
	int i;

	for (i = 0; i < 8; i++) {
		if (action & 1)
			octeon_ciu3_mbox_send(cpu, i);
		action >>= 1;
	}
}

static void octeon_78xx_send_ipi_mask(const struct cpumask *mask,
				      unsigned int action)
{
	unsigned int cpu;

	for_each_cpu(cpu, mask)
		octeon_78xx_send_ipi_single(cpu, action);
}

static struct plat_smp_ops octeon_78xx_smp_ops = {
	.send_ipi_single	= octeon_78xx_send_ipi_single,
	.send_ipi_mask		= octeon_78xx_send_ipi_mask,
	.init_secondary		= octeon_init_secondary,
	.smp_finish		= octeon_smp_finish,
	.boot_secondary		= octeon_boot_secondary,
	.smp_setup		= octeon_smp_setup,
	.prepare_cpus		= octeon_78xx_prepare_cpus,
#ifdef CONFIG_HOTPLUG_CPU
	.cpu_disable		= octeon_cpu_disable,
	.cpu_die		= octeon_cpu_die,
#endif
};

void __init octeon_setup_smp(void)
{
	struct plat_smp_ops *ops;

	if (octeon_has_feature(OCTEON_FEATURE_CIU3))
		ops = &octeon_78xx_smp_ops;
	else
		ops = &octeon_smp_ops;

	register_smp_ops(ops);
}
Commit	Line	Data
5b3b1688 DD	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
edfcbb8c	6	* Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
5b3b1688	7	*/
773cb77d	8	#include <linux/cpu.h>
5b3b1688 DD	9	#include <linux/delay.h>
	10	#include <linux/smp.h>
	11	#include <linux/interrupt.h>
	12	#include <linux/kernel_stat.h>
	13	#include <linux/sched.h>
ef8bd77f	14	#include <linux/sched/hotplug.h>
fc69910f	15	#include <linux/sched/task_stack.h>
26dd3e4f PG	16	#include <linux/init.h>
26dd3e4f PG	17	#include <linux/export.h>
5b3b1688 DD	18
5b3b1688 DD	19	#include <asm/mmu_context.h>
5b3b1688	20	#include <asm/time.h>
b81947c6	21	#include <asm/setup.h>
5b3b1688 DD	22
	23	#include <asm/octeon/octeon.h>
	24
773cb77d RB	25	#include "octeon_boot.h"
773cb77d RB	26
5b3b1688 DD	27	volatile unsigned long octeon_processor_boot = 0xff;
	28	volatile unsigned long octeon_processor_sp;
	29	volatile unsigned long octeon_processor_gp;
3ff72be4 SH	30	#ifdef CONFIG_RELOCATABLE
	31	volatile unsigned long octeon_processor_relocated_kernel_entry;
	32	#endif /* CONFIG_RELOCATABLE */
5b3b1688	33
773cb77d	34	#ifdef CONFIG_HOTPLUG_CPU
babba4f1 DD	35	uint64_t octeon_bootloader_entry_addr;
babba4f1 DD	36	EXPORT_SYMBOL(octeon_bootloader_entry_addr);
773cb77d RB	37	#endif
773cb77d RB	38
3ff72be4 SH	39	extern void kernel_entry(unsigned long arg1, ...);
3ff72be4 SH	40
c6d2b22e DD	41	static void octeon_icache_flush(void)
	42	{
	43	asm volatile ("synci 0($0)\n");
	44	}
	45
	46	static void (*octeon_message_functions[8])(void) = {
	47	scheduler_ipi,
	48	generic_smp_call_function_interrupt,
	49	octeon_icache_flush,
	50	};
	51
5b3b1688 DD	52	static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
5b3b1688 DD	53	{
c6d2b22e DD	54	u64 mbox_clrx = CVMX_CIU_MBOX_CLRX(cvmx_get_core_num());
	55	u64 action;
	56	int i;
	57
	58	/*
	59	* Make sure the function array initialization remains
	60	* correct.
	61	*/
	62	BUILD_BUG_ON(SMP_RESCHEDULE_YOURSELF != (1 << 0));
	63	BUILD_BUG_ON(SMP_CALL_FUNCTION != (1 << 1));
	64	BUILD_BUG_ON(SMP_ICACHE_FLUSH != (1 << 2));
	65
	66	/*
	67	* Load the mailbox register to figure out what we're supposed
	68	* to do.
	69	*/
	70	action = cvmx_read_csr(mbox_clrx);
5b3b1688	71
c6d2b22e DD	72	if (OCTEON_IS_MODEL(OCTEON_CN68XX))
	73	action &= 0xff;
	74	else
	75	action &= 0xffff;
5b3b1688 DD	76
5b3b1688 DD	77	/* Clear the mailbox to clear the interrupt */
c6d2b22e	78	cvmx_write_csr(mbox_clrx, action);
5b3b1688	79
c6d2b22e DD	80	for (i = 0; i < ARRAY_SIZE(octeon_message_functions) && action;) {
	81	if (action & 1) {
	82	void (*fn)(void) = octeon_message_functions[i];
5b3b1688	83
c6d2b22e DD	84	if (fn)
	85	fn();
	86	}
	87	action >>= 1;
	88	i++;
	89	}
5b3b1688 DD	90	return IRQ_HANDLED;
	91	}
	92
	93	/**
	94	* Cause the function described by call_data to be executed on the passed
70342287	95	* cpu. When the function has finished, increment the finished field of
5b3b1688 DD	96	* call_data.
	97	*/
	98	void octeon_send_ipi_single(int cpu, unsigned int action)
	99	{
	100	int coreid = cpu_logical_map(cpu);
	101	/*
	102	pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu,
	103	coreid, action);
	104	*/
	105	cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action);
	106	}
	107
067f3290 DD	108	static inline void octeon_send_ipi_mask(const struct cpumask *mask,
067f3290 DD	109	unsigned int action)
5b3b1688 DD	110	{
	111	unsigned int i;
	112
8dd92891	113	for_each_cpu(i, mask)
5b3b1688 DD	114	octeon_send_ipi_single(i, action);
	115	}
	116
	117	/**
5f054e31	118	* Detect available CPUs, populate cpu_possible_mask
5b3b1688	119	*/
773cb77d RB	120	static void octeon_smp_hotplug_setup(void)
	121	{
	122	#ifdef CONFIG_HOTPLUG_CPU
babba4f1 DD	123	struct linux_app_boot_info *labi;
babba4f1 DD	124
5ca0e377 AK	125	if (!setup_max_cpus)
	126	return;
	127
babba4f1	128	labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
eac44d9c AK	129	if (labi->labi_signature != LABI_SIGNATURE) {
	130	pr_info("The bootloader on this board does not support HOTPLUG_CPU.");
	131	return;
	132	}
babba4f1 DD	133
babba4f1 DD	134	octeon_bootloader_entry_addr = labi->InitTLBStart_addr;
773cb77d RB	135	#endif
	136	}
	137
0e8c1a32	138	static void __init octeon_smp_setup(void)
5b3b1688 DD	139	{
	140	const int coreid = cvmx_get_core_num();
	141	int cpus;
	142	int id;
7d52ab16 DD	143	struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get();
7d52ab16 DD	144
edfcbb8c	145	#ifdef CONFIG_HOTPLUG_CPU
c6d2b22e	146	int core_mask = octeon_get_boot_coremask();
edfcbb8c DD	147	unsigned int num_cores = cvmx_octeon_num_cores();
	148	#endif
	149
	150	/* The present CPUs are initially just the boot cpu (CPU 0). */
	151	for (id = 0; id < NR_CPUS; id++) {
	152	set_cpu_possible(id, id == 0);
	153	set_cpu_present(id, id == 0);
	154	}
5b3b1688	155
5b3b1688 DD	156	__cpu_number_map[coreid] = 0;
5b3b1688 DD	157	__cpu_logical_map[0] = coreid;
5b3b1688	158
edfcbb8c	159	/* The present CPUs get the lowest CPU numbers. */
5b3b1688	160	cpus = 1;
edfcbb8c	161	for (id = 0; id < NR_CPUS; id++) {
7d52ab16	162	if ((id != coreid) && cvmx_coremask_is_core_set(&sysinfo->core_mask, id)) {
edfcbb8c DD	163	set_cpu_possible(cpus, true);
	164	set_cpu_present(cpus, true);
	165	__cpu_number_map[id] = cpus;
	166	__cpu_logical_map[cpus] = id;
	167	cpus++;
	168	}
	169	}
	170
	171	#ifdef CONFIG_HOTPLUG_CPU
	172	/*
70342287 RB	173	* The possible CPUs are all those present on the chip. We
70342287 RB	174	* will assign CPU numbers for possible cores as well. Cores
edfcbb8c DD	175	* are always consecutively numberd from 0.
edfcbb8c DD	176	*/
eac44d9c AK	177	for (id = 0; setup_max_cpus && octeon_bootloader_entry_addr &&
eac44d9c AK	178	id < num_cores && id < NR_CPUS; id++) {
edfcbb8c DD	179	if (!(core_mask & (1 << id))) {
edfcbb8c DD	180	set_cpu_possible(cpus, true);
5b3b1688 DD	181	__cpu_number_map[id] = cpus;
	182	__cpu_logical_map[cpus] = id;
	183	cpus++;
	184	}
	185	}
edfcbb8c	186	#endif
773cb77d RB	187
773cb77d RB	188	octeon_smp_hotplug_setup();
5b3b1688 DD	189	}
5b3b1688 DD	190
3ff72be4 SH	191
	192	#ifdef CONFIG_RELOCATABLE
	193	int plat_post_relocation(long offset)
	194	{
	195	unsigned long entry = (unsigned long)kernel_entry;
	196
	197	/* Send secondaries into relocated kernel */
	198	octeon_processor_relocated_kernel_entry = entry + offset;
	199
	200	return 0;
	201	}
	202	#endif /* CONFIG_RELOCATABLE */
	203
5b3b1688 DD	204	/**
	205	* Firmware CPU startup hook
	206	*
	207	*/
	208	static void octeon_boot_secondary(int cpu, struct task_struct *idle)
	209	{
	210	int count;
	211
	212	pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu,
	213	cpu_logical_map(cpu));
	214
	215	octeon_processor_sp = __KSTK_TOS(idle);
	216	octeon_processor_gp = (unsigned long)(task_thread_info(idle));
	217	octeon_processor_boot = cpu_logical_map(cpu);
	218	mb();
	219
	220	count = 10000;
	221	while (octeon_processor_sp && count) {
	222	/* Waiting for processor to get the SP and GP */
	223	udelay(1);
	224	count--;
	225	}
	226	if (count == 0)
	227	pr_err("Secondary boot timeout\n");
	228	}
	229
	230	/**
	231	* After we've done initial boot, this function is called to allow the
	232	* board code to clean up state, if needed
	233	*/
078a55fc	234	static void octeon_init_secondary(void)
5b3b1688	235	{
babba4f1	236	unsigned int sr;
5b3b1688	237
babba4f1 DD	238	sr = set_c0_status(ST0_BEV);
	239	write_c0_ebase((u32)ebase);
	240	write_c0_status(sr);
	241
5b3b1688 DD	242	octeon_check_cpu_bist();
5b3b1688 DD	243	octeon_init_cvmcount();
0c326387 DD	244
0c326387 DD	245	octeon_irq_setup_secondary();
5b3b1688 DD	246	}
	247
	248	/**
	249	* Callout to firmware before smp_init
	250	*
	251	*/
0e8c1a32	252	static void __init octeon_prepare_cpus(unsigned int max_cpus)
5b3b1688	253	{
e650ce0f DD	254	/*
	255	* Only the low order mailbox bits are used for IPIs, leave
	256	* the other bits alone.
	257	*/
	258	cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff);
e63fb7a9 VS	259	if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt,
	260	IRQF_PERCPU \| IRQF_NO_THREAD, "SMP-IPI",
	261	mailbox_interrupt)) {
ab75dc02	262	panic("Cannot request_irq(OCTEON_IRQ_MBOX0)");
5b3b1688	263	}
5b3b1688 DD	264	}
	265
	266	/**
	267	* Last chance for the board code to finish SMP initialization before
	268	* the CPU is "online".
	269	*/
	270	static void octeon_smp_finish(void)
	271	{
5b3b1688 DD	272	octeon_user_io_init();
	273
	274	/* to generate the first CPU timer interrupt */
	275	write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
1bcfecc0	276	local_irq_enable();
5b3b1688 DD	277	}
5b3b1688 DD	278
773cb77d RB	279	#ifdef CONFIG_HOTPLUG_CPU
	280
	281	/* State of each CPU. */
	282	DEFINE_PER_CPU(int, cpu_state);
	283
773cb77d RB	284	static int octeon_cpu_disable(void)
	285	{
	286	unsigned int cpu = smp_processor_id();
	287
	288	if (cpu == 0)
	289	return -EBUSY;
	290
eac44d9c AK	291	if (!octeon_bootloader_entry_addr)
	292	return -ENOTSUPP;
	293
0b5f9c00	294	set_cpu_online(cpu, false);
826e99be	295	calculate_cpu_foreign_map();
17efb59a	296	octeon_fixup_irqs();
773cb77d	297
9329c154	298	__flush_cache_all();
773cb77d RB	299	local_flush_tlb_all();
773cb77d RB	300
773cb77d RB	301	return 0;
	302	}
	303
	304	static void octeon_cpu_die(unsigned int cpu)
	305	{
	306	int coreid = cpu_logical_map(cpu);
babba4f1 DD	307	uint32_t mask, new_mask;
babba4f1 DD	308	const struct cvmx_bootmem_named_block_desc *block_desc;
773cb77d	309
773cb77d RB	310	while (per_cpu(cpu_state, cpu) != CPU_DEAD)
	311	cpu_relax();
	312
	313	/*
	314	* This is a bit complicated strategics of getting/settig available
	315	* cores mask, copied from bootloader
	316	*/
babba4f1 DD	317
babba4f1 DD	318	mask = 1 << coreid;
773cb77d RB	319	/* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */
	320	block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
	321
	322	if (!block_desc) {
babba4f1	323	struct linux_app_boot_info *labi;
773cb77d	324
babba4f1	325	labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
773cb77d	326
babba4f1 DD	327	labi->avail_coremask \|= mask;
	328	new_mask = labi->avail_coremask;
	329	} else { /* alternative, already initialized */
	330	uint32_t p = (uint32_t )PHYS_TO_XKSEG_CACHED(block_desc->base_addr +
	331	AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
	332	*p \|= mask;
	333	new_mask = *p;
773cb77d RB	334	}
773cb77d RB	335
babba4f1 DD	336	pr_info("Reset core %d. Available Coremask = 0x%x \n", coreid, new_mask);
babba4f1 DD	337	mb();
773cb77d RB	338	cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
	339	cvmx_write_csr(CVMX_CIU_PP_RST, 0);
	340	}
	341
	342	void play_dead(void)
	343	{
babba4f1	344	int cpu = cpu_number_map(cvmx_get_core_num());
773cb77d RB	345
	346	idle_task_exit();
	347	octeon_processor_boot = 0xff;
babba4f1 DD	348	per_cpu(cpu_state, cpu) = CPU_DEAD;
	349
	350	mb();
773cb77d RB	351
	352	while (1) /* core will be reset here */
	353	;
	354	}
	355
773cb77d RB	356	static void start_after_reset(void)
773cb77d RB	357	{
70342287	358	kernel_entry(0, 0, 0); /* set a2 = 0 for secondary core */
773cb77d RB	359	}
773cb77d RB	360
babba4f1	361	static int octeon_update_boot_vector(unsigned int cpu)
773cb77d RB	362	{
	363
	364	int coreid = cpu_logical_map(cpu);
babba4f1 DD	365	uint32_t avail_coremask;
babba4f1 DD	366	const struct cvmx_bootmem_named_block_desc *block_desc;
773cb77d	367	struct boot_init_vector *boot_vect =
babba4f1	368	(struct boot_init_vector *)PHYS_TO_XKSEG_CACHED(BOOTLOADER_BOOT_VECTOR);
773cb77d RB	369
	370	block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
	371
	372	if (!block_desc) {
babba4f1 DD	373	struct linux_app_boot_info *labi;
	374
	375	labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
	376
	377	avail_coremask = labi->avail_coremask;
	378	labi->avail_coremask &= ~(1 << coreid);
773cb77d	379	} else { /* alternative, already initialized */
babba4f1 DD	380	avail_coremask = (uint32_t )PHYS_TO_XKSEG_CACHED(
babba4f1 DD	381	block_desc->base_addr + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
773cb77d RB	382	}
	383
	384	if (!(avail_coremask & (1 << coreid))) {
92a76f6d	385	/* core not available, assume, that caught by simple-executive */
773cb77d RB	386	cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
	387	cvmx_write_csr(CVMX_CIU_PP_RST, 0);
	388	}
	389
	390	boot_vect[coreid].app_start_func_addr =
	391	(uint32_t) (unsigned long) start_after_reset;
babba4f1	392	boot_vect[coreid].code_addr = octeon_bootloader_entry_addr;
773cb77d	393
babba4f1	394	mb();
773cb77d RB	395
	396	cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask);
	397
	398	return 0;
	399	}
	400
078a55fc	401	static int register_cavium_notifier(void)
773cb77d	402	{
dd6d7c6f SAS	403	return cpuhp_setup_state_nocalls(CPUHP_MIPS_SOC_PREPARE,
	404	"mips/cavium:prepare",
	405	octeon_update_boot_vector, NULL);
773cb77d	406	}
773cb77d RB	407	late_initcall(register_cavium_notifier);
773cb77d RB	408
70342287	409	#endif /* CONFIG_HOTPLUG_CPU */
773cb77d	410
5b3b1688 DD	411	struct plat_smp_ops octeon_smp_ops = {
	412	.send_ipi_single = octeon_send_ipi_single,
	413	.send_ipi_mask = octeon_send_ipi_mask,
	414	.init_secondary = octeon_init_secondary,
	415	.smp_finish = octeon_smp_finish,
5b3b1688 DD	416	.boot_secondary = octeon_boot_secondary,
	417	.smp_setup = octeon_smp_setup,
	418	.prepare_cpus = octeon_prepare_cpus,
773cb77d RB	419	#ifdef CONFIG_HOTPLUG_CPU
	420	.cpu_disable = octeon_cpu_disable,
	421	.cpu_die = octeon_cpu_die,
	422	#endif
5b3b1688	423	};
c6d2b22e DD	424
	425	static irqreturn_t octeon_78xx_reched_interrupt(int irq, void *dev_id)
	426	{
	427	scheduler_ipi();
	428	return IRQ_HANDLED;
	429	}
	430
	431	static irqreturn_t octeon_78xx_call_function_interrupt(int irq, void *dev_id)
	432	{
	433	generic_smp_call_function_interrupt();
	434	return IRQ_HANDLED;
	435	}
	436
	437	static irqreturn_t octeon_78xx_icache_flush_interrupt(int irq, void *dev_id)
	438	{
	439	octeon_icache_flush();
	440	return IRQ_HANDLED;
	441	}
	442
	443	/*
	444	* Callout to firmware before smp_init
	445	*/
	446	static void octeon_78xx_prepare_cpus(unsigned int max_cpus)
	447	{
	448	if (request_irq(OCTEON_IRQ_MBOX0 + 0,
	449	octeon_78xx_reched_interrupt,
	450	IRQF_PERCPU \| IRQF_NO_THREAD, "Scheduler",
	451	octeon_78xx_reched_interrupt)) {
	452	panic("Cannot request_irq for SchedulerIPI");
	453	}
	454	if (request_irq(OCTEON_IRQ_MBOX0 + 1,
	455	octeon_78xx_call_function_interrupt,
	456	IRQF_PERCPU \| IRQF_NO_THREAD, "SMP-Call",
	457	octeon_78xx_call_function_interrupt)) {
	458	panic("Cannot request_irq for SMP-Call");
	459	}
	460	if (request_irq(OCTEON_IRQ_MBOX0 + 2,
	461	octeon_78xx_icache_flush_interrupt,
	462	IRQF_PERCPU \| IRQF_NO_THREAD, "ICache-Flush",
	463	octeon_78xx_icache_flush_interrupt)) {
	464	panic("Cannot request_irq for ICache-Flush");
	465	}
	466	}
	467
	468	static void octeon_78xx_send_ipi_single(int cpu, unsigned int action)
	469	{
	470	int i;
	471
	472	for (i = 0; i < 8; i++) {
	473	if (action & 1)
	474	octeon_ciu3_mbox_send(cpu, i);
	475	action >>= 1;
	476	}
	477	}
	478
	479	static void octeon_78xx_send_ipi_mask(const struct cpumask *mask,
	480	unsigned int action)
	481	{
	482	unsigned int cpu;
	483
	484	for_each_cpu(cpu, mask)
	485	octeon_78xx_send_ipi_single(cpu, action);
	486	}
	487
488	static struct plat_smp_ops octeon_78xx_smp_ops = {
489	.send_ipi_single = octeon_78xx_send_ipi_single,
490	.send_ipi_mask = octeon_78xx_send_ipi_mask,
491	.init_secondary = octeon_init_secondary,
492	.smp_finish = octeon_smp_finish,
493	.boot_secondary = octeon_boot_secondary,
494	.smp_setup = octeon_smp_setup,
495	.prepare_cpus = octeon_78xx_prepare_cpus,
496	#ifdef CONFIG_HOTPLUG_CPU
497	.cpu_disable = octeon_cpu_disable,
498	.cpu_die = octeon_cpu_die,
499	#endif
500	};
501
502	void __init octeon_setup_smp(void)
503	{
504	struct plat_smp_ops *ops;
505
506	if (octeon_has_feature(OCTEON_FEATURE_CIU3))
507	ops = &octeon_78xx_smp_ops;
508	else
509	ops = &octeon_smp_ops;
510
511	register_smp_ops(ops);
512	}