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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * IRQ vector handles | |
3 | * | |
4 | * This file is subject to the terms and conditions of the GNU General Public | |
5 | * License. See the file "COPYING" in the main directory of this archive | |
6 | * for more details. | |
7 | * | |
8 | * Copyright (C) 1995, 1996, 1997, 2003 by Ralf Baechle | |
9 | */ | |
10 | #include <linux/kernel.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/irq.h> | |
c4ed38a0 RB |
13 | #include <linux/interrupt.h> |
14 | #include <linux/pci.h> | |
1da177e4 LT |
15 | |
16 | #include <asm/i8259.h> | |
17 | #include <asm/irq_cpu.h> | |
18 | #include <asm/gt64120.h> | |
19 | #include <asm/ptrace.h> | |
20 | ||
11ed6d5b | 21 | #include <asm/mach-cobalt/cobalt.h> |
1da177e4 | 22 | |
1da177e4 LT |
23 | /* |
24 | * We have two types of interrupts that we handle, ones that come in through | |
25 | * the CPU interrupt lines, and ones that come in on the via chip. The CPU | |
26 | * mappings are: | |
27 | * | |
c4ed38a0 RB |
28 | * 16 - Software interrupt 0 (unused) IE_SW0 |
29 | * 17 - Software interrupt 1 (unused) IE_SW1 | |
1da177e4 LT |
30 | * 18 - Galileo chip (timer) IE_IRQ0 |
31 | * 19 - Tulip 0 + NCR SCSI IE_IRQ1 | |
32 | * 20 - Tulip 1 IE_IRQ2 | |
33 | * 21 - 16550 UART IE_IRQ3 | |
34 | * 22 - VIA southbridge PIC IE_IRQ4 | |
35 | * 23 - unused IE_IRQ5 | |
36 | * | |
37 | * The VIA chip is a master/slave 8259 setup and has the following interrupts: | |
38 | * | |
39 | * 8 - RTC | |
40 | * 9 - PCI | |
41 | * 14 - IDE0 | |
42 | * 15 - IDE1 | |
43 | */ | |
44 | ||
937a8015 | 45 | static inline void galileo_irq(void) |
1da177e4 | 46 | { |
c4ed38a0 | 47 | unsigned int mask, pending, devfn; |
1da177e4 | 48 | |
c4ed38a0 RB |
49 | mask = GALILEO_INL(GT_INTRMASK_OFS); |
50 | pending = GALILEO_INL(GT_INTRCAUSE_OFS) & mask; | |
1da177e4 | 51 | |
c4ed38a0 | 52 | if (pending & GALILEO_INTR_T0EXP) { |
1da177e4 | 53 | |
c4ed38a0 | 54 | GALILEO_OUTL(~GALILEO_INTR_T0EXP, GT_INTRCAUSE_OFS); |
937a8015 | 55 | do_IRQ(COBALT_GALILEO_IRQ); |
1da177e4 | 56 | |
c4ed38a0 | 57 | } else if (pending & GALILEO_INTR_RETRY_CTR) { |
1da177e4 | 58 | |
c4ed38a0 RB |
59 | devfn = GALILEO_INL(GT_PCI0_CFGADDR_OFS) >> 8; |
60 | GALILEO_OUTL(~GALILEO_INTR_RETRY_CTR, GT_INTRCAUSE_OFS); | |
61 | printk(KERN_WARNING "Galileo: PCI retry count exceeded (%02x.%u)\n", | |
62 | PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
63 | ||
64 | } else { | |
1da177e4 | 65 | |
c4ed38a0 RB |
66 | GALILEO_OUTL(mask & ~pending, GT_INTRMASK_OFS); |
67 | printk(KERN_WARNING "Galileo: masking unexpected interrupt %08x\n", pending); | |
1da177e4 LT |
68 | } |
69 | } | |
70 | ||
937a8015 | 71 | static inline void via_pic_irq(void) |
c4ed38a0 RB |
72 | { |
73 | int irq; | |
74 | ||
75 | irq = i8259_irq(); | |
76 | if (irq >= 0) | |
937a8015 | 77 | do_IRQ(irq); |
c4ed38a0 RB |
78 | } |
79 | ||
937a8015 | 80 | asmlinkage void plat_irq_dispatch(void) |
c4ed38a0 | 81 | { |
937a8015 RB |
82 | unsigned pending = read_c0_status() & read_c0_cause(); |
83 | ||
84 | if (pending & CAUSEF_IP2) /* COBALT_GALILEO_IRQ (18) */ | |
85 | galileo_irq(); | |
86 | else if (pending & CAUSEF_IP6) /* COBALT_VIA_IRQ (22) */ | |
87 | via_pic_irq(); | |
88 | else if (pending & CAUSEF_IP3) /* COBALT_ETH0_IRQ (19) */ | |
89 | do_IRQ(COBALT_CPU_IRQ + 3); | |
90 | else if (pending & CAUSEF_IP4) /* COBALT_ETH1_IRQ (20) */ | |
91 | do_IRQ(COBALT_CPU_IRQ + 4); | |
92 | else if (pending & CAUSEF_IP5) /* COBALT_SERIAL_IRQ (21) */ | |
93 | do_IRQ(COBALT_CPU_IRQ + 5); | |
94 | else if (pending & CAUSEF_IP7) /* IRQ 23 */ | |
95 | do_IRQ(COBALT_CPU_IRQ + 7); | |
c4ed38a0 RB |
96 | } |
97 | ||
98 | static struct irqaction irq_via = { | |
99 | no_action, 0, { { 0, } }, "cascade", NULL, NULL | |
100 | }; | |
101 | ||
1da177e4 LT |
102 | void __init arch_init_irq(void) |
103 | { | |
c4ed38a0 RB |
104 | /* |
105 | * Mask all Galileo interrupts. The Galileo | |
106 | * handler is set in cobalt_timer_setup() | |
107 | */ | |
108 | GALILEO_OUTL(0, GT_INTRMASK_OFS); | |
109 | ||
1da177e4 | 110 | init_i8259_irqs(); /* 0 ... 15 */ |
c4ed38a0 | 111 | mips_cpu_irq_init(COBALT_CPU_IRQ); /* 16 ... 23 */ |
1da177e4 LT |
112 | |
113 | /* | |
114 | * Mask all cpu interrupts | |
115 | * (except IE4, we already masked those at VIA level) | |
116 | */ | |
117 | change_c0_status(ST0_IM, IE_IRQ4); | |
c4ed38a0 RB |
118 | |
119 | setup_irq(COBALT_VIA_IRQ, &irq_via); | |
1da177e4 | 120 | } |