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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * DEC I/O ASIC interrupts. |
3 | * | |
0fabe102 | 4 | * Copyright (c) 2002, 2003, 2013 Maciej W. Rozycki |
1da177e4 LT |
5 | * |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
13 | #include <linux/irq.h> | |
1da177e4 LT |
14 | #include <linux/types.h> |
15 | ||
16 | #include <asm/dec/ioasic.h> | |
17 | #include <asm/dec/ioasic_addrs.h> | |
18 | #include <asm/dec/ioasic_ints.h> | |
19 | ||
1da177e4 LT |
20 | static int ioasic_irq_base; |
21 | ||
009c200a | 22 | static void unmask_ioasic_irq(struct irq_data *d) |
1da177e4 LT |
23 | { |
24 | u32 simr; | |
25 | ||
26 | simr = ioasic_read(IO_REG_SIMR); | |
009c200a | 27 | simr |= (1 << (d->irq - ioasic_irq_base)); |
1da177e4 LT |
28 | ioasic_write(IO_REG_SIMR, simr); |
29 | } | |
30 | ||
009c200a | 31 | static void mask_ioasic_irq(struct irq_data *d) |
1da177e4 LT |
32 | { |
33 | u32 simr; | |
34 | ||
35 | simr = ioasic_read(IO_REG_SIMR); | |
009c200a | 36 | simr &= ~(1 << (d->irq - ioasic_irq_base)); |
1da177e4 LT |
37 | ioasic_write(IO_REG_SIMR, simr); |
38 | } | |
39 | ||
009c200a | 40 | static void ack_ioasic_irq(struct irq_data *d) |
1da177e4 | 41 | { |
009c200a | 42 | mask_ioasic_irq(d); |
1da177e4 LT |
43 | fast_iob(); |
44 | } | |
45 | ||
94dee171 | 46 | static struct irq_chip ioasic_irq_type = { |
70d21cde | 47 | .name = "IO-ASIC", |
009c200a TG |
48 | .irq_ack = ack_ioasic_irq, |
49 | .irq_mask = mask_ioasic_irq, | |
50 | .irq_mask_ack = ack_ioasic_irq, | |
51 | .irq_unmask = unmask_ioasic_irq, | |
1da177e4 LT |
52 | }; |
53 | ||
0fabe102 | 54 | static void clear_ioasic_dma_irq(struct irq_data *d) |
5359b938 MR |
55 | { |
56 | u32 sir; | |
57 | ||
0fabe102 | 58 | sir = ~(1 << (d->irq - ioasic_irq_base)); |
5359b938 | 59 | ioasic_write(IO_REG_SIR, sir); |
0fabe102 | 60 | fast_iob(); |
5359b938 MR |
61 | } |
62 | ||
94dee171 | 63 | static struct irq_chip ioasic_dma_irq_type = { |
70d21cde | 64 | .name = "IO-ASIC-DMA", |
0fabe102 | 65 | .irq_ack = clear_ioasic_dma_irq, |
009c200a | 66 | .irq_mask = mask_ioasic_irq, |
009c200a | 67 | .irq_unmask = unmask_ioasic_irq, |
0fabe102 | 68 | .irq_eoi = clear_ioasic_dma_irq, |
1da177e4 LT |
69 | }; |
70 | ||
0fabe102 MR |
71 | /* |
72 | * I/O ASIC implements two kinds of DMA interrupts, informational and | |
73 | * error interrupts. | |
74 | * | |
75 | * The formers do not stop DMA and should be cleared as soon as possible | |
76 | * so that if they retrigger before the handler has completed, usually as | |
77 | * a side effect of actions taken by the handler, then they are reissued. | |
78 | * These use the `handle_edge_irq' handler that clears the request right | |
79 | * away. | |
80 | * | |
81 | * The latters stop DMA and do not resume it until the interrupt has been | |
82 | * cleared. This cannot be done until after a corrective action has been | |
83 | * taken and this also means they will not retrigger. Therefore they use | |
84 | * the `handle_fasteoi_irq' handler that only clears the request on the | |
85 | * way out. Because MIPS processor interrupt inputs, one of which the I/O | |
86 | * ASIC is cascaded to, are level-triggered it is recommended that error | |
87 | * DMA interrupt action handlers are registered with the IRQF_ONESHOT flag | |
88 | * set so that they are run with the interrupt line masked. | |
89 | * | |
90 | * This mask has `1' bits in the positions of informational interrupts. | |
91 | */ | |
92 | #define IO_IRQ_DMA_INFO \ | |
93 | (IO_IRQ_MASK(IO_INR_SCC0A_RXDMA) | \ | |
94 | IO_IRQ_MASK(IO_INR_SCC1A_RXDMA) | \ | |
95 | IO_IRQ_MASK(IO_INR_ISDN_TXDMA) | \ | |
96 | IO_IRQ_MASK(IO_INR_ISDN_RXDMA) | \ | |
97 | IO_IRQ_MASK(IO_INR_ASC_DMA)) | |
98 | ||
1da177e4 LT |
99 | void __init init_ioasic_irqs(int base) |
100 | { | |
101 | int i; | |
102 | ||
103 | /* Mask interrupts. */ | |
104 | ioasic_write(IO_REG_SIMR, 0); | |
105 | fast_iob(); | |
106 | ||
1603b5ac | 107 | for (i = base; i < base + IO_INR_DMA; i++) |
e4ec7989 | 108 | irq_set_chip_and_handler(i, &ioasic_irq_type, |
1417836e | 109 | handle_level_irq); |
1603b5ac | 110 | for (; i < base + IO_IRQ_LINES; i++) |
0fabe102 MR |
111 | irq_set_chip_and_handler(i, &ioasic_dma_irq_type, |
112 | 1 << (i - base) & IO_IRQ_DMA_INFO ? | |
113 | handle_edge_irq : handle_fasteoi_irq); | |
1da177e4 LT |
114 | |
115 | ioasic_irq_base = base; | |
116 | } |