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2874c5fd 1// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4 2/*
1da177e4
LT
3 * DECstation 5000/200 (KN02) Control and Status Register
4 * interrupts.
5 *
64dac503 6 * Copyright (c) 2002, 2003, 2005 Maciej W. Rozycki
1da177e4
LT
7 */
8
9#include <linux/init.h>
10#include <linux/irq.h>
1da177e4
LT
11#include <linux/types.h>
12
13#include <asm/dec/kn02.h>
14
15
16/*
17 * Bits 7:0 of the Control Register are write-only -- the
18 * corresponding bits of the Status Register have a different
19 * meaning. Hence we use a cache. It speeds up things a bit
20 * as well.
21 *
22 * There is no default value -- it has to be initialized.
23 */
24u32 cached_kn02_csr;
1da177e4 25
1da177e4
LT
26static int kn02_irq_base;
27
009c200a 28static void unmask_kn02_irq(struct irq_data *d)
1da177e4 29{
a5fc9c0b
MR
30 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
31 KN02_CSR);
1da177e4 32
009c200a 33 cached_kn02_csr |= (1 << (d->irq - kn02_irq_base + 16));
1da177e4
LT
34 *csr = cached_kn02_csr;
35}
36
009c200a 37static void mask_kn02_irq(struct irq_data *d)
1da177e4 38{
a5fc9c0b
MR
39 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
40 KN02_CSR);
1da177e4 41
009c200a 42 cached_kn02_csr &= ~(1 << (d->irq - kn02_irq_base + 16));
1da177e4
LT
43 *csr = cached_kn02_csr;
44}
45
009c200a 46static void ack_kn02_irq(struct irq_data *d)
1da177e4 47{
009c200a 48 mask_kn02_irq(d);
1da177e4
LT
49 iob();
50}
51
94dee171 52static struct irq_chip kn02_irq_type = {
70d21cde 53 .name = "KN02-CSR",
009c200a
TG
54 .irq_ack = ack_kn02_irq,
55 .irq_mask = mask_kn02_irq,
56 .irq_mask_ack = ack_kn02_irq,
57 .irq_unmask = unmask_kn02_irq,
1da177e4
LT
58};
59
1da177e4
LT
60void __init init_kn02_irqs(int base)
61{
a5fc9c0b
MR
62 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
63 KN02_CSR);
1da177e4
LT
64 int i;
65
66 /* Mask interrupts. */
64dac503 67 cached_kn02_csr &= ~KN02_CSR_IOINTEN;
1da177e4
LT
68 *csr = cached_kn02_csr;
69 iob();
1603b5ac
AN
70
71 for (i = base; i < base + KN02_IRQ_LINES; i++)
e4ec7989 72 irq_set_chip_and_handler(i, &kn02_irq_type, handle_level_irq);
1da177e4
LT
73
74 kn02_irq_base = base;
75}