[mirror_ubuntu-jammy-kernel.git] / arch / mips / include / asm / asm.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
 * Copyright (C) 1999 by Silicon Graphics, Inc.
 * Copyright (C) 2001 MIPS Technologies, Inc.
 * Copyright (C) 2002  Maciej W. Rozycki
 *
 * Some useful macros for MIPS assembler code
 *
 * Some of the routines below contain useless nops that will be optimized
 * away by gas in -O mode. These nops are however required to fill delay
 * slots in noreorder mode.
 */
#ifndef __ASM_ASM_H
#define __ASM_ASM_H

#include <asm/sgidefs.h>
#include <asm/asm-eva.h>

/*
 * LEAF - declare leaf routine
 */
#define LEAF(symbol)					\
		.globl	symbol;				\
		.align	2;				\
		.type	symbol, @function;		\
		.ent	symbol, 0;			\
symbol:		.frame	sp, 0, ra;			\
		.cfi_startproc;				\
		.insn

/*
 * NESTED - declare nested routine entry point
 */
#define NESTED(symbol, framesize, rpc)			\
		.globl	symbol;				\
		.align	2;				\
		.type	symbol, @function;		\
		.ent	symbol, 0;			\
symbol:		.frame	sp, framesize, rpc;		\
		.cfi_startproc;				\
		.insn

/*
 * END - mark end of function
 */
#define END(function)					\
		.cfi_endproc;				\
		.end	function;			\
		.size	function, .-function

/*
 * EXPORT - export definition of symbol
 */
#define EXPORT(symbol)					\
		.globl	symbol;				\
symbol:

/*
 * FEXPORT - export definition of a function symbol
 */
#define FEXPORT(symbol)					\
		.globl	symbol;				\
		.type	symbol, @function;		\
symbol:		.insn

/*
 * ABS - export absolute symbol
 */
#define ABS(symbol,value)				\
		.globl	symbol;				\
symbol		=	value

#define PANIC(msg)					\
		.set	push;				\
		.set	reorder;			\
		PTR_LA	a0, 8f;				 \
		jal	panic;				\
9:		b	9b;				\
		.set	pop;				\
		TEXT(msg)

/*
 * Print formatted string
 */
#ifdef CONFIG_PRINTK
#define PRINT(string)					\
		.set	push;				\
		.set	reorder;			\
		PTR_LA	a0, 8f;				 \
		jal	printk;				\
		.set	pop;				\
		TEXT(string)
#else
#define PRINT(string)
#endif

#define TEXT(msg)					\
		.pushsection .data;			\
8:		.asciiz msg;				\
		.popsection;

/*
 * Stack alignment
 */
#if (_MIPS_SIM == _MIPS_SIM_ABI32)
#define ALSZ	7
#define ALMASK	~7
#endif
#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
#define ALSZ	15
#define ALMASK	~15
#endif

/*
 * Macros to handle different pointer/register sizes for 32/64-bit code
 */

/*
 * Size of a register
 */
#ifdef __mips64
#define SZREG	8
#else
#define SZREG	4
#endif

/*
 * Use the following macros in assemblercode to load/store registers,
 * pointers etc.
 */
#if (_MIPS_SIM == _MIPS_SIM_ABI32)
#define REG_S		sw
#define REG_L		lw
#define REG_SUBU	subu
#define REG_ADDU	addu
#endif
#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
#define REG_S		sd
#define REG_L		ld
#define REG_SUBU	dsubu
#define REG_ADDU	daddu
#endif

/*
 * How to add/sub/load/store/shift C int variables.
 */
#if (_MIPS_SZINT == 32)
#define INT_ADD		add
#define INT_ADDU	addu
#define INT_ADDI	addi
#define INT_ADDIU	addiu
#define INT_SUB		sub
#define INT_SUBU	subu
#define INT_L		lw
#define INT_S		sw
#define INT_SLL		sll
#define INT_SLLV	sllv
#define INT_SRL		srl
#define INT_SRLV	srlv
#define INT_SRA		sra
#define INT_SRAV	srav
#endif

#if (_MIPS_SZINT == 64)
#define INT_ADD		dadd
#define INT_ADDU	daddu
#define INT_ADDI	daddi
#define INT_ADDIU	daddiu
#define INT_SUB		dsub
#define INT_SUBU	dsubu
#define INT_L		ld
#define INT_S		sd
#define INT_SLL		dsll
#define INT_SLLV	dsllv
#define INT_SRL		dsrl
#define INT_SRLV	dsrlv
#define INT_SRA		dsra
#define INT_SRAV	dsrav
#endif

/*
 * How to add/sub/load/store/shift C long variables.
 */
#if (_MIPS_SZLONG == 32)
#define LONG_ADD	add
#define LONG_ADDU	addu
#define LONG_ADDI	addi
#define LONG_ADDIU	addiu
#define LONG_SUB	sub
#define LONG_SUBU	subu
#define LONG_L		lw
#define LONG_S		sw
#define LONG_SP		swp
#define LONG_SLL	sll
#define LONG_SLLV	sllv
#define LONG_SRL	srl
#define LONG_SRLV	srlv
#define LONG_SRA	sra
#define LONG_SRAV	srav

#ifdef __ASSEMBLY__
#define LONG		.word
#endif
#define LONGSIZE	4
#define LONGMASK	3
#define LONGLOG		2
#endif

#if (_MIPS_SZLONG == 64)
#define LONG_ADD	dadd
#define LONG_ADDU	daddu
#define LONG_ADDI	daddi
#define LONG_ADDIU	daddiu
#define LONG_SUB	dsub
#define LONG_SUBU	dsubu
#define LONG_L		ld
#define LONG_S		sd
#define LONG_SP		sdp
#define LONG_SLL	dsll
#define LONG_SLLV	dsllv
#define LONG_SRL	dsrl
#define LONG_SRLV	dsrlv
#define LONG_SRA	dsra
#define LONG_SRAV	dsrav

#ifdef __ASSEMBLY__
#define LONG		.dword
#endif
#define LONGSIZE	8
#define LONGMASK	7
#define LONGLOG		3
#endif

/*
 * How to add/sub/load/store/shift pointers.
 */
#if (_MIPS_SZPTR == 32)
#define PTR_ADD		add
#define PTR_ADDU	addu
#define PTR_ADDI	addi
#define PTR_ADDIU	addiu
#define PTR_SUB		sub
#define PTR_SUBU	subu
#define PTR_L		lw
#define PTR_S		sw
#define PTR_LA		la
#define PTR_LI		li
#define PTR_SLL		sll
#define PTR_SLLV	sllv
#define PTR_SRL		srl
#define PTR_SRLV	srlv
#define PTR_SRA		sra
#define PTR_SRAV	srav

#define PTR_SCALESHIFT	2

#define PTR		.word
#define PTRSIZE		4
#define PTRLOG		2
#endif

#if (_MIPS_SZPTR == 64)
#define PTR_ADD		dadd
#define PTR_ADDU	daddu
#define PTR_ADDI	daddi
#define PTR_ADDIU	daddiu
#define PTR_SUB		dsub
#define PTR_SUBU	dsubu
#define PTR_L		ld
#define PTR_S		sd
#define PTR_LA		dla
#define PTR_LI		dli
#define PTR_SLL		dsll
#define PTR_SLLV	dsllv
#define PTR_SRL		dsrl
#define PTR_SRLV	dsrlv
#define PTR_SRA		dsra
#define PTR_SRAV	dsrav

#define PTR_SCALESHIFT	3

#define PTR		.dword
#define PTRSIZE		8
#define PTRLOG		3
#endif

/*
 * Some cp0 registers were extended to 64bit for MIPS III.
 */
#if (_MIPS_SIM == _MIPS_SIM_ABI32)
#define MFC0		mfc0
#define MTC0		mtc0
#endif
#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
#define MFC0		dmfc0
#define MTC0		dmtc0
#endif

#define SSNOP		sll zero, zero, 1

#ifdef CONFIG_SGI_IP28
/* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
#include <asm/cacheops.h>
#define R10KCBARRIER(addr)  cache   Cache_Barrier, addr;
#else
#define R10KCBARRIER(addr)
#endif

#endif /* __ASM_ASM_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
	7	* Copyright (C) 1999 by Silicon Graphics, Inc.
	8	* Copyright (C) 2001 MIPS Technologies, Inc.
	9	* Copyright (C) 2002 Maciej W. Rozycki
	10	*
	11	* Some useful macros for MIPS assembler code
	12	*
	13	* Some of the routines below contain useless nops that will be optimized
	14	* away by gas in -O mode. These nops are however required to fill delay
	15	* slots in noreorder mode.
	16	*/
	17	#ifndef __ASM_ASM_H
	18	#define __ASM_ASM_H
	19
1da177e4	20	#include <asm/sgidefs.h>
93244945	21	#include <asm/asm-eva.h>
1da177e4	22
1da177e4 LT	23	/*
	24	* LEAF - declare leaf routine
	25	*/
70342287 RB	26	#define LEAF(symbol) \
	27	.globl symbol; \
	28	.align 2; \
	29	.type symbol, @function; \
	30	.ent symbol, 0; \
08889582	31	symbol: .frame sp, 0, ra; \
866b6a89	32	.cfi_startproc; \
08889582	33	.insn
1da177e4 LT	34
	35	/*
	36	* NESTED - declare nested routine entry point
	37	*/
70342287 RB	38	#define NESTED(symbol, framesize, rpc) \
	39	.globl symbol; \
	40	.align 2; \
	41	.type symbol, @function; \
08889582 PB	42	.ent symbol, 0; \
08889582 PB	43	symbol: .frame sp, framesize, rpc; \
866b6a89	44	.cfi_startproc; \
08889582	45	.insn
1da177e4 LT	46
	47	/*
	48	* END - mark end of function
	49	*/
70342287	50	#define END(function) \
866b6a89	51	.cfi_endproc; \
70342287	52	.end function; \
21a151d8	53	.size function, .-function
1da177e4 LT	54
	55	/*
	56	* EXPORT - export definition of symbol
	57	*/
	58	#define EXPORT(symbol) \
70342287	59	.globl symbol; \
1da177e4 LT	60	symbol:
	61
	62	/*
	63	* FEXPORT - export definition of a function symbol
	64	*/
	65	#define FEXPORT(symbol) \
	66	.globl symbol; \
21a151d8	67	.type symbol, @function; \
08889582	68	symbol: .insn
1da177e4 LT	69
	70	/*
	71	* ABS - export absolute symbol
	72	*/
70342287 RB	73	#define ABS(symbol,value) \
70342287 RB	74	.globl symbol; \
1da177e4 LT	75	symbol = value
1da177e4 LT	76
70342287	77	#define PANIC(msg) \
1da177e4	78	.set push; \
70342287 RB	79	.set reorder; \
	80	PTR_LA a0, 8f; \
	81	jal panic; \
	82	9: b 9b; \
1da177e4 LT	83	.set pop; \
	84	TEXT(msg)
	85
	86	/*
	87	* Print formatted string
	88	*/
ac130ac4	89	#ifdef CONFIG_PRINTK
70342287	90	#define PRINT(string) \
1da177e4	91	.set push; \
70342287 RB	92	.set reorder; \
	93	PTR_LA a0, 8f; \
	94	jal printk; \
1da177e4 LT	95	.set pop; \
1da177e4 LT	96	TEXT(string)
ac130ac4 RB	97	#else
	98	#define PRINT(string)
	99	#endif
1da177e4	100
70342287	101	#define TEXT(msg) \
1da177e4	102	.pushsection .data; \
70342287	103	8: .asciiz msg; \
1da177e4 LT	104	.popsection;
1da177e4 LT	105
1da177e4 LT	106	/*
	107	* Stack alignment
	108	*/
	109	#if (_MIPS_SIM == _MIPS_SIM_ABI32)
	110	#define ALSZ 7
	111	#define ALMASK ~7
	112	#endif
	113	#if (_MIPS_SIM == _MIPS_SIM_NABI32) \|\| (_MIPS_SIM == _MIPS_SIM_ABI64)
	114	#define ALSZ 15
	115	#define ALMASK ~15
	116	#endif
	117
	118	/*
	119	* Macros to handle different pointer/register sizes for 32/64-bit code
	120	*/
	121
	122	/*
	123	* Size of a register
	124	*/
	125	#ifdef __mips64
	126	#define SZREG 8
	127	#else
	128	#define SZREG 4
	129	#endif
	130
	131	/*
	132	* Use the following macros in assemblercode to load/store registers,
	133	* pointers etc.
	134	*/
	135	#if (_MIPS_SIM == _MIPS_SIM_ABI32)
	136	#define REG_S sw
	137	#define REG_L lw
	138	#define REG_SUBU subu
	139	#define REG_ADDU addu
	140	#endif
	141	#if (_MIPS_SIM == _MIPS_SIM_NABI32) \|\| (_MIPS_SIM == _MIPS_SIM_ABI64)
	142	#define REG_S sd
	143	#define REG_L ld
	144	#define REG_SUBU dsubu
	145	#define REG_ADDU daddu
	146	#endif
	147
	148	/*
	149	* How to add/sub/load/store/shift C int variables.
	150	*/
	151	#if (_MIPS_SZINT == 32)
	152	#define INT_ADD add
	153	#define INT_ADDU addu
	154	#define INT_ADDI addi
	155	#define INT_ADDIU addiu
	156	#define INT_SUB sub
	157	#define INT_SUBU subu
	158	#define INT_L lw
	159	#define INT_S sw
	160	#define INT_SLL sll
	161	#define INT_SLLV sllv
	162	#define INT_SRL srl
	163	#define INT_SRLV srlv
	164	#define INT_SRA sra
	165	#define INT_SRAV srav
	166	#endif
	167
	168	#if (_MIPS_SZINT == 64)
	169	#define INT_ADD dadd
170	#define INT_ADDU daddu
171	#define INT_ADDI daddi
172	#define INT_ADDIU daddiu
173	#define INT_SUB dsub
174	#define INT_SUBU dsubu
175	#define INT_L ld
176	#define INT_S sd
177	#define INT_SLL dsll
178	#define INT_SLLV dsllv
179	#define INT_SRL dsrl
180	#define INT_SRLV dsrlv
181	#define INT_SRA dsra
182	#define INT_SRAV dsrav
183	#endif
184
185	/*
186	* How to add/sub/load/store/shift C long variables.
187	*/
188	#if (_MIPS_SZLONG == 32)
189	#define LONG_ADD add
190	#define LONG_ADDU addu
191	#define LONG_ADDI addi
192	#define LONG_ADDIU addiu
193	#define LONG_SUB sub
194	#define LONG_SUBU subu
195	#define LONG_L lw
196	#define LONG_S sw
26c5e07d	197	#define LONG_SP swp
1da177e4 LT	198	#define LONG_SLL sll
	199	#define LONG_SLLV sllv
	200	#define LONG_SRL srl
	201	#define LONG_SRLV srlv
	202	#define LONG_SRA sra
	203	#define LONG_SRAV srav
	204
d339cd02	205	#ifdef __ASSEMBLY__
1da177e4	206	#define LONG .word
d339cd02	207	#endif
1da177e4 LT	208	#define LONGSIZE 4
	209	#define LONGMASK 3
	210	#define LONGLOG 2
	211	#endif
	212
	213	#if (_MIPS_SZLONG == 64)
	214	#define LONG_ADD dadd
	215	#define LONG_ADDU daddu
	216	#define LONG_ADDI daddi
	217	#define LONG_ADDIU daddiu
	218	#define LONG_SUB dsub
	219	#define LONG_SUBU dsubu
	220	#define LONG_L ld
	221	#define LONG_S sd
26c5e07d	222	#define LONG_SP sdp
1da177e4 LT	223	#define LONG_SLL dsll
	224	#define LONG_SLLV dsllv
	225	#define LONG_SRL dsrl
	226	#define LONG_SRLV dsrlv
	227	#define LONG_SRA dsra
	228	#define LONG_SRAV dsrav
	229
d339cd02	230	#ifdef __ASSEMBLY__
1da177e4	231	#define LONG .dword
d339cd02	232	#endif
1da177e4 LT	233	#define LONGSIZE 8
	234	#define LONGMASK 7
	235	#define LONGLOG 3
	236	#endif
	237
	238	/*
	239	* How to add/sub/load/store/shift pointers.
	240	*/
	241	#if (_MIPS_SZPTR == 32)
	242	#define PTR_ADD add
	243	#define PTR_ADDU addu
	244	#define PTR_ADDI addi
	245	#define PTR_ADDIU addiu
	246	#define PTR_SUB sub
	247	#define PTR_SUBU subu
	248	#define PTR_L lw
	249	#define PTR_S sw
	250	#define PTR_LA la
242954b5	251	#define PTR_LI li
1da177e4 LT	252	#define PTR_SLL sll
	253	#define PTR_SLLV sllv
	254	#define PTR_SRL srl
	255	#define PTR_SRLV srlv
	256	#define PTR_SRA sra
	257	#define PTR_SRAV srav
	258
	259	#define PTR_SCALESHIFT 2
	260
	261	#define PTR .word
	262	#define PTRSIZE 4
	263	#define PTRLOG 2
	264	#endif
	265
	266	#if (_MIPS_SZPTR == 64)
	267	#define PTR_ADD dadd
	268	#define PTR_ADDU daddu
	269	#define PTR_ADDI daddi
	270	#define PTR_ADDIU daddiu
	271	#define PTR_SUB dsub
	272	#define PTR_SUBU dsubu
	273	#define PTR_L ld
	274	#define PTR_S sd
	275	#define PTR_LA dla
242954b5	276	#define PTR_LI dli
1da177e4 LT	277	#define PTR_SLL dsll
	278	#define PTR_SLLV dsllv
	279	#define PTR_SRL dsrl
	280	#define PTR_SRLV dsrlv
	281	#define PTR_SRA dsra
	282	#define PTR_SRAV dsrav
	283
	284	#define PTR_SCALESHIFT 3
	285
	286	#define PTR .dword
	287	#define PTRSIZE 8
	288	#define PTRLOG 3
	289	#endif
	290
	291	/*
	292	* Some cp0 registers were extended to 64bit for MIPS III.
	293	*/
	294	#if (_MIPS_SIM == _MIPS_SIM_ABI32)
	295	#define MFC0 mfc0
	296	#define MTC0 mtc0
	297	#endif
	298	#if (_MIPS_SIM == _MIPS_SIM_NABI32) \|\| (_MIPS_SIM == _MIPS_SIM_ABI64)
	299	#define MFC0 dmfc0
	300	#define MTC0 dmtc0
	301	#endif
	302
21a151d8	303	#define SSNOP sll zero, zero, 1
1da177e4	304
930bff88 TB	305	#ifdef CONFIG_SGI_IP28
	306	/* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
	307	#include <asm/cacheops.h>
	308	#define R10KCBARRIER(addr) cache Cache_Barrier, addr;
	309	#else
	310	#define R10KCBARRIER(addr)
	311	#endif
	312
1da177e4	313	#endif /* __ASM_ASM_H */