[mirror_ubuntu-bionic-kernel.git] / arch / mips / include / asm / asmmacro.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2003 Ralf Baechle
 */
#ifndef _ASM_ASMMACRO_H
#define _ASM_ASMMACRO_H

#include <asm/hazards.h>
#include <asm/asm-offsets.h>
#include <asm/msa.h>

#ifdef CONFIG_32BIT
#include <asm/asmmacro-32.h>
#endif
#ifdef CONFIG_64BIT
#include <asm/asmmacro-64.h>
#endif

/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
#undef fp

/*
 * Helper macros for generating raw instruction encodings.
 */
#ifdef CONFIG_CPU_MICROMIPS
	.macro	insn32_if_mm enc
	.insn
	.hword ((\enc) >> 16)
	.hword ((\enc) & 0xffff)
	.endm

	.macro	insn_if_mips enc
	.endm
#else
	.macro	insn32_if_mm enc
	.endm

	.macro	insn_if_mips enc
	.insn
	.word (\enc)
	.endm
#endif

#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
	.macro	local_irq_enable reg=t0
	ei
	irq_enable_hazard
	.endm

	.macro	local_irq_disable reg=t0
	di
	irq_disable_hazard
	.endm
#else
	.macro	local_irq_enable reg=t0
	mfc0	\reg, CP0_STATUS
	ori	\reg, \reg, 1
	mtc0	\reg, CP0_STATUS
	irq_enable_hazard
	.endm

	.macro	local_irq_disable reg=t0
#ifdef CONFIG_PREEMPT
	lw      \reg, TI_PRE_COUNT($28)
	addi    \reg, \reg, 1
	sw      \reg, TI_PRE_COUNT($28)
#endif
	mfc0	\reg, CP0_STATUS
	ori	\reg, \reg, 1
	xori	\reg, \reg, 1
	mtc0	\reg, CP0_STATUS
	irq_disable_hazard
#ifdef CONFIG_PREEMPT
	lw      \reg, TI_PRE_COUNT($28)
	addi    \reg, \reg, -1
	sw      \reg, TI_PRE_COUNT($28)
#endif
	.endm
#endif /* CONFIG_CPU_MIPSR2 */

	.macro	fpu_save_16even thread tmp=t0
	.set	push
	SET_HARDFLOAT
	cfc1	\tmp, fcr31
	sdc1	$f0,  THREAD_FPR0(\thread)
	sdc1	$f2,  THREAD_FPR2(\thread)
	sdc1	$f4,  THREAD_FPR4(\thread)
	sdc1	$f6,  THREAD_FPR6(\thread)
	sdc1	$f8,  THREAD_FPR8(\thread)
	sdc1	$f10, THREAD_FPR10(\thread)
	sdc1	$f12, THREAD_FPR12(\thread)
	sdc1	$f14, THREAD_FPR14(\thread)
	sdc1	$f16, THREAD_FPR16(\thread)
	sdc1	$f18, THREAD_FPR18(\thread)
	sdc1	$f20, THREAD_FPR20(\thread)
	sdc1	$f22, THREAD_FPR22(\thread)
	sdc1	$f24, THREAD_FPR24(\thread)
	sdc1	$f26, THREAD_FPR26(\thread)
	sdc1	$f28, THREAD_FPR28(\thread)
	sdc1	$f30, THREAD_FPR30(\thread)
	sw	\tmp, THREAD_FCR31(\thread)
	.set	pop
	.endm

	.macro	fpu_save_16odd thread
	.set	push
	.set	mips64r2
	.set	fp=64
	SET_HARDFLOAT
	sdc1	$f1,  THREAD_FPR1(\thread)
	sdc1	$f3,  THREAD_FPR3(\thread)
	sdc1	$f5,  THREAD_FPR5(\thread)
	sdc1	$f7,  THREAD_FPR7(\thread)
	sdc1	$f9,  THREAD_FPR9(\thread)
	sdc1	$f11, THREAD_FPR11(\thread)
	sdc1	$f13, THREAD_FPR13(\thread)
	sdc1	$f15, THREAD_FPR15(\thread)
	sdc1	$f17, THREAD_FPR17(\thread)
	sdc1	$f19, THREAD_FPR19(\thread)
	sdc1	$f21, THREAD_FPR21(\thread)
	sdc1	$f23, THREAD_FPR23(\thread)
	sdc1	$f25, THREAD_FPR25(\thread)
	sdc1	$f27, THREAD_FPR27(\thread)
	sdc1	$f29, THREAD_FPR29(\thread)
	sdc1	$f31, THREAD_FPR31(\thread)
	.set	pop
	.endm

	.macro	fpu_save_double thread status tmp
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
		defined(CONFIG_CPU_MIPSR6)
	sll	\tmp, \status, 5
	bgez	\tmp, 10f
	fpu_save_16odd \thread
10:
#endif
	fpu_save_16even \thread \tmp
	.endm

	.macro	fpu_restore_16even thread tmp=t0
	.set	push
	SET_HARDFLOAT
	lw	\tmp, THREAD_FCR31(\thread)
	ldc1	$f0,  THREAD_FPR0(\thread)
	ldc1	$f2,  THREAD_FPR2(\thread)
	ldc1	$f4,  THREAD_FPR4(\thread)
	ldc1	$f6,  THREAD_FPR6(\thread)
	ldc1	$f8,  THREAD_FPR8(\thread)
	ldc1	$f10, THREAD_FPR10(\thread)
	ldc1	$f12, THREAD_FPR12(\thread)
	ldc1	$f14, THREAD_FPR14(\thread)
	ldc1	$f16, THREAD_FPR16(\thread)
	ldc1	$f18, THREAD_FPR18(\thread)
	ldc1	$f20, THREAD_FPR20(\thread)
	ldc1	$f22, THREAD_FPR22(\thread)
	ldc1	$f24, THREAD_FPR24(\thread)
	ldc1	$f26, THREAD_FPR26(\thread)
	ldc1	$f28, THREAD_FPR28(\thread)
	ldc1	$f30, THREAD_FPR30(\thread)
	ctc1	\tmp, fcr31
	.set	pop
	.endm

	.macro	fpu_restore_16odd thread
	.set	push
	.set	mips64r2
	.set	fp=64
	SET_HARDFLOAT
	ldc1	$f1,  THREAD_FPR1(\thread)
	ldc1	$f3,  THREAD_FPR3(\thread)
	ldc1	$f5,  THREAD_FPR5(\thread)
	ldc1	$f7,  THREAD_FPR7(\thread)
	ldc1	$f9,  THREAD_FPR9(\thread)
	ldc1	$f11, THREAD_FPR11(\thread)
	ldc1	$f13, THREAD_FPR13(\thread)
	ldc1	$f15, THREAD_FPR15(\thread)
	ldc1	$f17, THREAD_FPR17(\thread)
	ldc1	$f19, THREAD_FPR19(\thread)
	ldc1	$f21, THREAD_FPR21(\thread)
	ldc1	$f23, THREAD_FPR23(\thread)
	ldc1	$f25, THREAD_FPR25(\thread)
	ldc1	$f27, THREAD_FPR27(\thread)
	ldc1	$f29, THREAD_FPR29(\thread)
	ldc1	$f31, THREAD_FPR31(\thread)
	.set	pop
	.endm

	.macro	fpu_restore_double thread status tmp
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \
		defined(CONFIG_CPU_MIPSR6)
	sll	\tmp, \status, 5
	bgez	\tmp, 10f				# 16 register mode?

	fpu_restore_16odd \thread
10:
#endif
	fpu_restore_16even \thread \tmp
	.endm

#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
	.macro	_EXT	rd, rs, p, s
	ext	\rd, \rs, \p, \s
	.endm
#else /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */
	.macro	_EXT	rd, rs, p, s
	srl	\rd, \rs, \p
	andi	\rd, \rd, (1 << \s) - 1
	.endm
#endif /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */

/*
 * Temporary until all gas have MT ASE support
 */
	.macro	DMT	reg=0
	.word	0x41600bc1 | (\reg << 16)
	.endm

	.macro	EMT	reg=0
	.word	0x41600be1 | (\reg << 16)
	.endm

	.macro	DVPE	reg=0
	.word	0x41600001 | (\reg << 16)
	.endm

	.macro	EVPE	reg=0
	.word	0x41600021 | (\reg << 16)
	.endm

	.macro	MFTR	rt=0, rd=0, u=0, sel=0
	 .word	0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
	.endm

	.macro	MTTR	rt=0, rd=0, u=0, sel=0
	 .word	0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
	.endm

#ifdef TOOLCHAIN_SUPPORTS_MSA
	.macro	_cfcmsa	rd, cs
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	cfcmsa	\rd, $\cs
	.set	pop
	.endm

	.macro	_ctcmsa	cd, rs
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	ctcmsa	$\cd, \rs
	.set	pop
	.endm

	.macro	ld_b	wd, off, base
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	ld.b	$w\wd, \off(\base)
	.set	pop
	.endm

	.macro	ld_h	wd, off, base
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	ld.h	$w\wd, \off(\base)
	.set	pop
	.endm

	.macro	ld_w	wd, off, base
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	ld.w	$w\wd, \off(\base)
	.set	pop
	.endm

	.macro	ld_d	wd, off, base
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	ld.d	$w\wd, \off(\base)
	.set	pop
	.endm

	.macro	st_b	wd, off, base
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	st.b	$w\wd, \off(\base)
	.set	pop
	.endm

	.macro	st_h	wd, off, base
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	st.h	$w\wd, \off(\base)
	.set	pop
	.endm

	.macro	st_w	wd, off, base
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	st.w	$w\wd, \off(\base)
	.set	pop
	.endm

	.macro	st_d	wd, off, base
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	st.d	$w\wd, \off(\base)
	.set	pop
	.endm

	.macro	copy_s_w	ws, n
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	copy_s.w $1, $w\ws[\n]
	.set	pop
	.endm

	.macro	copy_s_d	ws, n
	.set	push
	.set	mips64r2
	.set	fp=64
	.set	msa
	copy_s.d $1, $w\ws[\n]
	.set	pop
	.endm

	.macro	insert_w	wd, n
	.set	push
	.set	mips32r2
	.set	fp=64
	.set	msa
	insert.w $w\wd[\n], $1
	.set	pop
	.endm

	.macro	insert_d	wd, n
	.set	push
	.set	mips64r2
	.set	fp=64
	.set	msa
	insert.d $w\wd[\n], $1
	.set	pop
	.endm
#else

	/*
	 * Temporary until all toolchains in use include MSA support.
	 */
	.macro	_cfcmsa	rd, cs
	.set	push
	.set	noat
	SET_HARDFLOAT
	insn_if_mips 0x787e0059 | (\cs << 11)
	insn32_if_mm 0x587e0056 | (\cs << 11)
	move	\rd, $1
	.set	pop
	.endm

	.macro	_ctcmsa	cd, rs
	.set	push
	.set	noat
	SET_HARDFLOAT
	move	$1, \rs
	insn_if_mips 0x783e0819 | (\cd << 6)
	insn32_if_mm 0x583e0816 | (\cd << 6)
	.set	pop
	.endm

	.macro	ld_b	wd, off, base
	.set	push
	.set	noat
	SET_HARDFLOAT
	PTR_ADDU $1, \base, \off
	insn_if_mips 0x78000820 | (\wd << 6)
	insn32_if_mm 0x58000807 | (\wd << 6)
	.set	pop
	.endm

	.macro	ld_h	wd, off, base
	.set	push
	.set	noat
	SET_HARDFLOAT
	PTR_ADDU $1, \base, \off
	insn_if_mips 0x78000821 | (\wd << 6)
	insn32_if_mm 0x58000817 | (\wd << 6)
	.set	pop
	.endm

	.macro	ld_w	wd, off, base
	.set	push
	.set	noat
	SET_HARDFLOAT
	PTR_ADDU $1, \base, \off
	insn_if_mips 0x78000822 | (\wd << 6)
	insn32_if_mm 0x58000827 | (\wd << 6)
	.set	pop
	.endm

	.macro	ld_d	wd, off, base
	.set	push
	.set	noat
	SET_HARDFLOAT
	PTR_ADDU $1, \base, \off
	insn_if_mips 0x78000823 | (\wd << 6)
	insn32_if_mm 0x58000837 | (\wd << 6)
	.set	pop
	.endm

	.macro	st_b	wd, off, base
	.set	push
	.set	noat
	SET_HARDFLOAT
	PTR_ADDU $1, \base, \off
	insn_if_mips 0x78000824 | (\wd << 6)
	insn32_if_mm 0x5800080f | (\wd << 6)
	.set	pop
	.endm

	.macro	st_h	wd, off, base
	.set	push
	.set	noat
	SET_HARDFLOAT
	PTR_ADDU $1, \base, \off
	insn_if_mips 0x78000825 | (\wd << 6)
	insn32_if_mm 0x5800081f | (\wd << 6)
	.set	pop
	.endm

	.macro	st_w	wd, off, base
	.set	push
	.set	noat
	SET_HARDFLOAT
	PTR_ADDU $1, \base, \off
	insn_if_mips 0x78000826 | (\wd << 6)
	insn32_if_mm 0x5800082f | (\wd << 6)
	.set	pop
	.endm

	.macro	st_d	wd, off, base
	.set	push
	.set	noat
	SET_HARDFLOAT
	PTR_ADDU $1, \base, \off
	insn_if_mips 0x78000827 | (\wd << 6)
	insn32_if_mm 0x5800083f | (\wd << 6)
	.set	pop
	.endm

	.macro	copy_s_w	ws, n
	.set	push
	.set	noat
	SET_HARDFLOAT
	insn_if_mips 0x78b00059 | (\n << 16) | (\ws << 11)
	insn32_if_mm 0x58b00056 | (\n << 16) | (\ws << 11)
	.set	pop
	.endm

	.macro	copy_s_d	ws, n
	.set	push
	.set	noat
	SET_HARDFLOAT
	insn_if_mips 0x78b80059 | (\n << 16) | (\ws << 11)
	insn32_if_mm 0x58b80056 | (\n << 16) | (\ws << 11)
	.set	pop
	.endm

	.macro	insert_w	wd, n
	.set	push
	.set	noat
	SET_HARDFLOAT
	insn_if_mips 0x79300819 | (\n << 16) | (\wd << 6)
	insn32_if_mm 0x59300816 | (\n << 16) | (\wd << 6)
	.set	pop
	.endm

	.macro	insert_d	wd, n
	.set	push
	.set	noat
	SET_HARDFLOAT
	insn_if_mips 0x79380819 | (\n << 16) | (\wd << 6)
	insn32_if_mm 0x59380816 | (\n << 16) | (\wd << 6)
	.set	pop
	.endm
#endif

#ifdef TOOLCHAIN_SUPPORTS_MSA
#define FPR_BASE_OFFS	THREAD_FPR0
#define FPR_BASE	$1
#else
#define FPR_BASE_OFFS	0
#define FPR_BASE	\thread
#endif

	.macro	msa_save_all	thread
	.set	push
	.set	noat
#ifdef TOOLCHAIN_SUPPORTS_MSA
	PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
#endif
	st_d	 0, THREAD_FPR0  - FPR_BASE_OFFS, FPR_BASE
	st_d	 1, THREAD_FPR1  - FPR_BASE_OFFS, FPR_BASE
	st_d	 2, THREAD_FPR2  - FPR_BASE_OFFS, FPR_BASE
	st_d	 3, THREAD_FPR3  - FPR_BASE_OFFS, FPR_BASE
	st_d	 4, THREAD_FPR4  - FPR_BASE_OFFS, FPR_BASE
	st_d	 5, THREAD_FPR5  - FPR_BASE_OFFS, FPR_BASE
	st_d	 6, THREAD_FPR6  - FPR_BASE_OFFS, FPR_BASE
	st_d	 7, THREAD_FPR7  - FPR_BASE_OFFS, FPR_BASE
	st_d	 8, THREAD_FPR8  - FPR_BASE_OFFS, FPR_BASE
	st_d	 9, THREAD_FPR9  - FPR_BASE_OFFS, FPR_BASE
	st_d	10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
	st_d	11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
	st_d	12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
	st_d	13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
	st_d	14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
	st_d	15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
	st_d	16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
	st_d	17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
	st_d	18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
	st_d	19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
	st_d	20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
	st_d	21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
	st_d	22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
	st_d	23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
	st_d	24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
	st_d	25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
	st_d	26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
	st_d	27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
	st_d	28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
	st_d	29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
	st_d	30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
	st_d	31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
	SET_HARDFLOAT
	_cfcmsa	$1, MSA_CSR
	sw	$1, THREAD_MSA_CSR(\thread)
	.set	pop
	.endm

	.macro	msa_restore_all	thread
	.set	push
	.set	noat
	SET_HARDFLOAT
	lw	$1, THREAD_MSA_CSR(\thread)
	_ctcmsa	MSA_CSR, $1
#ifdef TOOLCHAIN_SUPPORTS_MSA
	PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
#endif
	ld_d	 0, THREAD_FPR0  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 1, THREAD_FPR1  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 2, THREAD_FPR2  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 3, THREAD_FPR3  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 4, THREAD_FPR4  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 5, THREAD_FPR5  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 6, THREAD_FPR6  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 7, THREAD_FPR7  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 8, THREAD_FPR8  - FPR_BASE_OFFS, FPR_BASE
	ld_d	 9, THREAD_FPR9  - FPR_BASE_OFFS, FPR_BASE
	ld_d	10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
	ld_d	11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
	ld_d	12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
	ld_d	13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
	ld_d	14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
	ld_d	15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
	ld_d	16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
	ld_d	17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
	ld_d	18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
	ld_d	19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
	ld_d	20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
	ld_d	21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
	ld_d	22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
	ld_d	23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
	ld_d	24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
	ld_d	25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
	ld_d	26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
	ld_d	27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
	ld_d	28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
	ld_d	29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
	ld_d	30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
	ld_d	31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
	.set pop
	.endm

#undef FPR_BASE_OFFS
#undef FPR_BASE

	.macro	msa_init_upper wd
#ifdef CONFIG_64BIT
	insert_d \wd, 1
#else
	insert_w \wd, 2
	insert_w \wd, 3
#endif
	.endm

	.macro	msa_init_all_upper
	.set	push
	.set	noat
	SET_HARDFLOAT
	not	$1, zero
	msa_init_upper	0
	msa_init_upper	1
	msa_init_upper	2
	msa_init_upper	3
	msa_init_upper	4
	msa_init_upper	5
	msa_init_upper	6
	msa_init_upper	7
	msa_init_upper	8
	msa_init_upper	9
	msa_init_upper	10
	msa_init_upper	11
	msa_init_upper	12
	msa_init_upper	13
	msa_init_upper	14
	msa_init_upper	15
	msa_init_upper	16
	msa_init_upper	17
	msa_init_upper	18
	msa_init_upper	19
	msa_init_upper	20
	msa_init_upper	21
	msa_init_upper	22
	msa_init_upper	23
	msa_init_upper	24
	msa_init_upper	25
	msa_init_upper	26
	msa_init_upper	27
	msa_init_upper	28
	msa_init_upper	29
	msa_init_upper	30
	msa_init_upper	31
	.set	pop
	.endm

#endif /* _ASM_ASMMACRO_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2003 Ralf Baechle
	7	*/
	8	#ifndef _ASM_ASMMACRO_H
	9	#define _ASM_ASMMACRO_H
42a3b4f2	10
1da177e4	11	#include <asm/hazards.h>
71ca7588	12	#include <asm/asm-offsets.h>
f7a46fa7	13	#include <asm/msa.h>
42a3b4f2	14
875d43e7	15	#ifdef CONFIG_32BIT
1da177e4 LT	16	#include <asm/asmmacro-32.h>
1da177e4 LT	17	#endif
875d43e7	18	#ifdef CONFIG_64BIT
1da177e4 LT	19	#include <asm/asmmacro-64.h>
1da177e4 LT	20	#endif
41c594ab	21
c7fd89a6 JH	22	/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
	23	#undef fp
	24
6e1b29c3 JH	25	/*
	26	* Helper macros for generating raw instruction encodings.
	27	*/
	28	#ifdef CONFIG_CPU_MICROMIPS
	29	.macro insn32_if_mm enc
	30	.insn
	31	.hword ((\enc) >> 16)
	32	.hword ((\enc) & 0xffff)
	33	.endm
	34
	35	.macro insn_if_mips enc
	36	.endm
	37	#else
	38	.macro insn32_if_mm enc
	39	.endm
	40
	41	.macro insn_if_mips enc
	42	.insn
	43	.word (\enc)
	44	.endm
	45	#endif
	46
226da55f	47	#if defined(CONFIG_CPU_MIPSR2) \|\| defined(CONFIG_CPU_MIPSR6)
b6354db5 DD	48	.macro local_irq_enable reg=t0
	49	ei
	50	irq_enable_hazard
	51	.endm
	52
	53	.macro local_irq_disable reg=t0
	54	di
	55	irq_disable_hazard
	56	.endm
41c594ab	57	#else
1da177e4 LT	58	.macro local_irq_enable reg=t0
	59	mfc0 \reg, CP0_STATUS
	60	ori \reg, \reg, 1
	61	mtc0 \reg, CP0_STATUS
	62	irq_enable_hazard
	63	.endm
	64
	65	.macro local_irq_disable reg=t0
71ca7588 JQ	66	#ifdef CONFIG_PREEMPT
	67	lw \reg, TI_PRE_COUNT($28)
	68	addi \reg, \reg, 1
	69	sw \reg, TI_PRE_COUNT($28)
	70	#endif
1da177e4 LT	71	mfc0 \reg, CP0_STATUS
	72	ori \reg, \reg, 1
	73	xori \reg, \reg, 1
	74	mtc0 \reg, CP0_STATUS
	75	irq_disable_hazard
71ca7588 JQ	76	#ifdef CONFIG_PREEMPT
	77	lw \reg, TI_PRE_COUNT($28)
	78	addi \reg, \reg, -1
	79	sw \reg, TI_PRE_COUNT($28)
	80	#endif
1da177e4	81	.endm
b633648c	82	#endif /* CONFIG_CPU_MIPSR2 */
1da177e4	83
597ce172	84	.macro fpu_save_16even thread tmp=t0
842dfc11 ML	85	.set push
842dfc11 ML	86	SET_HARDFLOAT
597ce172	87	cfc1 \tmp, fcr31
466aec5f JH	88	sdc1 $f0, THREAD_FPR0(\thread)
	89	sdc1 $f2, THREAD_FPR2(\thread)
	90	sdc1 $f4, THREAD_FPR4(\thread)
	91	sdc1 $f6, THREAD_FPR6(\thread)
	92	sdc1 $f8, THREAD_FPR8(\thread)
	93	sdc1 $f10, THREAD_FPR10(\thread)
	94	sdc1 $f12, THREAD_FPR12(\thread)
	95	sdc1 $f14, THREAD_FPR14(\thread)
	96	sdc1 $f16, THREAD_FPR16(\thread)
	97	sdc1 $f18, THREAD_FPR18(\thread)
	98	sdc1 $f20, THREAD_FPR20(\thread)
	99	sdc1 $f22, THREAD_FPR22(\thread)
	100	sdc1 $f24, THREAD_FPR24(\thread)
	101	sdc1 $f26, THREAD_FPR26(\thread)
	102	sdc1 $f28, THREAD_FPR28(\thread)
	103	sdc1 $f30, THREAD_FPR30(\thread)
597ce172	104	sw \tmp, THREAD_FCR31(\thread)
842dfc11	105	.set pop
597ce172 PB	106	.endm
	107
	108	.macro fpu_save_16odd thread
	109	.set push
	110	.set mips64r2
c7fd89a6	111	.set fp=64
842dfc11	112	SET_HARDFLOAT
466aec5f JH	113	sdc1 $f1, THREAD_FPR1(\thread)
	114	sdc1 $f3, THREAD_FPR3(\thread)
	115	sdc1 $f5, THREAD_FPR5(\thread)
	116	sdc1 $f7, THREAD_FPR7(\thread)
	117	sdc1 $f9, THREAD_FPR9(\thread)
	118	sdc1 $f11, THREAD_FPR11(\thread)
	119	sdc1 $f13, THREAD_FPR13(\thread)
	120	sdc1 $f15, THREAD_FPR15(\thread)
	121	sdc1 $f17, THREAD_FPR17(\thread)
	122	sdc1 $f19, THREAD_FPR19(\thread)
	123	sdc1 $f21, THREAD_FPR21(\thread)
	124	sdc1 $f23, THREAD_FPR23(\thread)
	125	sdc1 $f25, THREAD_FPR25(\thread)
	126	sdc1 $f27, THREAD_FPR27(\thread)
	127	sdc1 $f29, THREAD_FPR29(\thread)
	128	sdc1 $f31, THREAD_FPR31(\thread)
597ce172 PB	129	.set pop
	130	.endm
	131
	132	.macro fpu_save_double thread status tmp
22b8ba76 JH	133	#if defined(CONFIG_64BIT) \|\| defined(CONFIG_CPU_MIPSR2) \|\| \
22b8ba76 JH	134	defined(CONFIG_CPU_MIPSR6)
597ce172 PB	135	sll \tmp, \status, 5
	136	bgez \tmp, 10f
	137	fpu_save_16odd \thread
	138	10:
	139	#endif
	140	fpu_save_16even \thread \tmp
	141	.endm
	142
	143	.macro fpu_restore_16even thread tmp=t0
842dfc11 ML	144	.set push
842dfc11 ML	145	SET_HARDFLOAT
597ce172	146	lw \tmp, THREAD_FCR31(\thread)
466aec5f JH	147	ldc1 $f0, THREAD_FPR0(\thread)
	148	ldc1 $f2, THREAD_FPR2(\thread)
	149	ldc1 $f4, THREAD_FPR4(\thread)
	150	ldc1 $f6, THREAD_FPR6(\thread)
	151	ldc1 $f8, THREAD_FPR8(\thread)
	152	ldc1 $f10, THREAD_FPR10(\thread)
	153	ldc1 $f12, THREAD_FPR12(\thread)
	154	ldc1 $f14, THREAD_FPR14(\thread)
	155	ldc1 $f16, THREAD_FPR16(\thread)
	156	ldc1 $f18, THREAD_FPR18(\thread)
	157	ldc1 $f20, THREAD_FPR20(\thread)
	158	ldc1 $f22, THREAD_FPR22(\thread)
	159	ldc1 $f24, THREAD_FPR24(\thread)
	160	ldc1 $f26, THREAD_FPR26(\thread)
	161	ldc1 $f28, THREAD_FPR28(\thread)
	162	ldc1 $f30, THREAD_FPR30(\thread)
597ce172	163	ctc1 \tmp, fcr31
3cbc6fc9	164	.set pop
597ce172 PB	165	.endm
	166
	167	.macro fpu_restore_16odd thread
	168	.set push
	169	.set mips64r2
c7fd89a6	170	.set fp=64
842dfc11	171	SET_HARDFLOAT
466aec5f JH	172	ldc1 $f1, THREAD_FPR1(\thread)
	173	ldc1 $f3, THREAD_FPR3(\thread)
	174	ldc1 $f5, THREAD_FPR5(\thread)
	175	ldc1 $f7, THREAD_FPR7(\thread)
	176	ldc1 $f9, THREAD_FPR9(\thread)
	177	ldc1 $f11, THREAD_FPR11(\thread)
	178	ldc1 $f13, THREAD_FPR13(\thread)
	179	ldc1 $f15, THREAD_FPR15(\thread)
	180	ldc1 $f17, THREAD_FPR17(\thread)
	181	ldc1 $f19, THREAD_FPR19(\thread)
	182	ldc1 $f21, THREAD_FPR21(\thread)
	183	ldc1 $f23, THREAD_FPR23(\thread)
	184	ldc1 $f25, THREAD_FPR25(\thread)
	185	ldc1 $f27, THREAD_FPR27(\thread)
	186	ldc1 $f29, THREAD_FPR29(\thread)
	187	ldc1 $f31, THREAD_FPR31(\thread)
597ce172 PB	188	.set pop
	189	.endm
	190
	191	.macro fpu_restore_double thread status tmp
22b8ba76 JH	192	#if defined(CONFIG_64BIT) \|\| defined(CONFIG_CPU_MIPSR2) \|\| \
22b8ba76 JH	193	defined(CONFIG_CPU_MIPSR6)
597ce172 PB	194	sll \tmp, \status, 5
	195	bgez \tmp, 10f # 16 register mode?
	196
	197	fpu_restore_16odd \thread
	198	10:
	199	#endif
	200	fpu_restore_16even \thread \tmp
	201	.endm
	202
207083b1	203	#if defined(CONFIG_CPU_MIPSR2) \|\| defined(CONFIG_CPU_MIPSR6)
1d688087 PB	204	.macro _EXT rd, rs, p, s
	205	ext \rd, \rs, \p, \s
	206	.endm
207083b1	207	#else /* !CONFIG_CPU_MIPSR2 \|\| !CONFIG_CPU_MIPSR6 */
1d688087 PB	208	.macro _EXT rd, rs, p, s
	209	srl \rd, \rs, \p
	210	andi \rd, \rd, (1 << \s) - 1
	211	.endm
207083b1	212	#endif /* !CONFIG_CPU_MIPSR2 \|\| !CONFIG_CPU_MIPSR6 */
1d688087	213
41c594ab RB	214	/*
	215	* Temporary until all gas have MT ASE support
	216	*/
	217	.macro DMT reg=0
49a89efb	218	.word 0x41600bc1 \| (\reg << 16)
41c594ab RB	219	.endm
	220
	221	.macro EMT reg=0
49a89efb	222	.word 0x41600be1 \| (\reg << 16)
41c594ab RB	223	.endm
	224
	225	.macro DVPE reg=0
49a89efb	226	.word 0x41600001 \| (\reg << 16)
41c594ab RB	227	.endm
	228
	229	.macro EVPE reg=0
49a89efb	230	.word 0x41600021 \| (\reg << 16)
41c594ab RB	231	.endm
	232
	233	.macro MFTR rt=0, rd=0, u=0, sel=0
49a89efb	234	.word 0x41000000 \| (\rt << 16) \| (\rd << 11) \| (\u << 5) \| (\sel)
41c594ab RB	235	.endm
	236
	237	.macro MTTR rt=0, rd=0, u=0, sel=0
49a89efb	238	.word 0x41800000 \| (\rt << 16) \| (\rd << 11) \| (\u << 5) \| (\sel)
41c594ab RB	239	.endm
41c594ab RB	240
7f65afb9	241	#ifdef TOOLCHAIN_SUPPORTS_MSA
e1bebbab PB	242	.macro _cfcmsa rd, cs
	243	.set push
	244	.set mips32r2
2bd7bc25	245	.set fp=64
e1bebbab PB	246	.set msa
	247	cfcmsa \rd, $\cs
	248	.set pop
	249	.endm
	250
	251	.macro _ctcmsa cd, rs
	252	.set push
	253	.set mips32r2
2bd7bc25	254	.set fp=64
e1bebbab PB	255	.set msa
	256	ctcmsa $\cd, \rs
	257	.set pop
	258	.endm
	259
6b35e114 PB	260	.macro ld_b wd, off, base
	261	.set push
	262	.set mips32r2
92e9953c	263	.set fp=64
6b35e114 PB	264	.set msa
	265	ld.b $w\wd, \off(\base)
	266	.set pop
	267	.endm
	268
	269	.macro ld_h wd, off, base
	270	.set push
	271	.set mips32r2
92e9953c	272	.set fp=64
6b35e114 PB	273	.set msa
	274	ld.h $w\wd, \off(\base)
	275	.set pop
	276	.endm
	277
	278	.macro ld_w wd, off, base
	279	.set push
	280	.set mips32r2
92e9953c	281	.set fp=64
6b35e114 PB	282	.set msa
	283	ld.w $w\wd, \off(\base)
	284	.set pop
	285	.endm
	286
7f65afb9 PB	287	.macro ld_d wd, off, base
	288	.set push
	289	.set mips32r2
2bd7bc25	290	.set fp=64
7f65afb9 PB	291	.set msa
	292	ld.d $w\wd, \off(\base)
	293	.set pop
	294	.endm
	295
6b35e114 PB	296	.macro st_b wd, off, base
	297	.set push
	298	.set mips32r2
92e9953c	299	.set fp=64
6b35e114 PB	300	.set msa
	301	st.b $w\wd, \off(\base)
	302	.set pop
	303	.endm
	304
	305	.macro st_h wd, off, base
	306	.set push
	307	.set mips32r2
92e9953c	308	.set fp=64
6b35e114 PB	309	.set msa
	310	st.h $w\wd, \off(\base)
	311	.set pop
	312	.endm
	313
	314	.macro st_w wd, off, base
	315	.set push
	316	.set mips32r2
92e9953c	317	.set fp=64
6b35e114 PB	318	.set msa
	319	st.w $w\wd, \off(\base)
	320	.set pop
	321	.endm
	322
7f65afb9 PB	323	.macro st_d wd, off, base
	324	.set push
	325	.set mips32r2
2bd7bc25	326	.set fp=64
7f65afb9 PB	327	.set msa
	328	st.d $w\wd, \off(\base)
	329	.set pop
	330	.endm
	331
8a3c8b48	332	.macro copy_s_w ws, n
7f65afb9 PB	333	.set push
7f65afb9 PB	334	.set mips32r2
2bd7bc25	335	.set fp=64
7f65afb9	336	.set msa
8a3c8b48	337	copy_s.w $1, $w\ws[\n]
7f65afb9 PB	338	.set pop
	339	.endm
	340
8a3c8b48	341	.macro copy_s_d ws, n
7f65afb9 PB	342	.set push
7f65afb9 PB	343	.set mips64r2
2bd7bc25	344	.set fp=64
7f65afb9	345	.set msa
8a3c8b48	346	copy_s.d $1, $w\ws[\n]
7f65afb9 PB	347	.set pop
	348	.endm
	349
f23ce388	350	.macro insert_w wd, n
7f65afb9 PB	351	.set push
7f65afb9 PB	352	.set mips32r2
2bd7bc25	353	.set fp=64
7f65afb9	354	.set msa
f23ce388	355	insert.w $w\wd[\n], $1
7f65afb9 PB	356	.set pop
	357	.endm
	358
f23ce388	359	.macro insert_d wd, n
7f65afb9 PB	360	.set push
7f65afb9 PB	361	.set mips64r2
2bd7bc25	362	.set fp=64
7f65afb9	363	.set msa
f23ce388	364	insert.d $w\wd[\n], $1
7f65afb9 PB	365	.set pop
	366	.endm
	367	#else
d96cc3d1	368
7f65afb9 PB	369	/*
	370	* Temporary until all toolchains in use include MSA support.
	371	*/
e1bebbab	372	.macro _cfcmsa rd, cs
7f65afb9 PB	373	.set push
7f65afb9 PB	374	.set noat
842dfc11	375	SET_HARDFLOAT
6e1b29c3 JH	376	insn_if_mips 0x787e0059 \| (\cs << 11)
6e1b29c3 JH	377	insn32_if_mm 0x587e0056 \| (\cs << 11)
7f65afb9 PB	378	move \rd, $1
	379	.set pop
	380	.endm
	381
e1bebbab	382	.macro _ctcmsa cd, rs
7f65afb9 PB	383	.set push
7f65afb9 PB	384	.set noat
842dfc11	385	SET_HARDFLOAT
7f65afb9	386	move $1, \rs
6e1b29c3 JH	387	insn_if_mips 0x783e0819 \| (\cd << 6)
6e1b29c3 JH	388	insn32_if_mm 0x583e0816 \| (\cd << 6)
7f65afb9 PB	389	.set pop
	390	.endm
	391
6b35e114 PB	392	.macro ld_b wd, off, base
	393	.set push
	394	.set noat
	395	SET_HARDFLOAT
ea168857	396	PTR_ADDU $1, \base, \off
6e1b29c3 JH	397	insn_if_mips 0x78000820 \| (\wd << 6)
6e1b29c3 JH	398	insn32_if_mm 0x58000807 \| (\wd << 6)
6b35e114 PB	399	.set pop
	400	.endm
	401
	402	.macro ld_h wd, off, base
	403	.set push
	404	.set noat
	405	SET_HARDFLOAT
ea168857	406	PTR_ADDU $1, \base, \off
6e1b29c3 JH	407	insn_if_mips 0x78000821 \| (\wd << 6)
6e1b29c3 JH	408	insn32_if_mm 0x58000817 \| (\wd << 6)
6b35e114 PB	409	.set pop
	410	.endm
	411
	412	.macro ld_w wd, off, base
	413	.set push
	414	.set noat
	415	SET_HARDFLOAT
ea168857	416	PTR_ADDU $1, \base, \off
6e1b29c3 JH	417	insn_if_mips 0x78000822 \| (\wd << 6)
6e1b29c3 JH	418	insn32_if_mm 0x58000827 \| (\wd << 6)
6b35e114 PB	419	.set pop
	420	.endm
	421
7f65afb9 PB	422	.macro ld_d wd, off, base
	423	.set push
	424	.set noat
842dfc11	425	SET_HARDFLOAT
ea168857	426	PTR_ADDU $1, \base, \off
6e1b29c3 JH	427	insn_if_mips 0x78000823 \| (\wd << 6)
6e1b29c3 JH	428	insn32_if_mm 0x58000837 \| (\wd << 6)
7f65afb9 PB	429	.set pop
	430	.endm
	431
6b35e114 PB	432	.macro st_b wd, off, base
	433	.set push
	434	.set noat
	435	SET_HARDFLOAT
ea168857	436	PTR_ADDU $1, \base, \off
6e1b29c3 JH	437	insn_if_mips 0x78000824 \| (\wd << 6)
6e1b29c3 JH	438	insn32_if_mm 0x5800080f \| (\wd << 6)
6b35e114 PB	439	.set pop
	440	.endm
	441
	442	.macro st_h wd, off, base
	443	.set push
	444	.set noat
	445	SET_HARDFLOAT
ea168857	446	PTR_ADDU $1, \base, \off
6e1b29c3 JH	447	insn_if_mips 0x78000825 \| (\wd << 6)
6e1b29c3 JH	448	insn32_if_mm 0x5800081f \| (\wd << 6)
6b35e114 PB	449	.set pop
	450	.endm
	451
	452	.macro st_w wd, off, base
	453	.set push
	454	.set noat
	455	SET_HARDFLOAT
ea168857	456	PTR_ADDU $1, \base, \off
6e1b29c3 JH	457	insn_if_mips 0x78000826 \| (\wd << 6)
6e1b29c3 JH	458	insn32_if_mm 0x5800082f \| (\wd << 6)
6b35e114 PB	459	.set pop
	460	.endm
	461
7f65afb9 PB	462	.macro st_d wd, off, base
	463	.set push
	464	.set noat
842dfc11	465	SET_HARDFLOAT
ea168857	466	PTR_ADDU $1, \base, \off
6e1b29c3 JH	467	insn_if_mips 0x78000827 \| (\wd << 6)
6e1b29c3 JH	468	insn32_if_mm 0x5800083f \| (\wd << 6)
7f65afb9 PB	469	.set pop
	470	.endm
	471
8a3c8b48	472	.macro copy_s_w ws, n
7f65afb9 PB	473	.set push
7f65afb9 PB	474	.set noat
842dfc11	475	SET_HARDFLOAT
6e1b29c3 JH	476	insn_if_mips 0x78b00059 \| (\n << 16) \| (\ws << 11)
6e1b29c3 JH	477	insn32_if_mm 0x58b00056 \| (\n << 16) \| (\ws << 11)
7f65afb9 PB	478	.set pop
	479	.endm
	480
8a3c8b48	481	.macro copy_s_d ws, n
7f65afb9 PB	482	.set push
7f65afb9 PB	483	.set noat
842dfc11	484	SET_HARDFLOAT
6e1b29c3 JH	485	insn_if_mips 0x78b80059 \| (\n << 16) \| (\ws << 11)
6e1b29c3 JH	486	insn32_if_mm 0x58b80056 \| (\n << 16) \| (\ws << 11)
7f65afb9 PB	487	.set pop
	488	.endm
	489
f23ce388	490	.macro insert_w wd, n
7f65afb9 PB	491	.set push
7f65afb9 PB	492	.set noat
842dfc11	493	SET_HARDFLOAT
6e1b29c3 JH	494	insn_if_mips 0x79300819 \| (\n << 16) \| (\wd << 6)
6e1b29c3 JH	495	insn32_if_mm 0x59300816 \| (\n << 16) \| (\wd << 6)
7f65afb9 PB	496	.set pop
	497	.endm
	498
f23ce388	499	.macro insert_d wd, n
7f65afb9 PB	500	.set push
7f65afb9 PB	501	.set noat
842dfc11	502	SET_HARDFLOAT
6e1b29c3 JH	503	insn_if_mips 0x79380819 \| (\n << 16) \| (\wd << 6)
6e1b29c3 JH	504	insn32_if_mm 0x59380816 \| (\n << 16) \| (\wd << 6)
7f65afb9 PB	505	.set pop
	506	.endm
	507	#endif
	508
143e93d7 JH	509	#ifdef TOOLCHAIN_SUPPORTS_MSA
	510	#define FPR_BASE_OFFS THREAD_FPR0
	511	#define FPR_BASE $1
	512	#else
	513	#define FPR_BASE_OFFS 0
	514	#define FPR_BASE \thread
	515	#endif
	516
1db1af84	517	.macro msa_save_all thread
f7a46fa7 PB	518	.set push
f7a46fa7 PB	519	.set noat
143e93d7 JH	520	#ifdef TOOLCHAIN_SUPPORTS_MSA
	521	PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
	522	#endif
	523	st_d 0, THREAD_FPR0 - FPR_BASE_OFFS, FPR_BASE
	524	st_d 1, THREAD_FPR1 - FPR_BASE_OFFS, FPR_BASE
	525	st_d 2, THREAD_FPR2 - FPR_BASE_OFFS, FPR_BASE
	526	st_d 3, THREAD_FPR3 - FPR_BASE_OFFS, FPR_BASE
	527	st_d 4, THREAD_FPR4 - FPR_BASE_OFFS, FPR_BASE
	528	st_d 5, THREAD_FPR5 - FPR_BASE_OFFS, FPR_BASE
	529	st_d 6, THREAD_FPR6 - FPR_BASE_OFFS, FPR_BASE
	530	st_d 7, THREAD_FPR7 - FPR_BASE_OFFS, FPR_BASE
	531	st_d 8, THREAD_FPR8 - FPR_BASE_OFFS, FPR_BASE
	532	st_d 9, THREAD_FPR9 - FPR_BASE_OFFS, FPR_BASE
	533	st_d 10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
	534	st_d 11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
	535	st_d 12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
	536	st_d 13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
	537	st_d 14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
	538	st_d 15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
	539	st_d 16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
	540	st_d 17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
	541	st_d 18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
	542	st_d 19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
	543	st_d 20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
	544	st_d 21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
	545	st_d 22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
	546	st_d 23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
	547	st_d 24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
	548	st_d 25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
	549	st_d 26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
	550	st_d 27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
	551	st_d 28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
	552	st_d 29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
	553	st_d 30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
	554	st_d 31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
842dfc11	555	SET_HARDFLOAT
e1bebbab	556	_cfcmsa $1, MSA_CSR
f7a46fa7 PB	557	sw $1, THREAD_MSA_CSR(\thread)
f7a46fa7 PB	558	.set pop
1db1af84 PB	559	.endm
	560
	561	.macro msa_restore_all thread
f7a46fa7 PB	562	.set push
f7a46fa7 PB	563	.set noat
842dfc11	564	SET_HARDFLOAT
f7a46fa7	565	lw $1, THREAD_MSA_CSR(\thread)
e1bebbab	566	_ctcmsa MSA_CSR, $1
143e93d7 JH	567	#ifdef TOOLCHAIN_SUPPORTS_MSA
	568	PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS
	569	#endif
	570	ld_d 0, THREAD_FPR0 - FPR_BASE_OFFS, FPR_BASE
	571	ld_d 1, THREAD_FPR1 - FPR_BASE_OFFS, FPR_BASE
	572	ld_d 2, THREAD_FPR2 - FPR_BASE_OFFS, FPR_BASE
	573	ld_d 3, THREAD_FPR3 - FPR_BASE_OFFS, FPR_BASE
	574	ld_d 4, THREAD_FPR4 - FPR_BASE_OFFS, FPR_BASE
	575	ld_d 5, THREAD_FPR5 - FPR_BASE_OFFS, FPR_BASE
	576	ld_d 6, THREAD_FPR6 - FPR_BASE_OFFS, FPR_BASE
	577	ld_d 7, THREAD_FPR7 - FPR_BASE_OFFS, FPR_BASE
	578	ld_d 8, THREAD_FPR8 - FPR_BASE_OFFS, FPR_BASE
	579	ld_d 9, THREAD_FPR9 - FPR_BASE_OFFS, FPR_BASE
	580	ld_d 10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE
	581	ld_d 11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE
	582	ld_d 12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE
	583	ld_d 13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE
	584	ld_d 14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE
	585	ld_d 15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE
	586	ld_d 16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE
	587	ld_d 17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE
	588	ld_d 18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE
	589	ld_d 19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE
	590	ld_d 20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE
	591	ld_d 21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE
	592	ld_d 22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE
	593	ld_d 23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE
	594	ld_d 24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE
	595	ld_d 25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE
	596	ld_d 26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE
	597	ld_d 27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE
	598	ld_d 28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE
	599	ld_d 29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE
	600	ld_d 30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE
	601	ld_d 31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE
	602	.set pop
	603	.endm
	604
	605	#undef FPR_BASE_OFFS
	606	#undef FPR_BASE
1db1af84	607
c9017757 PB	608	.macro msa_init_upper wd
	609	#ifdef CONFIG_64BIT
	610	insert_d \wd, 1
	611	#else
	612	insert_w \wd, 2
	613	insert_w \wd, 3
	614	#endif
c9017757 PB	615	.endm
	616
	617	.macro msa_init_all_upper
	618	.set push
	619	.set noat
842dfc11	620	SET_HARDFLOAT
c9017757 PB	621	not $1, zero
c9017757 PB	622	msa_init_upper 0
a3a49810 PB	623	msa_init_upper 1
	624	msa_init_upper 2
	625	msa_init_upper 3
	626	msa_init_upper 4
	627	msa_init_upper 5
	628	msa_init_upper 6
	629	msa_init_upper 7
	630	msa_init_upper 8
	631	msa_init_upper 9
	632	msa_init_upper 10
	633	msa_init_upper 11
	634	msa_init_upper 12
	635	msa_init_upper 13
	636	msa_init_upper 14
	637	msa_init_upper 15
	638	msa_init_upper 16
	639	msa_init_upper 17
	640	msa_init_upper 18
	641	msa_init_upper 19
	642	msa_init_upper 20
	643	msa_init_upper 21
	644	msa_init_upper 22
	645	msa_init_upper 23
	646	msa_init_upper 24
	647	msa_init_upper 25
	648	msa_init_upper 26
	649	msa_init_upper 27
	650	msa_init_upper 28
	651	msa_init_upper 29
	652	msa_init_upper 30
	653	msa_init_upper 31
c9017757 PB	654	.set pop
	655	.endm
	656
1da177e4	657	#endif /* _ASM_ASMMACRO_H */