[mirror_ubuntu-zesty-kernel.git] / arch / mips / include / asm / barrier.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2006 by Ralf Baechle (ralf@linux-mips.org)
 */
#ifndef __ASM_BARRIER_H
#define __ASM_BARRIER_H

#include <asm/addrspace.h>

/*
 * Sync types defined by the MIPS architecture (document MD00087 table 6.5)
 * These values are used with the sync instruction to perform memory barriers.
 * Types of ordering guarantees available through the SYNC instruction:
 * - Completion Barriers
 * - Ordering Barriers
 * As compared to the completion barrier, the ordering barrier is a
 * lighter-weight operation as it does not require the specified instructions
 * before the SYNC to be already completed. Instead it only requires that those
 * specified instructions which are subsequent to the SYNC in the instruction
 * stream are never re-ordered for processing ahead of the specified
 * instructions which are before the SYNC in the instruction stream.
 * This potentially reduces how many cycles the barrier instruction must stall
 * before it completes.
 * Implementations that do not use any of the non-zero values of stype to define
 * different barriers, such as ordering barriers, must make those stype values
 * act the same as stype zero.
 */

/*
 * Completion barriers:
 * - Every synchronizable specified memory instruction (loads or stores or both)
 *   that occurs in the instruction stream before the SYNC instruction must be
 *   already globally performed before any synchronizable specified memory
 *   instructions that occur after the SYNC are allowed to be performed, with
 *   respect to any other processor or coherent I/O module.
 *
 * - The barrier does not guarantee the order in which instruction fetches are
 *   performed.
 *
 * - A stype value of zero will always be defined such that it performs the most
 *   complete set of synchronization operations that are defined.This means
 *   stype zero always does a completion barrier that affects both loads and
 *   stores preceding the SYNC instruction and both loads and stores that are
 *   subsequent to the SYNC instruction. Non-zero values of stype may be defined
 *   by the architecture or specific implementations to perform synchronization
 *   behaviors that are less complete than that of stype zero. If an
 *   implementation does not use one of these non-zero values to define a
 *   different synchronization behavior, then that non-zero value of stype must
 *   act the same as stype zero completion barrier. This allows software written
 *   for an implementation with a lighter-weight barrier to work on another
 *   implementation which only implements the stype zero completion barrier.
 *
 * - A completion barrier is required, potentially in conjunction with SSNOP (in
 *   Release 1 of the Architecture) or EHB (in Release 2 of the Architecture),
 *   to guarantee that memory reference results are visible across operating
 *   mode changes. For example, a completion barrier is required on some
 *   implementations on entry to and exit from Debug Mode to guarantee that
 *   memory effects are handled correctly.
 */

/*
 * stype 0 - A completion barrier that affects preceding loads and stores and
 * subsequent loads and stores.
 * Older instructions which must reach the load/store ordering point before the
 * SYNC instruction completes: Loads, Stores
 * Younger instructions which must reach the load/store ordering point only
 * after the SYNC instruction completes: Loads, Stores
 * Older instructions which must be globally performed when the SYNC instruction
 * completes: Loads, Stores
 */
#define STYPE_SYNC 0x0

/*
 * Ordering barriers:
 * - Every synchronizable specified memory instruction (loads or stores or both)
 *   that occurs in the instruction stream before the SYNC instruction must
 *   reach a stage in the load/store datapath after which no instruction
 *   re-ordering is possible before any synchronizable specified memory
 *   instruction which occurs after the SYNC instruction in the instruction
 *   stream reaches the same stage in the load/store datapath.
 *
 * - If any memory instruction before the SYNC instruction in program order,
 *   generates a memory request to the external memory and any memory
 *   instruction after the SYNC instruction in program order also generates a
 *   memory request to external memory, the memory request belonging to the
 *   older instruction must be globally performed before the time the memory
 *   request belonging to the younger instruction is globally performed.
 *
 * - The barrier does not guarantee the order in which instruction fetches are
 *   performed.
 */

/*
 * stype 0x10 - An ordering barrier that affects preceding loads and stores and
 * subsequent loads and stores.
 * Older instructions which must reach the load/store ordering point before the
 * SYNC instruction completes: Loads, Stores
 * Younger instructions which must reach the load/store ordering point only
 * after the SYNC instruction completes: Loads, Stores
 * Older instructions which must be globally performed when the SYNC instruction
 * completes: N/A
 */
#define STYPE_SYNC_MB 0x10


#ifdef CONFIG_CPU_HAS_SYNC
#define __sync()				\
	__asm__ __volatile__(			\
		".set	push\n\t"		\
		".set	noreorder\n\t"		\
		".set	mips2\n\t"		\
		"sync\n\t"			\
		".set	pop"			\
		: /* no output */		\
		: /* no input */		\
		: "memory")
#else
#define __sync()	do { } while(0)
#endif

#define __fast_iob()				\
	__asm__ __volatile__(			\
		".set	push\n\t"		\
		".set	noreorder\n\t"		\
		"lw	$0,%0\n\t"		\
		"nop\n\t"			\
		".set	pop"			\
		: /* no output */		\
		: "m" (*(int *)CKSEG1)		\
		: "memory")
#ifdef CONFIG_CPU_CAVIUM_OCTEON
# define OCTEON_SYNCW_STR	".set push\n.set arch=octeon\nsyncw\nsyncw\n.set pop\n"
# define __syncw()	__asm__ __volatile__(OCTEON_SYNCW_STR : : : "memory")

# define fast_wmb()	__syncw()
# define fast_rmb()	barrier()
# define fast_mb()	__sync()
# define fast_iob()	do { } while (0)
#else /* ! CONFIG_CPU_CAVIUM_OCTEON */
# define fast_wmb()	__sync()
# define fast_rmb()	__sync()
# define fast_mb()	__sync()
# ifdef CONFIG_SGI_IP28
#  define fast_iob()				\
	__asm__ __volatile__(			\
		".set	push\n\t"		\
		".set	noreorder\n\t"		\
		"lw	$0,%0\n\t"		\
		"sync\n\t"			\
		"lw	$0,%0\n\t"		\
		".set	pop"			\
		: /* no output */		\
		: "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \
		: "memory")
# else
#  define fast_iob()				\
	do {					\
		__sync();			\
		__fast_iob();			\
	} while (0)
# endif
#endif /* CONFIG_CPU_CAVIUM_OCTEON */

#ifdef CONFIG_CPU_HAS_WB

#include <asm/wbflush.h>

#define mb()		wbflush()
#define iob()		wbflush()

#else /* !CONFIG_CPU_HAS_WB */

#define mb()		fast_mb()
#define iob()		fast_iob()

#endif /* !CONFIG_CPU_HAS_WB */

#define wmb()		fast_wmb()
#define rmb()		fast_rmb()

#if defined(CONFIG_WEAK_ORDERING)
# ifdef CONFIG_CPU_CAVIUM_OCTEON
#  define __smp_mb()	__sync()
#  define __smp_rmb()	barrier()
#  define __smp_wmb()	__syncw()
# else
#  define __smp_mb()	__asm__ __volatile__("sync" : : :"memory")
#  define __smp_rmb()	__asm__ __volatile__("sync" : : :"memory")
#  define __smp_wmb()	__asm__ __volatile__("sync" : : :"memory")
# endif
#else
#define __smp_mb()	barrier()
#define __smp_rmb()	barrier()
#define __smp_wmb()	barrier()
#endif

#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP)
#define __WEAK_LLSC_MB		"	sync	\n"
#else
#define __WEAK_LLSC_MB		"		\n"
#endif

#define smp_llsc_mb()	__asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")

#ifdef CONFIG_CPU_CAVIUM_OCTEON
#define smp_mb__before_llsc() smp_wmb()
#define __smp_mb__before_llsc() __smp_wmb()
/* Cause previous writes to become visible on all CPUs as soon as possible */
#define nudge_writes() __asm__ __volatile__(".set push\n\t"		\
					    ".set arch=octeon\n\t"	\
					    "syncw\n\t"			\
					    ".set pop" : : : "memory")
#else
#define smp_mb__before_llsc() smp_llsc_mb()
#define __smp_mb__before_llsc() smp_llsc_mb()
#define nudge_writes() mb()
#endif

#define __smp_mb__before_atomic()	__smp_mb__before_llsc()
#define __smp_mb__after_atomic()	smp_llsc_mb()

#include <asm-generic/barrier.h>

#endif /* __ASM_BARRIER_H */
Commit	Line	Data
0004a9df RB	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2006 by Ralf Baechle (ralf@linux-mips.org)
	7	*/
	8	#ifndef __ASM_BARRIER_H
	9	#define __ASM_BARRIER_H
	10
b81947c6 DH	11	#include <asm/addrspace.h>
b81947c6 DH	12
6622ada3 MR	13	/*
	14	* Sync types defined by the MIPS architecture (document MD00087 table 6.5)
	15	* These values are used with the sync instruction to perform memory barriers.
	16	* Types of ordering guarantees available through the SYNC instruction:
	17	* - Completion Barriers
	18	* - Ordering Barriers
	19	* As compared to the completion barrier, the ordering barrier is a
	20	* lighter-weight operation as it does not require the specified instructions
	21	* before the SYNC to be already completed. Instead it only requires that those
	22	* specified instructions which are subsequent to the SYNC in the instruction
	23	* stream are never re-ordered for processing ahead of the specified
	24	* instructions which are before the SYNC in the instruction stream.
	25	* This potentially reduces how many cycles the barrier instruction must stall
	26	* before it completes.
	27	* Implementations that do not use any of the non-zero values of stype to define
	28	* different barriers, such as ordering barriers, must make those stype values
	29	* act the same as stype zero.
	30	*/
	31
	32	/*
	33	* Completion barriers:
	34	* - Every synchronizable specified memory instruction (loads or stores or both)
	35	* that occurs in the instruction stream before the SYNC instruction must be
	36	* already globally performed before any synchronizable specified memory
	37	* instructions that occur after the SYNC are allowed to be performed, with
	38	* respect to any other processor or coherent I/O module.
	39	*
	40	* - The barrier does not guarantee the order in which instruction fetches are
	41	* performed.
	42	*
	43	* - A stype value of zero will always be defined such that it performs the most
	44	* complete set of synchronization operations that are defined.This means
	45	* stype zero always does a completion barrier that affects both loads and
	46	* stores preceding the SYNC instruction and both loads and stores that are
	47	* subsequent to the SYNC instruction. Non-zero values of stype may be defined
	48	* by the architecture or specific implementations to perform synchronization
	49	* behaviors that are less complete than that of stype zero. If an
	50	* implementation does not use one of these non-zero values to define a
	51	* different synchronization behavior, then that non-zero value of stype must
	52	* act the same as stype zero completion barrier. This allows software written
	53	* for an implementation with a lighter-weight barrier to work on another
	54	* implementation which only implements the stype zero completion barrier.
	55	*
	56	* - A completion barrier is required, potentially in conjunction with SSNOP (in
	57	* Release 1 of the Architecture) or EHB (in Release 2 of the Architecture),
	58	* to guarantee that memory reference results are visible across operating
	59	* mode changes. For example, a completion barrier is required on some
	60	* implementations on entry to and exit from Debug Mode to guarantee that
	61	* memory effects are handled correctly.
	62	*/
	63
	64	/*
	65	* stype 0 - A completion barrier that affects preceding loads and stores and
	66	* subsequent loads and stores.
	67	* Older instructions which must reach the load/store ordering point before the
	68	* SYNC instruction completes: Loads, Stores
	69	* Younger instructions which must reach the load/store ordering point only
	70	* after the SYNC instruction completes: Loads, Stores
	71	* Older instructions which must be globally performed when the SYNC instruction
	72	* completes: Loads, Stores
	73	*/
	74	#define STYPE_SYNC 0x0
	75
	76	/*
77	* Ordering barriers:
78	* - Every synchronizable specified memory instruction (loads or stores or both)
79	* that occurs in the instruction stream before the SYNC instruction must
80	* reach a stage in the load/store datapath after which no instruction
81	* re-ordering is possible before any synchronizable specified memory
82	* instruction which occurs after the SYNC instruction in the instruction
83	* stream reaches the same stage in the load/store datapath.
84	*
85	* - If any memory instruction before the SYNC instruction in program order,
86	* generates a memory request to the external memory and any memory
87	* instruction after the SYNC instruction in program order also generates a
88	* memory request to external memory, the memory request belonging to the
89	* older instruction must be globally performed before the time the memory
90	* request belonging to the younger instruction is globally performed.
91	*
92	* - The barrier does not guarantee the order in which instruction fetches are
93	* performed.
94	*/
95
96	/*
97	* stype 0x10 - An ordering barrier that affects preceding loads and stores and
98	* subsequent loads and stores.
99	* Older instructions which must reach the load/store ordering point before the
100	* SYNC instruction completes: Loads, Stores
101	* Younger instructions which must reach the load/store ordering point only
102	* after the SYNC instruction completes: Loads, Stores
103	* Older instructions which must be globally performed when the SYNC instruction
104	* completes: N/A
105	*/
106	#define STYPE_SYNC_MB 0x10
107
108
0004a9df RB	109	#ifdef CONFIG_CPU_HAS_SYNC
	110	#define __sync() \
	111	__asm__ __volatile__( \
	112	".set push\n\t" \
	113	".set noreorder\n\t" \
	114	".set mips2\n\t" \
	115	"sync\n\t" \
	116	".set pop" \
	117	: /* no output */ \
	118	: /* no input */ \
	119	: "memory")
	120	#else
	121	#define __sync() do { } while(0)
	122	#endif
	123
	124	#define __fast_iob() \
	125	__asm__ __volatile__( \
	126	".set push\n\t" \
	127	".set noreorder\n\t" \
	128	"lw $0,%0\n\t" \
	129	"nop\n\t" \
	130	".set pop" \
	131	: /* no output */ \
	132	: "m" ((int )CKSEG1) \
	133	: "memory")
6b07d38a DD	134	#ifdef CONFIG_CPU_CAVIUM_OCTEON
6b07d38a DD	135	# define OCTEON_SYNCW_STR ".set push\n.set arch=octeon\nsyncw\nsyncw\n.set pop\n"
70342287	136	# define __syncw() __asm__ __volatile__(OCTEON_SYNCW_STR : : : "memory")
6b07d38a DD	137
	138	# define fast_wmb() __syncw()
	139	# define fast_rmb() barrier()
	140	# define fast_mb() __sync()
	141	# define fast_iob() do { } while (0)
	142	#else /* ! CONFIG_CPU_CAVIUM_OCTEON */
	143	# define fast_wmb() __sync()
	144	# define fast_rmb() __sync()
	145	# define fast_mb() __sync()
	146	# ifdef CONFIG_SGI_IP28
	147	# define fast_iob() \
7a2852e4 TB	148	__asm__ __volatile__( \
	149	".set push\n\t" \
	150	".set noreorder\n\t" \
	151	"lw $0,%0\n\t" \
	152	"sync\n\t" \
	153	"lw $0,%0\n\t" \
	154	".set pop" \
	155	: /* no output */ \
	156	: "m" ((int )CKSEG1ADDR(0x1fa00004)) \
	157	: "memory")
6b07d38a DD	158	# else
6b07d38a DD	159	# define fast_iob() \
0004a9df RB	160	do { \
	161	__sync(); \
	162	__fast_iob(); \
	163	} while (0)
6b07d38a DD	164	# endif
6b07d38a DD	165	#endif /* CONFIG_CPU_CAVIUM_OCTEON */
0004a9df RB	166
	167	#ifdef CONFIG_CPU_HAS_WB
	168
	169	#include <asm/wbflush.h>
	170
0004a9df RB	171	#define mb() wbflush()
	172	#define iob() wbflush()
	173
	174	#else /* !CONFIG_CPU_HAS_WB */
	175
0004a9df RB	176	#define mb() fast_mb()
	177	#define iob() fast_iob()
	178
	179	#endif /* !CONFIG_CPU_HAS_WB */
	180
1077fa36 AD	181	#define wmb() fast_wmb()
1077fa36 AD	182	#define rmb() fast_rmb()
1077fa36	183
a60514ba	184	#if defined(CONFIG_WEAK_ORDERING)
6b07d38a	185	# ifdef CONFIG_CPU_CAVIUM_OCTEON
a60514ba MT	186	# define __smp_mb() __sync()
	187	# define __smp_rmb() barrier()
	188	# define __smp_wmb() __syncw()
6b07d38a	189	# else
a60514ba MT	190	# define __smp_mb() __asm__ __volatile__("sync" : : :"memory")
	191	# define __smp_rmb() __asm__ __volatile__("sync" : : :"memory")
	192	# define __smp_wmb() __asm__ __volatile__("sync" : : :"memory")
6b07d38a	193	# endif
0004a9df	194	#else
a60514ba MT	195	#define __smp_mb() barrier()
	196	#define __smp_rmb() barrier()
	197	#define __smp_wmb() barrier()
0004a9df	198	#endif
f252ffd5	199
17099b11	200	#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP)
70342287	201	#define __WEAK_LLSC_MB " sync \n"
17099b11 RB	202	#else
	203	#define __WEAK_LLSC_MB " \n"
	204	#endif
0004a9df	205
17099b11	206	#define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
17099b11	207
6b07d38a DD	208	#ifdef CONFIG_CPU_CAVIUM_OCTEON
6b07d38a DD	209	#define smp_mb__before_llsc() smp_wmb()
a60514ba	210	#define __smp_mb__before_llsc() __smp_wmb()
500c2e1f DD	211	/* Cause previous writes to become visible on all CPUs as soon as possible */
	212	#define nudge_writes() __asm__ __volatile__(".set push\n\t" \
	213	".set arch=octeon\n\t" \
	214	"syncw\n\t" \
	215	".set pop" : : : "memory")
6b07d38a	216	#else
f252ffd5	217	#define smp_mb__before_llsc() smp_llsc_mb()
a60514ba	218	#define __smp_mb__before_llsc() smp_llsc_mb()
500c2e1f	219	#define nudge_writes() mb()
6b07d38a	220	#endif
f252ffd5	221
a60514ba MT	222	#define __smp_mb__before_atomic() __smp_mb__before_llsc()
a60514ba MT	223	#define __smp_mb__after_atomic() smp_llsc_mb()
91bbefe6	224
fa083e28 MT	225	#include <asm-generic/barrier.h>
fa083e28 MT	226
0004a9df	227	#endif /* __ASM_BARRIER_H */