[mirror_ubuntu-artful-kernel.git] / arch / mips / include / asm / cpu-features.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2003, 2004 Ralf Baechle
 * Copyright (C) 2004  Maciej W. Rozycki
 */
#ifndef __ASM_CPU_FEATURES_H
#define __ASM_CPU_FEATURES_H

#include <asm/cpu.h>
#include <asm/cpu-info.h>
#include <cpu-feature-overrides.h>

#ifndef current_cpu_type
#define current_cpu_type()	current_cpu_data.cputype
#endif

/*
 * SMP assumption: Options of CPU 0 are a superset of all processors.
 * This is true for all known MIPS systems.
 */
#ifndef cpu_has_tlb
#define cpu_has_tlb		(cpu_data[0].options & MIPS_CPU_TLB)
#endif

/*
 * For the moment we don't consider R6000 and R8000 so we can assume that
 * anything that doesn't support R4000-style exceptions and interrupts is
 * R3000-like.  Users should still treat these two macro definitions as
 * opaque.
 */
#ifndef cpu_has_3kex
#define cpu_has_3kex		(!cpu_has_4kex)
#endif
#ifndef cpu_has_4kex
#define cpu_has_4kex		(cpu_data[0].options & MIPS_CPU_4KEX)
#endif
#ifndef cpu_has_3k_cache
#define cpu_has_3k_cache	(cpu_data[0].options & MIPS_CPU_3K_CACHE)
#endif
#define cpu_has_6k_cache	0
#define cpu_has_8k_cache	0
#ifndef cpu_has_4k_cache
#define cpu_has_4k_cache	(cpu_data[0].options & MIPS_CPU_4K_CACHE)
#endif
#ifndef cpu_has_tx39_cache
#define cpu_has_tx39_cache	(cpu_data[0].options & MIPS_CPU_TX39_CACHE)
#endif
#ifndef cpu_has_octeon_cache
#define cpu_has_octeon_cache	0
#endif
#ifndef cpu_has_fpu
#define cpu_has_fpu		(current_cpu_data.options & MIPS_CPU_FPU)
#define raw_cpu_has_fpu		(raw_current_cpu_data.options & MIPS_CPU_FPU)
#else
#define raw_cpu_has_fpu		cpu_has_fpu
#endif
#ifndef cpu_has_32fpr
#define cpu_has_32fpr		(cpu_data[0].options & MIPS_CPU_32FPR)
#endif
#ifndef cpu_has_counter
#define cpu_has_counter		(cpu_data[0].options & MIPS_CPU_COUNTER)
#endif
#ifndef cpu_has_watch
#define cpu_has_watch		(cpu_data[0].options & MIPS_CPU_WATCH)
#endif
#ifndef cpu_has_divec
#define cpu_has_divec		(cpu_data[0].options & MIPS_CPU_DIVEC)
#endif
#ifndef cpu_has_vce
#define cpu_has_vce		(cpu_data[0].options & MIPS_CPU_VCE)
#endif
#ifndef cpu_has_cache_cdex_p
#define cpu_has_cache_cdex_p	(cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
#endif
#ifndef cpu_has_cache_cdex_s
#define cpu_has_cache_cdex_s	(cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
#endif
#ifndef cpu_has_prefetch
#define cpu_has_prefetch	(cpu_data[0].options & MIPS_CPU_PREFETCH)
#endif
#ifndef cpu_has_mcheck
#define cpu_has_mcheck		(cpu_data[0].options & MIPS_CPU_MCHECK)
#endif
#ifndef cpu_has_ejtag
#define cpu_has_ejtag		(cpu_data[0].options & MIPS_CPU_EJTAG)
#endif
#ifndef cpu_has_llsc
#define cpu_has_llsc		(cpu_data[0].options & MIPS_CPU_LLSC)
#endif
#ifndef kernel_uses_llsc
#define kernel_uses_llsc	cpu_has_llsc
#endif
#ifndef cpu_has_mips16
#define cpu_has_mips16		(cpu_data[0].ases & MIPS_ASE_MIPS16)
#endif
#ifndef cpu_has_mdmx
#define cpu_has_mdmx	       (cpu_data[0].ases & MIPS_ASE_MDMX)
#endif
#ifndef cpu_has_mips3d
#define cpu_has_mips3d	       (cpu_data[0].ases & MIPS_ASE_MIPS3D)
#endif
#ifndef cpu_has_smartmips
#define cpu_has_smartmips      (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
#endif
#ifndef cpu_has_rixi
#define cpu_has_rixi		(cpu_data[0].options & MIPS_CPU_RIXI)
#endif
#ifndef cpu_has_mmips
# ifdef CONFIG_SYS_SUPPORTS_MICROMIPS
#  define cpu_has_mmips		(cpu_data[0].options & MIPS_CPU_MICROMIPS)
# else
#  define cpu_has_mmips		0
# endif
#endif
#ifndef cpu_has_vtag_icache
#define cpu_has_vtag_icache	(cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
#endif
#ifndef cpu_has_dc_aliases
#define cpu_has_dc_aliases	(cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
#endif
#ifndef cpu_has_ic_fills_f_dc
#define cpu_has_ic_fills_f_dc	(cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
#endif
#ifndef cpu_has_pindexed_dcache
#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
#endif
#ifndef cpu_has_local_ebase
#define cpu_has_local_ebase	1
#endif

/*
 * I-Cache snoops remote store.	 This only matters on SMP.  Some multiprocessors
 * such as the R10000 have I-Caches that snoop local stores; the embedded ones
 * don't.  For maintaining I-cache coherency this means we need to flush the
 * D-cache all the way back to whever the I-cache does refills from, so the
 * I-cache has a chance to see the new data at all.  Then we have to flush the
 * I-cache also.
 * Note we may have been rescheduled and may no longer be running on the CPU
 * that did the store so we can't optimize this into only doing the flush on
 * the local CPU.
 */
#ifndef cpu_icache_snoops_remote_store
#ifdef CONFIG_SMP
#define cpu_icache_snoops_remote_store	(cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
#else
#define cpu_icache_snoops_remote_store	1
#endif
#endif

#ifndef cpu_has_mips_2
# define cpu_has_mips_2		(cpu_data[0].isa_level & MIPS_CPU_ISA_II)
#endif
#ifndef cpu_has_mips_3
# define cpu_has_mips_3		(cpu_data[0].isa_level & MIPS_CPU_ISA_III)
#endif
#ifndef cpu_has_mips_4
# define cpu_has_mips_4		(cpu_data[0].isa_level & MIPS_CPU_ISA_IV)
#endif
#ifndef cpu_has_mips_5
# define cpu_has_mips_5		(cpu_data[0].isa_level & MIPS_CPU_ISA_V)
#endif
# ifndef cpu_has_mips32r1
# define cpu_has_mips32r1	(cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
# endif
# ifndef cpu_has_mips32r2
# define cpu_has_mips32r2	(cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
# endif
# ifndef cpu_has_mips64r1
# define cpu_has_mips64r1	(cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
# endif
# ifndef cpu_has_mips64r2
# define cpu_has_mips64r2	(cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
# endif

/*
 * Shortcuts ...
 */
#define cpu_has_mips32	(cpu_has_mips32r1 | cpu_has_mips32r2)
#define cpu_has_mips64	(cpu_has_mips64r1 | cpu_has_mips64r2)
#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
#define cpu_has_mips_r	(cpu_has_mips32r1 | cpu_has_mips32r2 | \
			 cpu_has_mips64r1 | cpu_has_mips64r2)

#ifndef cpu_has_mips_r2_exec_hazard
#define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2
#endif

/*
 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
 * pre-MIPS32/MIPS53 processors have CLO, CLZ.	The IDT RC64574 is 64-bit and
 * has CLO and CLZ but not DCLO nor DCLZ.  For 64-bit kernels
 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
 */
# ifndef cpu_has_clo_clz
# define cpu_has_clo_clz	cpu_has_mips_r
# endif

#ifndef cpu_has_dsp
#define cpu_has_dsp		(cpu_data[0].ases & MIPS_ASE_DSP)
#endif

#ifndef cpu_has_dsp2
#define cpu_has_dsp2		(cpu_data[0].ases & MIPS_ASE_DSP2P)
#endif

#ifndef cpu_has_mipsmt
#define cpu_has_mipsmt		(cpu_data[0].ases & MIPS_ASE_MIPSMT)
#endif

#ifndef cpu_has_userlocal
#define cpu_has_userlocal	(cpu_data[0].options & MIPS_CPU_ULRI)
#endif

#ifdef CONFIG_32BIT
# ifndef cpu_has_nofpuex
# define cpu_has_nofpuex	(cpu_data[0].options & MIPS_CPU_NOFPUEX)
# endif
# ifndef cpu_has_64bits
# define cpu_has_64bits		(cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
# endif
# ifndef cpu_has_64bit_zero_reg
# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
# endif
# ifndef cpu_has_64bit_gp_regs
# define cpu_has_64bit_gp_regs		0
# endif
# ifndef cpu_has_64bit_addresses
# define cpu_has_64bit_addresses	0
# endif
# ifndef cpu_vmbits
# define cpu_vmbits 31
# endif
#endif

#ifdef CONFIG_64BIT
# ifndef cpu_has_nofpuex
# define cpu_has_nofpuex		0
# endif
# ifndef cpu_has_64bits
# define cpu_has_64bits			1
# endif
# ifndef cpu_has_64bit_zero_reg
# define cpu_has_64bit_zero_reg		1
# endif
# ifndef cpu_has_64bit_gp_regs
# define cpu_has_64bit_gp_regs		1
# endif
# ifndef cpu_has_64bit_addresses
# define cpu_has_64bit_addresses	1
# endif
# ifndef cpu_vmbits
# define cpu_vmbits cpu_data[0].vmbits
# define __NEED_VMBITS_PROBE
# endif
#endif

#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
# define cpu_has_vint		(cpu_data[0].options & MIPS_CPU_VINT)
#elif !defined(cpu_has_vint)
# define cpu_has_vint			0
#endif

#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
# define cpu_has_veic		(cpu_data[0].options & MIPS_CPU_VEIC)
#elif !defined(cpu_has_veic)
# define cpu_has_veic			0
#endif

#ifndef cpu_has_inclusive_pcaches
#define cpu_has_inclusive_pcaches	(cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
#endif

#ifndef cpu_dcache_line_size
#define cpu_dcache_line_size()	cpu_data[0].dcache.linesz
#endif
#ifndef cpu_icache_line_size
#define cpu_icache_line_size()	cpu_data[0].icache.linesz
#endif
#ifndef cpu_scache_line_size
#define cpu_scache_line_size()	cpu_data[0].scache.linesz
#endif

#ifndef cpu_hwrena_impl_bits
#define cpu_hwrena_impl_bits		0
#endif

#ifndef cpu_has_perf_cntr_intr_bit
#define cpu_has_perf_cntr_intr_bit	(cpu_data[0].options & MIPS_CPU_PCI)
#endif

#ifndef cpu_has_vz
#define cpu_has_vz		(cpu_data[0].ases & MIPS_ASE_VZ)
#endif

#endif /* __ASM_CPU_FEATURES_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2003, 2004 Ralf Baechle
4194318c	7	* Copyright (C) 2004 Maciej W. Rozycki
1da177e4 LT	8	*/
	9	#ifndef __ASM_CPU_FEATURES_H
	10	#define __ASM_CPU_FEATURES_H
	11
1da177e4 LT	12	#include <asm/cpu.h>
	13	#include <asm/cpu-info.h>
	14	#include <cpu-feature-overrides.h>
	15
10cc3529	16	#ifndef current_cpu_type
70342287	17	#define current_cpu_type() current_cpu_data.cputype
10cc3529 RB	18	#endif
10cc3529 RB	19
1da177e4 LT	20	/*
	21	* SMP assumption: Options of CPU 0 are a superset of all processors.
	22	* This is true for all known MIPS systems.
	23	*/
	24	#ifndef cpu_has_tlb
	25	#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
	26	#endif
1990e542 RB	27
	28	/*
	29	* For the moment we don't consider R6000 and R8000 so we can assume that
	30	* anything that doesn't support R4000-style exceptions and interrupts is
	31	* R3000-like. Users should still treat these two macro definitions as
	32	* opaque.
	33	*/
	34	#ifndef cpu_has_3kex
	35	#define cpu_has_3kex (!cpu_has_4kex)
	36	#endif
1da177e4 LT	37	#ifndef cpu_has_4kex
	38	#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
	39	#endif
02cf2119 RB	40	#ifndef cpu_has_3k_cache
	41	#define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE)
	42	#endif
	43	#define cpu_has_6k_cache 0
	44	#define cpu_has_8k_cache 0
	45	#ifndef cpu_has_4k_cache
	46	#define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE)
	47	#endif
	48	#ifndef cpu_has_tx39_cache
	49	#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
	50	#endif
47d979ec DD	51	#ifndef cpu_has_octeon_cache
	52	#define cpu_has_octeon_cache 0
	53	#endif
1da177e4	54	#ifndef cpu_has_fpu
f088fc84	55	#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
53dc8028 AN	56	#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
	57	#else
	58	#define raw_cpu_has_fpu cpu_has_fpu
1da177e4 LT	59	#endif
	60	#ifndef cpu_has_32fpr
	61	#define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
	62	#endif
	63	#ifndef cpu_has_counter
	64	#define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
	65	#endif
	66	#ifndef cpu_has_watch
	67	#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
	68	#endif
1da177e4 LT	69	#ifndef cpu_has_divec
	70	#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
	71	#endif
	72	#ifndef cpu_has_vce
	73	#define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
	74	#endif
	75	#ifndef cpu_has_cache_cdex_p
	76	#define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
	77	#endif
	78	#ifndef cpu_has_cache_cdex_s
	79	#define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
	80	#endif
	81	#ifndef cpu_has_prefetch
	82	#define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
	83	#endif
	84	#ifndef cpu_has_mcheck
	85	#define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
	86	#endif
	87	#ifndef cpu_has_ejtag
	88	#define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
	89	#endif
	90	#ifndef cpu_has_llsc
	91	#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
	92	#endif
b791d119 DD	93	#ifndef kernel_uses_llsc
	94	#define kernel_uses_llsc cpu_has_llsc
	95	#endif
4194318c RB	96	#ifndef cpu_has_mips16
	97	#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
	98	#endif
	99	#ifndef cpu_has_mdmx
70342287	100	#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
4194318c RB	101	#endif
4194318c RB	102	#ifndef cpu_has_mips3d
70342287	103	#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
4194318c RB	104	#endif
	105	#ifndef cpu_has_smartmips
	106	#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
	107	#endif
b2ab4f08 SH	108	#ifndef cpu_has_rixi
	109	#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI)
	110	#endif
f8fa4811	111	#ifndef cpu_has_mmips
3ddc14ad DD	112	# ifdef CONFIG_SYS_SUPPORTS_MICROMIPS
	113	# define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS)
	114	# else
	115	# define cpu_has_mmips 0
	116	# endif
f8fa4811	117	#endif
1da177e4 LT	118	#ifndef cpu_has_vtag_icache
	119	#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
	120	#endif
	121	#ifndef cpu_has_dc_aliases
	122	#define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
	123	#endif
	124	#ifndef cpu_has_ic_fills_f_dc
	125	#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
	126	#endif
de62893b	127	#ifndef cpu_has_pindexed_dcache
70342287	128	#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
de62893b	129	#endif
8759934e HC	130	#ifndef cpu_has_local_ebase
	131	#define cpu_has_local_ebase 1
	132	#endif
1da177e4 LT	133
1da177e4 LT	134	/*
70342287	135	* I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
1da177e4 LT	136	* such as the R10000 have I-Caches that snoop local stores; the embedded ones
	137	* don't. For maintaining I-cache coherency this means we need to flush the
	138	* D-cache all the way back to whever the I-cache does refills from, so the
	139	* I-cache has a chance to see the new data at all. Then we have to flush the
	140	* I-cache also.
	141	* Note we may have been rescheduled and may no longer be running on the CPU
	142	* that did the store so we can't optimize this into only doing the flush on
	143	* the local CPU.
	144	*/
	145	#ifndef cpu_icache_snoops_remote_store
	146	#ifdef CONFIG_SMP
	147	#define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
	148	#else
	149	#define cpu_icache_snoops_remote_store 1
	150	#endif
	151	#endif
	152
a96102be SH	153	#ifndef cpu_has_mips_2
	154	# define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II)
	155	#endif
	156	#ifndef cpu_has_mips_3
	157	# define cpu_has_mips_3 (cpu_data[0].isa_level & MIPS_CPU_ISA_III)
	158	#endif
	159	#ifndef cpu_has_mips_4
	160	# define cpu_has_mips_4 (cpu_data[0].isa_level & MIPS_CPU_ISA_IV)
	161	#endif
	162	#ifndef cpu_has_mips_5
	163	# define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V)
	164	#endif
0401572a RB	165	# ifndef cpu_has_mips32r1
	166	# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
	167	# endif
	168	# ifndef cpu_has_mips32r2
	169	# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
	170	# endif
	171	# ifndef cpu_has_mips64r1
	172	# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
	173	# endif
	174	# ifndef cpu_has_mips64r2
	175	# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
	176	# endif
	177
	178	/*
	179	* Shortcuts ...
	180	*/
	181	#define cpu_has_mips32 (cpu_has_mips32r1 \| cpu_has_mips32r2)
	182	#define cpu_has_mips64 (cpu_has_mips64r1 \| cpu_has_mips64r2)
70342287 RB	183	#define cpu_has_mips_r1 (cpu_has_mips32r1 \| cpu_has_mips64r1)
70342287 RB	184	#define cpu_has_mips_r2 (cpu_has_mips32r2 \| cpu_has_mips64r2)
c46b302b RB	185	#define cpu_has_mips_r (cpu_has_mips32r1 \| cpu_has_mips32r2 \| \
c46b302b RB	186	cpu_has_mips64r1 \| cpu_has_mips64r2)
0401572a	187
41f0e4d0 DD	188	#ifndef cpu_has_mips_r2_exec_hazard
	189	#define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2
	190	#endif
	191
47740eb8 RB	192	/*
47740eb8 RB	193	* MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
70342287	194	* pre-MIPS32/MIPS53 processors have CLO, CLZ. The IDT RC64574 is 64-bit and
417a5eb0	195	* has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels
47740eb8 RB	196	* cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
	197	*/
	198	# ifndef cpu_has_clo_clz
	199	# define cpu_has_clo_clz cpu_has_mips_r
	200	# endif
	201
e50c0a8f RB	202	#ifndef cpu_has_dsp
	203	#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
	204	#endif
	205
ee80f7c7 SH	206	#ifndef cpu_has_dsp2
	207	#define cpu_has_dsp2 (cpu_data[0].ases & MIPS_ASE_DSP2P)
	208	#endif
	209
8f40611d	210	#ifndef cpu_has_mipsmt
2e128ded	211	#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
8f40611d RB	212	#endif
8f40611d RB	213
a3692020 RB	214	#ifndef cpu_has_userlocal
	215	#define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI)
	216	#endif
	217
875d43e7	218	#ifdef CONFIG_32BIT
1da177e4 LT	219	# ifndef cpu_has_nofpuex
	220	# define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
	221	# endif
	222	# ifndef cpu_has_64bits
	223	# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
	224	# endif
	225	# ifndef cpu_has_64bit_zero_reg
70342287	226	# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
1da177e4 LT	227	# endif
	228	# ifndef cpu_has_64bit_gp_regs
	229	# define cpu_has_64bit_gp_regs 0
	230	# endif
	231	# ifndef cpu_has_64bit_addresses
	232	# define cpu_has_64bit_addresses 0
	233	# endif
91dfc423 GR	234	# ifndef cpu_vmbits
	235	# define cpu_vmbits 31
	236	# endif
1da177e4 LT	237	#endif
1da177e4 LT	238
875d43e7	239	#ifdef CONFIG_64BIT
1da177e4 LT	240	# ifndef cpu_has_nofpuex
	241	# define cpu_has_nofpuex 0
	242	# endif
	243	# ifndef cpu_has_64bits
	244	# define cpu_has_64bits 1
	245	# endif
	246	# ifndef cpu_has_64bit_zero_reg
	247	# define cpu_has_64bit_zero_reg 1
	248	# endif
	249	# ifndef cpu_has_64bit_gp_regs
	250	# define cpu_has_64bit_gp_regs 1
	251	# endif
	252	# ifndef cpu_has_64bit_addresses
	253	# define cpu_has_64bit_addresses 1
	254	# endif
91dfc423 GR	255	# ifndef cpu_vmbits
	256	# define cpu_vmbits cpu_data[0].vmbits
	257	# define __NEED_VMBITS_PROBE
	258	# endif
1da177e4 LT	259	#endif
1da177e4 LT	260
f41ae0b2 RB	261	#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
	262	# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT)
	263	#elif !defined(cpu_has_vint)
8f40611d	264	# define cpu_has_vint 0
f41ae0b2 RB	265	#endif
	266
	267	#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
	268	# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC)
	269	#elif !defined(cpu_has_veic)
8f40611d RB	270	# define cpu_has_veic 0
	271	#endif
	272
fc5d2d27 RB	273	#ifndef cpu_has_inclusive_pcaches
fc5d2d27 RB	274	#define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
1da177e4 LT	275	#endif
	276
	277	#ifndef cpu_dcache_line_size
54fd6441	278	#define cpu_dcache_line_size() cpu_data[0].dcache.linesz
1da177e4 LT	279	#endif
1da177e4 LT	280	#ifndef cpu_icache_line_size
54fd6441	281	#define cpu_icache_line_size() cpu_data[0].icache.linesz
1da177e4 LT	282	#endif
1da177e4 LT	283	#ifndef cpu_scache_line_size
54fd6441	284	#define cpu_scache_line_size() cpu_data[0].scache.linesz
1da177e4 LT	285	#endif
1da177e4 LT	286
fbeda19f DD	287	#ifndef cpu_hwrena_impl_bits
	288	#define cpu_hwrena_impl_bits 0
	289	#endif
	290
da4b62cd AC	291	#ifndef cpu_has_perf_cntr_intr_bit
	292	#define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI)
	293	#endif
	294
1e7decdb DD	295	#ifndef cpu_has_vz
	296	#define cpu_has_vz (cpu_data[0].ases & MIPS_ASE_VZ)
	297	#endif
	298
1da177e4	299	#endif /* __ASM_CPU_FEATURES_H */