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1da177e4 LT |
1 | /* |
2 | * Copyright (C) 2002 MontaVista Software Inc. | |
3 | * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2 of the License, or (at your | |
8 | * option) any later version. | |
9 | */ | |
10 | #ifndef _ASM_FPU_H | |
11 | #define _ASM_FPU_H | |
12 | ||
1da177e4 | 13 | #include <linux/sched.h> |
68db0cf1 | 14 | #include <linux/sched/task_stack.h> |
fc69910f | 15 | #include <linux/ptrace.h> |
1da177e4 | 16 | #include <linux/thread_info.h> |
1977f032 | 17 | #include <linux/bitops.h> |
1da177e4 LT |
18 | |
19 | #include <asm/mipsregs.h> | |
20 | #include <asm/cpu.h> | |
21 | #include <asm/cpu-features.h> | |
e0cc3a42 | 22 | #include <asm/fpu_emulator.h> |
0b624956 | 23 | #include <asm/hazards.h> |
0c7e2bc8 | 24 | #include <asm/ptrace.h> |
1da177e4 LT |
25 | #include <asm/processor.h> |
26 | #include <asm/current.h> | |
33c771ba | 27 | #include <asm/msa.h> |
1da177e4 | 28 | |
f088fc84 RB |
29 | #ifdef CONFIG_MIPS_MT_FPAFF |
30 | #include <asm/mips_mt.h> | |
31 | #endif | |
32 | ||
1da177e4 LT |
33 | struct sigcontext; |
34 | struct sigcontext32; | |
35 | ||
9b26616c | 36 | extern void _init_fpu(unsigned int); |
1da177e4 LT |
37 | extern void _save_fp(struct task_struct *); |
38 | extern void _restore_fp(struct task_struct *); | |
39 | ||
597ce172 PB |
40 | /* |
41 | * This enum specifies a mode in which we want the FPU to operate, for cores | |
4227a2d4 PB |
42 | * which implement the Status.FR bit. Note that the bottom bit of the value |
43 | * purposefully matches the desired value of the Status.FR bit. | |
597ce172 PB |
44 | */ |
45 | enum fpu_mode { | |
46 | FPU_32BIT = 0, /* FR = 0 */ | |
4227a2d4 | 47 | FPU_64BIT, /* FR = 1, FRE = 0 */ |
597ce172 | 48 | FPU_AS_IS, |
4227a2d4 PB |
49 | FPU_HYBRID, /* FR = 1, FRE = 1 */ |
50 | ||
51 | #define FPU_FR_MASK 0x1 | |
597ce172 PB |
52 | }; |
53 | ||
84ab45b3 PB |
54 | #define __disable_fpu() \ |
55 | do { \ | |
56 | clear_c0_status(ST0_CU1); \ | |
57 | disable_fpu_hazard(); \ | |
58 | } while (0) | |
59 | ||
597ce172 PB |
60 | static inline int __enable_fpu(enum fpu_mode mode) |
61 | { | |
62 | int fr; | |
63 | ||
64 | switch (mode) { | |
65 | case FPU_AS_IS: | |
66 | /* just enable the FPU in its current mode */ | |
67 | set_c0_status(ST0_CU1); | |
68 | enable_fpu_hazard(); | |
69 | return 0; | |
70 | ||
4227a2d4 PB |
71 | case FPU_HYBRID: |
72 | if (!cpu_has_fre) | |
73 | return SIGFPE; | |
74 | ||
75 | /* set FRE */ | |
d33e6fe3 | 76 | set_c0_config5(MIPS_CONF5_FRE); |
4227a2d4 PB |
77 | goto fr_common; |
78 | ||
597ce172 | 79 | case FPU_64BIT: |
fcc53b5f | 80 | #if !(defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) \ |
6134d949 | 81 | || defined(CONFIG_64BIT)) |
597ce172 PB |
82 | /* we only have a 32-bit FPU */ |
83 | return SIGFPE; | |
84 | #endif | |
85 | /* fall through */ | |
86 | case FPU_32BIT: | |
b0c34f61 RB |
87 | if (cpu_has_fre) { |
88 | /* clear FRE */ | |
d33e6fe3 | 89 | clear_c0_config5(MIPS_CONF5_FRE); |
b0c34f61 | 90 | } |
4227a2d4 | 91 | fr_common: |
597ce172 | 92 | /* set CU1 & change FR appropriately */ |
4227a2d4 | 93 | fr = (int)mode & FPU_FR_MASK; |
597ce172 PB |
94 | change_c0_status(ST0_CU1 | ST0_FR, ST0_CU1 | (fr ? ST0_FR : 0)); |
95 | enable_fpu_hazard(); | |
96 | ||
97 | /* check FR has the desired value */ | |
84ab45b3 PB |
98 | if (!!(read_c0_status() & ST0_FR) == !!fr) |
99 | return 0; | |
100 | ||
101 | /* unsupported FR value */ | |
102 | __disable_fpu(); | |
103 | return SIGFPE; | |
597ce172 PB |
104 | |
105 | default: | |
106 | BUG(); | |
107 | } | |
97b8b16b AK |
108 | |
109 | return SIGFPE; | |
597ce172 | 110 | } |
1da177e4 | 111 | |
1da177e4 LT |
112 | #define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU) |
113 | ||
1d74f6bc RB |
114 | static inline int __is_fpu_owner(void) |
115 | { | |
116 | return test_thread_flag(TIF_USEDFPU); | |
117 | } | |
118 | ||
1da177e4 LT |
119 | static inline int is_fpu_owner(void) |
120 | { | |
1d74f6bc | 121 | return cpu_has_fpu && __is_fpu_owner(); |
1da177e4 LT |
122 | } |
123 | ||
597ce172 | 124 | static inline int __own_fpu(void) |
1da177e4 | 125 | { |
597ce172 PB |
126 | enum fpu_mode mode; |
127 | int ret; | |
128 | ||
4227a2d4 PB |
129 | if (test_thread_flag(TIF_HYBRID_FPREGS)) |
130 | mode = FPU_HYBRID; | |
131 | else | |
132 | mode = !test_thread_flag(TIF_32BIT_FPREGS); | |
133 | ||
597ce172 PB |
134 | ret = __enable_fpu(mode); |
135 | if (ret) | |
136 | return ret; | |
137 | ||
53dc8028 | 138 | KSTK_STATUS(current) |= ST0_CU1; |
4227a2d4 | 139 | if (mode == FPU_64BIT || mode == FPU_HYBRID) |
597ce172 PB |
140 | KSTK_STATUS(current) |= ST0_FR; |
141 | else /* mode == FPU_32BIT */ | |
142 | KSTK_STATUS(current) &= ~ST0_FR; | |
143 | ||
53dc8028 | 144 | set_thread_flag(TIF_USEDFPU); |
597ce172 | 145 | return 0; |
53dc8028 AN |
146 | } |
147 | ||
597ce172 | 148 | static inline int own_fpu_inatomic(int restore) |
53dc8028 | 149 | { |
597ce172 PB |
150 | int ret = 0; |
151 | ||
53dc8028 | 152 | if (cpu_has_fpu && !__is_fpu_owner()) { |
597ce172 PB |
153 | ret = __own_fpu(); |
154 | if (restore && !ret) | |
53dc8028 | 155 | _restore_fp(current); |
1da177e4 | 156 | } |
597ce172 | 157 | return ret; |
faea6234 AN |
158 | } |
159 | ||
597ce172 | 160 | static inline int own_fpu(int restore) |
faea6234 | 161 | { |
597ce172 PB |
162 | int ret; |
163 | ||
faea6234 | 164 | preempt_disable(); |
597ce172 | 165 | ret = own_fpu_inatomic(restore); |
53dc8028 | 166 | preempt_enable(); |
597ce172 | 167 | return ret; |
1da177e4 LT |
168 | } |
169 | ||
1a3d5957 | 170 | static inline void lose_fpu_inatomic(int save, struct task_struct *tsk) |
1da177e4 | 171 | { |
33c771ba PB |
172 | if (is_msa_enabled()) { |
173 | if (save) { | |
1a3d5957 PB |
174 | save_msa(tsk); |
175 | tsk->thread.fpu.fcr31 = | |
842dfc11 | 176 | read_32bit_cp1_register(CP1_STATUS); |
33c771ba PB |
177 | } |
178 | disable_msa(); | |
1a3d5957 | 179 | clear_tsk_thread_flag(tsk, TIF_USEDMSA); |
acaf6a97 | 180 | __disable_fpu(); |
33c771ba | 181 | } else if (is_fpu_owner()) { |
53dc8028 | 182 | if (save) |
1a3d5957 | 183 | _save_fp(tsk); |
1da177e4 | 184 | __disable_fpu(); |
00fe56dc JH |
185 | } else { |
186 | /* FPU should not have been left enabled with no owner */ | |
187 | WARN(read_c0_status() & ST0_CU1, | |
188 | "Orphaned FPU left enabled"); | |
1da177e4 | 189 | } |
1a3d5957 PB |
190 | KSTK_STATUS(tsk) &= ~ST0_CU1; |
191 | clear_tsk_thread_flag(tsk, TIF_USEDFPU); | |
192 | } | |
193 | ||
194 | static inline void lose_fpu(int save) | |
195 | { | |
196 | preempt_disable(); | |
197 | lose_fpu_inatomic(save, current); | |
53dc8028 | 198 | preempt_enable(); |
1da177e4 LT |
199 | } |
200 | ||
597ce172 | 201 | static inline int init_fpu(void) |
1da177e4 | 202 | { |
9b26616c | 203 | unsigned int fcr31 = current->thread.fpu.fcr31; |
597ce172 PB |
204 | int ret = 0; |
205 | ||
1da177e4 | 206 | if (cpu_has_fpu) { |
b0c34f61 RB |
207 | unsigned int config5; |
208 | ||
597ce172 | 209 | ret = __own_fpu(); |
b0c34f61 RB |
210 | if (ret) |
211 | return ret; | |
4227a2d4 | 212 | |
b0c34f61 | 213 | if (!cpu_has_fre) { |
9b26616c | 214 | _init_fpu(fcr31); |
4227a2d4 | 215 | |
b0c34f61 | 216 | return 0; |
4227a2d4 | 217 | } |
b0c34f61 | 218 | |
b0c34f61 RB |
219 | /* |
220 | * Ensure FRE is clear whilst running _init_fpu, since | |
221 | * single precision FP instructions are used. If FRE | |
222 | * was set then we'll just end up initialising all 32 | |
223 | * 64b registers. | |
224 | */ | |
d33e6fe3 | 225 | config5 = clear_c0_config5(MIPS_CONF5_FRE); |
b0c34f61 RB |
226 | enable_fpu_hazard(); |
227 | ||
9b26616c | 228 | _init_fpu(fcr31); |
b0c34f61 RB |
229 | |
230 | /* Restore FRE */ | |
231 | write_c0_config5(config5); | |
232 | enable_fpu_hazard(); | |
e0cc3a42 | 233 | } else |
1da177e4 | 234 | fpu_emulator_init_fpu(); |
597ce172 | 235 | |
597ce172 | 236 | return ret; |
1da177e4 LT |
237 | } |
238 | ||
239 | static inline void save_fp(struct task_struct *tsk) | |
240 | { | |
241 | if (cpu_has_fpu) | |
242 | _save_fp(tsk); | |
243 | } | |
244 | ||
245 | static inline void restore_fp(struct task_struct *tsk) | |
246 | { | |
247 | if (cpu_has_fpu) | |
248 | _restore_fp(tsk); | |
249 | } | |
250 | ||
bbd426f5 | 251 | static inline union fpureg *get_fpu_regs(struct task_struct *tsk) |
1da177e4 | 252 | { |
e04582b7 AN |
253 | if (tsk == current) { |
254 | preempt_disable(); | |
255 | if (is_fpu_owner()) | |
1da177e4 | 256 | _save_fp(current); |
e04582b7 | 257 | preempt_enable(); |
1da177e4 LT |
258 | } |
259 | ||
eae89076 | 260 | return tsk->thread.fpu.fpr; |
1da177e4 LT |
261 | } |
262 | ||
263 | #endif /* _ASM_FPU_H */ |