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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle | |
7 | * Copyright (C) 1995, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle | |
8 | */ | |
9 | #ifndef _ASM_IRQ_H | |
10 | #define _ASM_IRQ_H | |
11 | ||
1da177e4 | 12 | #include <linux/linkage.h> |
631330f5 | 13 | #include <linux/smp.h> |
41c594ab RB |
14 | |
15 | #include <asm/mipsmtregs.h> | |
16 | ||
1da177e4 LT |
17 | #include <irq.h> |
18 | ||
19 | #ifdef CONFIG_I8259 | |
20 | static inline int irq_canonicalize(int irq) | |
21 | { | |
2fa7937b | 22 | return ((irq == I8259A_IRQ_BASE + 2) ? I8259A_IRQ_BASE + 9 : irq); |
1da177e4 LT |
23 | } |
24 | #else | |
25 | #define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */ | |
26 | #endif | |
27 | ||
1146fe30 RB |
28 | #ifdef CONFIG_MIPS_MT_SMTC |
29 | ||
30 | struct irqaction; | |
31 | ||
32 | extern unsigned long irq_hwmask[]; | |
33 | extern int setup_irq_smtc(unsigned int irq, struct irqaction * new, | |
34 | unsigned long hwmask); | |
35 | ||
36 | static inline void smtc_im_ack_irq(unsigned int irq) | |
37 | { | |
38 | if (irq_hwmask[irq] & ST0_IM) | |
39 | set_c0_status(irq_hwmask[irq] & ST0_IM); | |
40 | } | |
41 | ||
42 | #else | |
43 | ||
44 | static inline void smtc_im_ack_irq(unsigned int irq) | |
45 | { | |
46 | } | |
47 | ||
48 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
49 | ||
f571eff0 KK |
50 | #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF |
51 | #include <linux/cpumask.h> | |
52 | ||
d5dedd45 | 53 | extern int plat_set_irq_affinity(unsigned int irq, |
0de26520 | 54 | const struct cpumask *affinity); |
f571eff0 KK |
55 | extern void smtc_forward_irq(unsigned int irq); |
56 | ||
57 | /* | |
58 | * IRQ affinity hook invoked at the beginning of interrupt dispatch | |
59 | * if option is enabled. | |
60 | * | |
61 | * Up through Linux 2.6.22 (at least) cpumask operations are very | |
62 | * inefficient on MIPS. Initial prototypes of SMTC IRQ affinity | |
63 | * used a "fast path" per-IRQ-descriptor cache of affinity information | |
64 | * to reduce latency. As there is a project afoot to optimize the | |
65 | * cpumask implementations, this version is optimistically assuming | |
66 | * that cpumask.h macro overhead is reasonable during interrupt dispatch. | |
67 | */ | |
68 | #define IRQ_AFFINITY_HOOK(irq) \ | |
69 | do { \ | |
e65e49d0 | 70 | if (!cpumask_test_cpu(smp_processor_id(), irq_desc[irq].affinity)) {\ |
f571eff0 KK |
71 | smtc_forward_irq(irq); \ |
72 | irq_exit(); \ | |
73 | return; \ | |
74 | } \ | |
75 | } while (0) | |
76 | ||
77 | #else /* Not doing SMTC affinity */ | |
78 | ||
79 | #define IRQ_AFFINITY_HOOK(irq) do { } while (0) | |
80 | ||
81 | #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ | |
82 | ||
0db34215 | 83 | #ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP |
1146fe30 | 84 | |
41c594ab RB |
85 | /* |
86 | * Clear interrupt mask handling "backstop" if irq_hwmask | |
87 | * entry so indicates. This implies that the ack() or end() | |
88 | * functions will take over re-enabling the low-level mask. | |
89 | * Otherwise it will be done on return from exception. | |
90 | */ | |
f9bba75e | 91 | #define __DO_IRQ_SMTC_HOOK(irq) \ |
41c594ab | 92 | do { \ |
f571eff0 | 93 | IRQ_AFFINITY_HOOK(irq); \ |
41c594ab RB |
94 | if (irq_hwmask[irq] & 0x0000ff00) \ |
95 | write_c0_tccontext(read_c0_tccontext() & \ | |
f571eff0 KK |
96 | ~(irq_hwmask[irq] & 0x0000ff00)); \ |
97 | } while (0) | |
98 | ||
99 | #define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) \ | |
100 | do { \ | |
101 | if (irq_hwmask[irq] & 0x0000ff00) \ | |
102 | write_c0_tccontext(read_c0_tccontext() & \ | |
103 | ~(irq_hwmask[irq] & 0x0000ff00)); \ | |
41c594ab | 104 | } while (0) |
f571eff0 | 105 | |
41c594ab | 106 | #else |
1146fe30 | 107 | |
f571eff0 KK |
108 | #define __DO_IRQ_SMTC_HOOK(irq) \ |
109 | do { \ | |
110 | IRQ_AFFINITY_HOOK(irq); \ | |
111 | } while (0) | |
112 | #define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) do { } while (0) | |
113 | ||
41c594ab RB |
114 | #endif |
115 | ||
1da177e4 LT |
116 | /* |
117 | * do_IRQ handles all normal device IRQ's (the special | |
118 | * SMP cross-CPU interrupts have their own specific | |
119 | * handlers). | |
120 | * | |
121 | * Ideally there should be away to get this into kernel/irq/handle.c to | |
122 | * avoid the overhead of a call for just a tiny function ... | |
123 | */ | |
937a8015 | 124 | #define do_IRQ(irq) \ |
1da177e4 LT |
125 | do { \ |
126 | irq_enter(); \ | |
f9bba75e | 127 | __DO_IRQ_SMTC_HOOK(irq); \ |
1417836e | 128 | generic_handle_irq(irq); \ |
1da177e4 LT |
129 | irq_exit(); \ |
130 | } while (0) | |
131 | ||
f571eff0 KK |
132 | #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF |
133 | /* | |
134 | * To avoid inefficient and in some cases pathological re-checking of | |
135 | * IRQ affinity, we have this variant that skips the affinity check. | |
136 | */ | |
137 | ||
138 | ||
139 | #define do_IRQ_no_affinity(irq) \ | |
140 | do { \ | |
141 | irq_enter(); \ | |
142 | __NO_AFFINITY_IRQ_SMTC_HOOK(irq); \ | |
143 | generic_handle_irq(irq); \ | |
144 | irq_exit(); \ | |
145 | } while (0) | |
146 | ||
147 | #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ | |
148 | ||
1da177e4 | 149 | extern void arch_init_irq(void); |
937a8015 | 150 | extern void spurious_interrupt(void); |
1da177e4 | 151 | |
4a4cf779 RB |
152 | extern int allocate_irqno(void); |
153 | extern void alloc_legacy_irqno(void); | |
154 | extern void free_irqno(unsigned int irq); | |
155 | ||
3b1d4ed5 RB |
156 | /* |
157 | * Before R2 the timer and performance counter interrupts were both fixed to | |
158 | * IE7. Since R2 their number has to be read from the c0_intctl register. | |
159 | */ | |
160 | #define CP0_LEGACY_COMPARE_IRQ 7 | |
161 | ||
162 | extern int cp0_compare_irq; | |
163 | extern int cp0_perfcount_irq; | |
164 | ||
1da177e4 | 165 | #endif /* _ASM_IRQ_H */ |