]>
Commit | Line | Data |
---|---|---|
740765ce SL |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. | |
7 | * Authors: Sanjay Lal <sanjayl@kymasys.com> | |
8 | */ | |
9 | ||
10 | #ifndef __MIPS_KVM_HOST_H__ | |
11 | #define __MIPS_KVM_HOST_H__ | |
12 | ||
13 | #include <linux/mutex.h> | |
14 | #include <linux/hrtimer.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/types.h> | |
17 | #include <linux/kvm.h> | |
18 | #include <linux/kvm_types.h> | |
19 | #include <linux/threads.h> | |
20 | #include <linux/spinlock.h> | |
21 | ||
e6207bbe JH |
22 | #include <asm/mipsregs.h> |
23 | ||
48a3c4e4 JH |
24 | /* MIPS KVM register ids */ |
25 | #define MIPS_CP0_32(_R, _S) \ | |
7bd4acec | 26 | (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S))) |
48a3c4e4 JH |
27 | |
28 | #define MIPS_CP0_64(_R, _S) \ | |
7bd4acec | 29 | (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S))) |
48a3c4e4 JH |
30 | |
31 | #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0) | |
32 | #define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0) | |
33 | #define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0) | |
34 | #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0) | |
35 | #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2) | |
36 | #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0) | |
37 | #define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1) | |
38 | #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0) | |
39 | #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0) | |
40 | #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0) | |
41 | #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0) | |
42 | #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0) | |
43 | #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0) | |
44 | #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0) | |
45 | #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0) | |
46 | #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0) | |
1068eaaf | 47 | #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0) |
48a3c4e4 JH |
48 | #define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1) |
49 | #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0) | |
50 | #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1) | |
51 | #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2) | |
52 | #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3) | |
c771607a JH |
53 | #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4) |
54 | #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5) | |
48a3c4e4 JH |
55 | #define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7) |
56 | #define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0) | |
57 | #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0) | |
58 | ||
740765ce SL |
59 | |
60 | #define KVM_MAX_VCPUS 1 | |
61 | #define KVM_USER_MEM_SLOTS 8 | |
62 | /* memory slots that does not exposed to userspace */ | |
caa1faa7 | 63 | #define KVM_PRIVATE_MEM_SLOTS 0 |
740765ce SL |
64 | |
65 | #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 | |
920552b2 | 66 | #define KVM_HALT_POLL_NS_DEFAULT 500000 |
740765ce | 67 | |
740765ce SL |
68 | |
69 | ||
70 | /* Special address that contains the comm page, used for reducing # of traps */ | |
22027945 | 71 | #define KVM_GUEST_COMMPAGE_ADDR 0x0 |
740765ce SL |
72 | |
73 | #define KVM_GUEST_KERNEL_MODE(vcpu) ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \ | |
74 | ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0)) | |
75 | ||
22027945 JH |
76 | #define KVM_GUEST_KUSEG 0x00000000UL |
77 | #define KVM_GUEST_KSEG0 0x40000000UL | |
78 | #define KVM_GUEST_KSEG23 0x60000000UL | |
7f5a1ddc | 79 | #define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0xe0000000) |
22027945 | 80 | #define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) |
740765ce SL |
81 | |
82 | #define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0) | |
83 | #define KVM_GUEST_CKSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1) | |
84 | #define KVM_GUEST_CKSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23) | |
85 | ||
86 | /* | |
87 | * Map an address to a certain kernel segment | |
88 | */ | |
89 | #define KVM_GUEST_KSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0) | |
90 | #define KVM_GUEST_KSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1) | |
91 | #define KVM_GUEST_KSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23) | |
92 | ||
22027945 JH |
93 | #define KVM_INVALID_PAGE 0xdeadbeef |
94 | #define KVM_INVALID_INST 0xdeadbeef | |
95 | #define KVM_INVALID_ADDR 0xdeadbeef | |
740765ce | 96 | |
740765ce | 97 | extern atomic_t kvm_mips_instance; |
740765ce SL |
98 | |
99 | struct kvm_vm_stat { | |
100 | u32 remote_tlb_flush; | |
101 | }; | |
102 | ||
103 | struct kvm_vcpu_stat { | |
104 | u32 wait_exits; | |
105 | u32 cache_exits; | |
106 | u32 signal_exits; | |
107 | u32 int_exits; | |
108 | u32 cop_unusable_exits; | |
109 | u32 tlbmod_exits; | |
110 | u32 tlbmiss_ld_exits; | |
111 | u32 tlbmiss_st_exits; | |
112 | u32 addrerr_st_exits; | |
113 | u32 addrerr_ld_exits; | |
114 | u32 syscall_exits; | |
115 | u32 resvd_inst_exits; | |
116 | u32 break_inst_exits; | |
0a560427 | 117 | u32 trap_inst_exits; |
c2537ed9 | 118 | u32 msa_fpe_exits; |
1c0cd66a | 119 | u32 fpe_exits; |
c2537ed9 | 120 | u32 msa_disabled_exits; |
740765ce | 121 | u32 flush_dcache_exits; |
f7819512 | 122 | u32 halt_successful_poll; |
62bea5bf | 123 | u32 halt_attempted_poll; |
3491caf2 | 124 | u32 halt_poll_invalid; |
740765ce SL |
125 | u32 halt_wakeup; |
126 | }; | |
127 | ||
740765ce SL |
128 | struct kvm_arch_memory_slot { |
129 | }; | |
130 | ||
131 | struct kvm_arch { | |
132 | /* Guest GVA->HPA page table */ | |
133 | unsigned long *guest_pmap; | |
134 | unsigned long guest_pmap_npages; | |
135 | ||
136 | /* Wired host TLB used for the commpage */ | |
137 | int commpage_tlb; | |
138 | }; | |
139 | ||
22027945 JH |
140 | #define N_MIPS_COPROC_REGS 32 |
141 | #define N_MIPS_COPROC_SEL 8 | |
740765ce SL |
142 | |
143 | struct mips_coproc { | |
144 | unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL]; | |
145 | #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS | |
146 | unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL]; | |
147 | #endif | |
148 | }; | |
149 | ||
150 | /* | |
151 | * Coprocessor 0 register names | |
152 | */ | |
22027945 JH |
153 | #define MIPS_CP0_TLB_INDEX 0 |
154 | #define MIPS_CP0_TLB_RANDOM 1 | |
155 | #define MIPS_CP0_TLB_LOW 2 | |
156 | #define MIPS_CP0_TLB_LO0 2 | |
157 | #define MIPS_CP0_TLB_LO1 3 | |
158 | #define MIPS_CP0_TLB_CONTEXT 4 | |
159 | #define MIPS_CP0_TLB_PG_MASK 5 | |
160 | #define MIPS_CP0_TLB_WIRED 6 | |
161 | #define MIPS_CP0_HWRENA 7 | |
162 | #define MIPS_CP0_BAD_VADDR 8 | |
163 | #define MIPS_CP0_COUNT 9 | |
164 | #define MIPS_CP0_TLB_HI 10 | |
165 | #define MIPS_CP0_COMPARE 11 | |
166 | #define MIPS_CP0_STATUS 12 | |
167 | #define MIPS_CP0_CAUSE 13 | |
168 | #define MIPS_CP0_EXC_PC 14 | |
169 | #define MIPS_CP0_PRID 15 | |
170 | #define MIPS_CP0_CONFIG 16 | |
171 | #define MIPS_CP0_LLADDR 17 | |
172 | #define MIPS_CP0_WATCH_LO 18 | |
173 | #define MIPS_CP0_WATCH_HI 19 | |
174 | #define MIPS_CP0_TLB_XCONTEXT 20 | |
175 | #define MIPS_CP0_ECC 26 | |
176 | #define MIPS_CP0_CACHE_ERR 27 | |
177 | #define MIPS_CP0_TAG_LO 28 | |
178 | #define MIPS_CP0_TAG_HI 29 | |
179 | #define MIPS_CP0_ERROR_PC 30 | |
180 | #define MIPS_CP0_DEBUG 23 | |
181 | #define MIPS_CP0_DEPC 24 | |
182 | #define MIPS_CP0_PERFCNT 25 | |
183 | #define MIPS_CP0_ERRCTL 26 | |
184 | #define MIPS_CP0_DATA_LO 28 | |
185 | #define MIPS_CP0_DATA_HI 29 | |
186 | #define MIPS_CP0_DESAVE 31 | |
187 | ||
188 | #define MIPS_CP0_CONFIG_SEL 0 | |
189 | #define MIPS_CP0_CONFIG1_SEL 1 | |
190 | #define MIPS_CP0_CONFIG2_SEL 2 | |
191 | #define MIPS_CP0_CONFIG3_SEL 3 | |
c771607a JH |
192 | #define MIPS_CP0_CONFIG4_SEL 4 |
193 | #define MIPS_CP0_CONFIG5_SEL 5 | |
740765ce SL |
194 | |
195 | /* Config0 register bits */ | |
22027945 JH |
196 | #define CP0C0_M 31 |
197 | #define CP0C0_K23 28 | |
198 | #define CP0C0_KU 25 | |
199 | #define CP0C0_MDU 20 | |
200 | #define CP0C0_MM 17 | |
201 | #define CP0C0_BM 16 | |
202 | #define CP0C0_BE 15 | |
203 | #define CP0C0_AT 13 | |
204 | #define CP0C0_AR 10 | |
205 | #define CP0C0_MT 7 | |
206 | #define CP0C0_VI 3 | |
207 | #define CP0C0_K0 0 | |
740765ce SL |
208 | |
209 | /* Config1 register bits */ | |
22027945 JH |
210 | #define CP0C1_M 31 |
211 | #define CP0C1_MMU 25 | |
212 | #define CP0C1_IS 22 | |
213 | #define CP0C1_IL 19 | |
214 | #define CP0C1_IA 16 | |
215 | #define CP0C1_DS 13 | |
216 | #define CP0C1_DL 10 | |
217 | #define CP0C1_DA 7 | |
218 | #define CP0C1_C2 6 | |
219 | #define CP0C1_MD 5 | |
220 | #define CP0C1_PC 4 | |
221 | #define CP0C1_WR 3 | |
222 | #define CP0C1_CA 2 | |
223 | #define CP0C1_EP 1 | |
224 | #define CP0C1_FP 0 | |
740765ce SL |
225 | |
226 | /* Config2 Register bits */ | |
22027945 JH |
227 | #define CP0C2_M 31 |
228 | #define CP0C2_TU 28 | |
229 | #define CP0C2_TS 24 | |
230 | #define CP0C2_TL 20 | |
231 | #define CP0C2_TA 16 | |
232 | #define CP0C2_SU 12 | |
233 | #define CP0C2_SS 8 | |
234 | #define CP0C2_SL 4 | |
235 | #define CP0C2_SA 0 | |
740765ce SL |
236 | |
237 | /* Config3 Register bits */ | |
22027945 JH |
238 | #define CP0C3_M 31 |
239 | #define CP0C3_ISA_ON_EXC 16 | |
240 | #define CP0C3_ULRI 13 | |
241 | #define CP0C3_DSPP 10 | |
242 | #define CP0C3_LPA 7 | |
243 | #define CP0C3_VEIC 6 | |
244 | #define CP0C3_VInt 5 | |
245 | #define CP0C3_SP 4 | |
246 | #define CP0C3_MT 2 | |
247 | #define CP0C3_SM 1 | |
248 | #define CP0C3_TL 0 | |
740765ce | 249 | |
740765ce SL |
250 | /* MMU types, the first four entries have the same layout as the |
251 | CP0C0_MT field. */ | |
252 | enum mips_mmu_types { | |
253 | MMU_TYPE_NONE, | |
254 | MMU_TYPE_R4000, | |
255 | MMU_TYPE_RESERVED, | |
256 | MMU_TYPE_FMT, | |
257 | MMU_TYPE_R3000, | |
258 | MMU_TYPE_R6000, | |
259 | MMU_TYPE_R8000 | |
260 | }; | |
261 | ||
740765ce | 262 | /* Resume Flags */ |
22027945 JH |
263 | #define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */ |
264 | #define RESUME_FLAG_HOST (1<<1) /* Resume host? */ | |
740765ce | 265 | |
22027945 JH |
266 | #define RESUME_GUEST 0 |
267 | #define RESUME_GUEST_DR RESUME_FLAG_DR | |
268 | #define RESUME_HOST RESUME_FLAG_HOST | |
740765ce SL |
269 | |
270 | enum emulation_result { | |
271 | EMULATE_DONE, /* no further processing */ | |
272 | EMULATE_DO_MMIO, /* kvm_run filled with MMIO request */ | |
273 | EMULATE_FAIL, /* can't emulate this instruction */ | |
274 | EMULATE_WAIT, /* WAIT instruction */ | |
275 | EMULATE_PRIV_FAIL, | |
276 | }; | |
277 | ||
740765ce | 278 | #define mips3_paddr_to_tlbpfn(x) \ |
22027945 | 279 | (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME) |
740765ce | 280 | #define mips3_tlbpfn_to_paddr(x) \ |
22027945 | 281 | ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT) |
740765ce | 282 | |
22027945 JH |
283 | #define MIPS3_PG_SHIFT 6 |
284 | #define MIPS3_PG_FRAME 0x3fffffc0 | |
740765ce | 285 | |
22027945 | 286 | #define VPN2_MASK 0xffffe000 |
ca64c2be | 287 | #define KVM_ENTRYHI_ASID MIPS_ENTRYHI_ASID |
e6207bbe | 288 | #define TLB_IS_GLOBAL(x) ((x).tlb_lo[0] & (x).tlb_lo[1] & ENTRYLO_G) |
22027945 | 289 | #define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK) |
ca64c2be | 290 | #define TLB_ASID(x) ((x).tlb_hi & KVM_ENTRYHI_ASID) |
19d194c6 | 291 | #define TLB_LO_IDX(x, va) (((va) >> PAGE_SHIFT) & 1) |
e6207bbe | 292 | #define TLB_IS_VALID(x, va) ((x).tlb_lo[TLB_LO_IDX(x, va)] & ENTRYLO_V) |
d116e812 DCZ |
293 | #define TLB_HI_VPN2_HIT(x, y) ((TLB_VPN2(x) & ~(x).tlb_mask) == \ |
294 | ((y) & VPN2_MASK & ~(x).tlb_mask)) | |
295 | #define TLB_HI_ASID_HIT(x, y) (TLB_IS_GLOBAL(x) || \ | |
ca64c2be | 296 | TLB_ASID(x) == ((y) & KVM_ENTRYHI_ASID)) |
740765ce SL |
297 | |
298 | struct kvm_mips_tlb { | |
299 | long tlb_mask; | |
300 | long tlb_hi; | |
9fbfb06a | 301 | long tlb_lo[2]; |
740765ce SL |
302 | }; |
303 | ||
f943176a JH |
304 | #define KVM_MIPS_AUX_FPU 0x1 |
305 | #define KVM_MIPS_AUX_MSA 0x2 | |
98e91b84 | 306 | |
22027945 | 307 | #define KVM_MIPS_GUEST_TLB_SIZE 64 |
740765ce | 308 | struct kvm_vcpu_arch { |
878edf01 | 309 | void *guest_ebase; |
797179bc | 310 | int (*vcpu_run)(struct kvm_run *run, struct kvm_vcpu *vcpu); |
740765ce SL |
311 | unsigned long host_stack; |
312 | unsigned long host_gp; | |
313 | ||
314 | /* Host CP0 registers used when handling exits from guest */ | |
315 | unsigned long host_cp0_badvaddr; | |
740765ce | 316 | unsigned long host_cp0_epc; |
31cf7498 | 317 | u32 host_cp0_cause; |
740765ce SL |
318 | |
319 | /* GPRS */ | |
320 | unsigned long gprs[32]; | |
321 | unsigned long hi; | |
322 | unsigned long lo; | |
323 | unsigned long pc; | |
324 | ||
325 | /* FPU State */ | |
326 | struct mips_fpu_struct fpu; | |
f943176a JH |
327 | /* Which auxiliary state is loaded (KVM_MIPS_AUX_*) */ |
328 | unsigned int aux_inuse; | |
740765ce SL |
329 | |
330 | /* COP0 State */ | |
331 | struct mips_coproc *cop0; | |
332 | ||
333 | /* Host KSEG0 address of the EI/DI offset */ | |
334 | void *kseg0_commpage; | |
335 | ||
336 | u32 io_gpr; /* GPR used as IO source/target */ | |
337 | ||
e30492bb | 338 | struct hrtimer comparecount_timer; |
f8239342 | 339 | /* Count timer control KVM register */ |
bdb7ed86 | 340 | u32 count_ctl; |
e30492bb | 341 | /* Count bias from the raw time */ |
bdb7ed86 | 342 | u32 count_bias; |
e30492bb | 343 | /* Frequency of timer in Hz */ |
bdb7ed86 | 344 | u32 count_hz; |
e30492bb JH |
345 | /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */ |
346 | s64 count_dyn_bias; | |
f8239342 JH |
347 | /* Resume time */ |
348 | ktime_t count_resume; | |
e30492bb JH |
349 | /* Period of timer tick in ns */ |
350 | u64 count_period; | |
740765ce SL |
351 | |
352 | /* Bitmask of exceptions that are pending */ | |
353 | unsigned long pending_exceptions; | |
354 | ||
355 | /* Bitmask of pending exceptions to be cleared */ | |
356 | unsigned long pending_exceptions_clr; | |
357 | ||
31cf7498 | 358 | u32 pending_load_cause; |
740765ce SL |
359 | |
360 | /* Save/Restore the entryhi register when are are preempted/scheduled back in */ | |
361 | unsigned long preempt_entryhi; | |
362 | ||
363 | /* S/W Based TLB for guest */ | |
364 | struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE]; | |
365 | ||
366 | /* Cached guest kernel/user ASIDs */ | |
bdb7ed86 JH |
367 | u32 guest_user_asid[NR_CPUS]; |
368 | u32 guest_kernel_asid[NR_CPUS]; | |
740765ce SL |
369 | struct mm_struct guest_kernel_mm, guest_user_mm; |
370 | ||
740765ce SL |
371 | int last_sched_cpu; |
372 | ||
373 | /* WAIT executed */ | |
374 | int wait; | |
98e91b84 JH |
375 | |
376 | u8 fpu_enabled; | |
539cb89f | 377 | u8 msa_enabled; |
740765ce SL |
378 | }; |
379 | ||
380 | ||
22027945 JH |
381 | #define kvm_read_c0_guest_index(cop0) (cop0->reg[MIPS_CP0_TLB_INDEX][0]) |
382 | #define kvm_write_c0_guest_index(cop0, val) (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val) | |
383 | #define kvm_read_c0_guest_entrylo0(cop0) (cop0->reg[MIPS_CP0_TLB_LO0][0]) | |
384 | #define kvm_read_c0_guest_entrylo1(cop0) (cop0->reg[MIPS_CP0_TLB_LO1][0]) | |
385 | #define kvm_read_c0_guest_context(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0]) | |
386 | #define kvm_write_c0_guest_context(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val)) | |
387 | #define kvm_read_c0_guest_userlocal(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2]) | |
7767b7d2 | 388 | #define kvm_write_c0_guest_userlocal(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2] = (val)) |
22027945 JH |
389 | #define kvm_read_c0_guest_pagemask(cop0) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0]) |
390 | #define kvm_write_c0_guest_pagemask(cop0, val) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val)) | |
391 | #define kvm_read_c0_guest_wired(cop0) (cop0->reg[MIPS_CP0_TLB_WIRED][0]) | |
392 | #define kvm_write_c0_guest_wired(cop0, val) (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val)) | |
26f4f3b5 JH |
393 | #define kvm_read_c0_guest_hwrena(cop0) (cop0->reg[MIPS_CP0_HWRENA][0]) |
394 | #define kvm_write_c0_guest_hwrena(cop0, val) (cop0->reg[MIPS_CP0_HWRENA][0] = (val)) | |
22027945 JH |
395 | #define kvm_read_c0_guest_badvaddr(cop0) (cop0->reg[MIPS_CP0_BAD_VADDR][0]) |
396 | #define kvm_write_c0_guest_badvaddr(cop0, val) (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val)) | |
397 | #define kvm_read_c0_guest_count(cop0) (cop0->reg[MIPS_CP0_COUNT][0]) | |
398 | #define kvm_write_c0_guest_count(cop0, val) (cop0->reg[MIPS_CP0_COUNT][0] = (val)) | |
399 | #define kvm_read_c0_guest_entryhi(cop0) (cop0->reg[MIPS_CP0_TLB_HI][0]) | |
400 | #define kvm_write_c0_guest_entryhi(cop0, val) (cop0->reg[MIPS_CP0_TLB_HI][0] = (val)) | |
401 | #define kvm_read_c0_guest_compare(cop0) (cop0->reg[MIPS_CP0_COMPARE][0]) | |
402 | #define kvm_write_c0_guest_compare(cop0, val) (cop0->reg[MIPS_CP0_COMPARE][0] = (val)) | |
403 | #define kvm_read_c0_guest_status(cop0) (cop0->reg[MIPS_CP0_STATUS][0]) | |
404 | #define kvm_write_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] = (val)) | |
405 | #define kvm_read_c0_guest_intctl(cop0) (cop0->reg[MIPS_CP0_STATUS][1]) | |
406 | #define kvm_write_c0_guest_intctl(cop0, val) (cop0->reg[MIPS_CP0_STATUS][1] = (val)) | |
407 | #define kvm_read_c0_guest_cause(cop0) (cop0->reg[MIPS_CP0_CAUSE][0]) | |
408 | #define kvm_write_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] = (val)) | |
409 | #define kvm_read_c0_guest_epc(cop0) (cop0->reg[MIPS_CP0_EXC_PC][0]) | |
410 | #define kvm_write_c0_guest_epc(cop0, val) (cop0->reg[MIPS_CP0_EXC_PC][0] = (val)) | |
411 | #define kvm_read_c0_guest_prid(cop0) (cop0->reg[MIPS_CP0_PRID][0]) | |
412 | #define kvm_write_c0_guest_prid(cop0, val) (cop0->reg[MIPS_CP0_PRID][0] = (val)) | |
413 | #define kvm_read_c0_guest_ebase(cop0) (cop0->reg[MIPS_CP0_PRID][1]) | |
414 | #define kvm_write_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] = (val)) | |
415 | #define kvm_read_c0_guest_config(cop0) (cop0->reg[MIPS_CP0_CONFIG][0]) | |
416 | #define kvm_read_c0_guest_config1(cop0) (cop0->reg[MIPS_CP0_CONFIG][1]) | |
417 | #define kvm_read_c0_guest_config2(cop0) (cop0->reg[MIPS_CP0_CONFIG][2]) | |
418 | #define kvm_read_c0_guest_config3(cop0) (cop0->reg[MIPS_CP0_CONFIG][3]) | |
c771607a JH |
419 | #define kvm_read_c0_guest_config4(cop0) (cop0->reg[MIPS_CP0_CONFIG][4]) |
420 | #define kvm_read_c0_guest_config5(cop0) (cop0->reg[MIPS_CP0_CONFIG][5]) | |
22027945 JH |
421 | #define kvm_read_c0_guest_config7(cop0) (cop0->reg[MIPS_CP0_CONFIG][7]) |
422 | #define kvm_write_c0_guest_config(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][0] = (val)) | |
423 | #define kvm_write_c0_guest_config1(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][1] = (val)) | |
424 | #define kvm_write_c0_guest_config2(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][2] = (val)) | |
425 | #define kvm_write_c0_guest_config3(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][3] = (val)) | |
c771607a JH |
426 | #define kvm_write_c0_guest_config4(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][4] = (val)) |
427 | #define kvm_write_c0_guest_config5(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][5] = (val)) | |
22027945 JH |
428 | #define kvm_write_c0_guest_config7(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][7] = (val)) |
429 | #define kvm_read_c0_guest_errorepc(cop0) (cop0->reg[MIPS_CP0_ERROR_PC][0]) | |
430 | #define kvm_write_c0_guest_errorepc(cop0, val) (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val)) | |
431 | ||
c73c99b0 JH |
432 | /* |
433 | * Some of the guest registers may be modified asynchronously (e.g. from a | |
434 | * hrtimer callback in hard irq context) and therefore need stronger atomicity | |
435 | * guarantees than other registers. | |
436 | */ | |
437 | ||
438 | static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg, | |
439 | unsigned long val) | |
440 | { | |
441 | unsigned long temp; | |
442 | do { | |
443 | __asm__ __volatile__( | |
444 | " .set mips3 \n" | |
445 | " " __LL "%0, %1 \n" | |
446 | " or %0, %2 \n" | |
447 | " " __SC "%0, %1 \n" | |
448 | " .set mips0 \n" | |
449 | : "=&r" (temp), "+m" (*reg) | |
450 | : "r" (val)); | |
451 | } while (unlikely(!temp)); | |
452 | } | |
453 | ||
454 | static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg, | |
455 | unsigned long val) | |
456 | { | |
457 | unsigned long temp; | |
458 | do { | |
459 | __asm__ __volatile__( | |
460 | " .set mips3 \n" | |
461 | " " __LL "%0, %1 \n" | |
462 | " and %0, %2 \n" | |
463 | " " __SC "%0, %1 \n" | |
464 | " .set mips0 \n" | |
465 | : "=&r" (temp), "+m" (*reg) | |
466 | : "r" (~val)); | |
467 | } while (unlikely(!temp)); | |
468 | } | |
469 | ||
470 | static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg, | |
471 | unsigned long change, | |
472 | unsigned long val) | |
473 | { | |
474 | unsigned long temp; | |
475 | do { | |
476 | __asm__ __volatile__( | |
477 | " .set mips3 \n" | |
478 | " " __LL "%0, %1 \n" | |
479 | " and %0, %2 \n" | |
480 | " or %0, %3 \n" | |
481 | " " __SC "%0, %1 \n" | |
482 | " .set mips0 \n" | |
483 | : "=&r" (temp), "+m" (*reg) | |
484 | : "r" (~change), "r" (val & change)); | |
485 | } while (unlikely(!temp)); | |
486 | } | |
487 | ||
22027945 JH |
488 | #define kvm_set_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] |= (val)) |
489 | #define kvm_clear_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val)) | |
c73c99b0 JH |
490 | |
491 | /* Cause can be modified asynchronously from hardirq hrtimer callback */ | |
492 | #define kvm_set_c0_guest_cause(cop0, val) \ | |
493 | _kvm_atomic_set_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val) | |
494 | #define kvm_clear_c0_guest_cause(cop0, val) \ | |
495 | _kvm_atomic_clear_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val) | |
22027945 | 496 | #define kvm_change_c0_guest_cause(cop0, change, val) \ |
c73c99b0 JH |
497 | _kvm_atomic_change_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], \ |
498 | change, val) | |
499 | ||
22027945 JH |
500 | #define kvm_set_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] |= (val)) |
501 | #define kvm_clear_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] &= ~(val)) | |
502 | #define kvm_change_c0_guest_ebase(cop0, change, val) \ | |
503 | { \ | |
504 | kvm_clear_c0_guest_ebase(cop0, change); \ | |
505 | kvm_set_c0_guest_ebase(cop0, ((val) & (change))); \ | |
740765ce SL |
506 | } |
507 | ||
98e91b84 JH |
508 | /* Helpers */ |
509 | ||
510 | static inline bool kvm_mips_guest_can_have_fpu(struct kvm_vcpu_arch *vcpu) | |
511 | { | |
512 | return (!__builtin_constant_p(cpu_has_fpu) || cpu_has_fpu) && | |
513 | vcpu->fpu_enabled; | |
514 | } | |
515 | ||
516 | static inline bool kvm_mips_guest_has_fpu(struct kvm_vcpu_arch *vcpu) | |
517 | { | |
518 | return kvm_mips_guest_can_have_fpu(vcpu) && | |
519 | kvm_read_c0_guest_config1(vcpu->cop0) & MIPS_CONF1_FP; | |
520 | } | |
740765ce | 521 | |
539cb89f JH |
522 | static inline bool kvm_mips_guest_can_have_msa(struct kvm_vcpu_arch *vcpu) |
523 | { | |
524 | return (!__builtin_constant_p(cpu_has_msa) || cpu_has_msa) && | |
525 | vcpu->msa_enabled; | |
526 | } | |
527 | ||
528 | static inline bool kvm_mips_guest_has_msa(struct kvm_vcpu_arch *vcpu) | |
529 | { | |
530 | return kvm_mips_guest_can_have_msa(vcpu) && | |
531 | kvm_read_c0_guest_config3(vcpu->cop0) & MIPS_CONF3_MSA; | |
532 | } | |
533 | ||
740765ce | 534 | struct kvm_mips_callbacks { |
2dca3725 JH |
535 | int (*handle_cop_unusable)(struct kvm_vcpu *vcpu); |
536 | int (*handle_tlb_mod)(struct kvm_vcpu *vcpu); | |
537 | int (*handle_tlb_ld_miss)(struct kvm_vcpu *vcpu); | |
538 | int (*handle_tlb_st_miss)(struct kvm_vcpu *vcpu); | |
539 | int (*handle_addr_err_st)(struct kvm_vcpu *vcpu); | |
540 | int (*handle_addr_err_ld)(struct kvm_vcpu *vcpu); | |
541 | int (*handle_syscall)(struct kvm_vcpu *vcpu); | |
542 | int (*handle_res_inst)(struct kvm_vcpu *vcpu); | |
543 | int (*handle_break)(struct kvm_vcpu *vcpu); | |
0a560427 | 544 | int (*handle_trap)(struct kvm_vcpu *vcpu); |
c2537ed9 | 545 | int (*handle_msa_fpe)(struct kvm_vcpu *vcpu); |
1c0cd66a | 546 | int (*handle_fpe)(struct kvm_vcpu *vcpu); |
98119ad5 | 547 | int (*handle_msa_disabled)(struct kvm_vcpu *vcpu); |
2dca3725 JH |
548 | int (*vm_init)(struct kvm *kvm); |
549 | int (*vcpu_init)(struct kvm_vcpu *vcpu); | |
550 | int (*vcpu_setup)(struct kvm_vcpu *vcpu); | |
551 | gpa_t (*gva_to_gpa)(gva_t gva); | |
552 | void (*queue_timer_int)(struct kvm_vcpu *vcpu); | |
553 | void (*dequeue_timer_int)(struct kvm_vcpu *vcpu); | |
554 | void (*queue_io_int)(struct kvm_vcpu *vcpu, | |
555 | struct kvm_mips_interrupt *irq); | |
556 | void (*dequeue_io_int)(struct kvm_vcpu *vcpu, | |
557 | struct kvm_mips_interrupt *irq); | |
558 | int (*irq_deliver)(struct kvm_vcpu *vcpu, unsigned int priority, | |
bdb7ed86 | 559 | u32 cause); |
2dca3725 | 560 | int (*irq_clear)(struct kvm_vcpu *vcpu, unsigned int priority, |
bdb7ed86 | 561 | u32 cause); |
f8be02da JH |
562 | int (*get_one_reg)(struct kvm_vcpu *vcpu, |
563 | const struct kvm_one_reg *reg, s64 *v); | |
564 | int (*set_one_reg)(struct kvm_vcpu *vcpu, | |
565 | const struct kvm_one_reg *reg, s64 v); | |
b86ecb37 JH |
566 | int (*vcpu_get_regs)(struct kvm_vcpu *vcpu); |
567 | int (*vcpu_set_regs)(struct kvm_vcpu *vcpu); | |
740765ce SL |
568 | }; |
569 | extern struct kvm_mips_callbacks *kvm_mips_callbacks; | |
570 | int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks); | |
571 | ||
572 | /* Debug: dump vcpu state */ | |
573 | int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu); | |
574 | ||
575 | /* Trampoline ASM routine to start running in "Guest" context */ | |
576 | extern int __kvm_mips_vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu); | |
577 | ||
539cb89f | 578 | /* FPU/MSA context management */ |
98e91b84 JH |
579 | void __kvm_save_fpu(struct kvm_vcpu_arch *vcpu); |
580 | void __kvm_restore_fpu(struct kvm_vcpu_arch *vcpu); | |
581 | void __kvm_restore_fcsr(struct kvm_vcpu_arch *vcpu); | |
539cb89f JH |
582 | void __kvm_save_msa(struct kvm_vcpu_arch *vcpu); |
583 | void __kvm_restore_msa(struct kvm_vcpu_arch *vcpu); | |
584 | void __kvm_restore_msa_upper(struct kvm_vcpu_arch *vcpu); | |
585 | void __kvm_restore_msacsr(struct kvm_vcpu_arch *vcpu); | |
98e91b84 | 586 | void kvm_own_fpu(struct kvm_vcpu *vcpu); |
539cb89f | 587 | void kvm_own_msa(struct kvm_vcpu *vcpu); |
98e91b84 JH |
588 | void kvm_drop_fpu(struct kvm_vcpu *vcpu); |
589 | void kvm_lose_fpu(struct kvm_vcpu *vcpu); | |
590 | ||
740765ce | 591 | /* TLB handling */ |
bdb7ed86 | 592 | u32 kvm_get_kernel_asid(struct kvm_vcpu *vcpu); |
740765ce | 593 | |
bdb7ed86 | 594 | u32 kvm_get_user_asid(struct kvm_vcpu *vcpu); |
740765ce | 595 | |
bdb7ed86 | 596 | u32 kvm_get_commpage_asid (struct kvm_vcpu *vcpu); |
740765ce SL |
597 | |
598 | extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr, | |
599 | struct kvm_vcpu *vcpu); | |
600 | ||
601 | extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr, | |
602 | struct kvm_vcpu *vcpu); | |
603 | ||
604 | extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu, | |
26ee17ff | 605 | struct kvm_mips_tlb *tlb); |
740765ce | 606 | |
31cf7498 | 607 | extern enum emulation_result kvm_mips_handle_tlbmiss(u32 cause, |
bdb7ed86 | 608 | u32 *opc, |
740765ce SL |
609 | struct kvm_run *run, |
610 | struct kvm_vcpu *vcpu); | |
611 | ||
31cf7498 | 612 | extern enum emulation_result kvm_mips_handle_tlbmod(u32 cause, |
bdb7ed86 | 613 | u32 *opc, |
740765ce SL |
614 | struct kvm_run *run, |
615 | struct kvm_vcpu *vcpu); | |
616 | ||
617 | extern void kvm_mips_dump_host_tlbs(void); | |
618 | extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu); | |
403015b3 JH |
619 | extern int kvm_mips_host_tlb_write(struct kvm_vcpu *vcpu, unsigned long entryhi, |
620 | unsigned long entrylo0, | |
621 | unsigned long entrylo1, | |
622 | int flush_dcache_mask); | |
740765ce SL |
623 | extern void kvm_mips_flush_host_tlb(int skip_kseg0); |
624 | extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi); | |
740765ce SL |
625 | |
626 | extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu, | |
627 | unsigned long entryhi); | |
628 | extern int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr); | |
629 | extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu, | |
630 | unsigned long gva); | |
631 | extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu, | |
632 | struct kvm_vcpu *vcpu); | |
740765ce | 633 | extern void kvm_local_flush_tlb_all(void); |
740765ce SL |
634 | extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu); |
635 | extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu); | |
636 | extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu); | |
637 | ||
638 | /* Emulation */ | |
bdb7ed86 JH |
639 | u32 kvm_get_inst(u32 *opc, struct kvm_vcpu *vcpu); |
640 | enum emulation_result update_pc(struct kvm_vcpu *vcpu, u32 cause); | |
740765ce | 641 | |
31cf7498 | 642 | extern enum emulation_result kvm_mips_emulate_inst(u32 cause, |
bdb7ed86 | 643 | u32 *opc, |
740765ce SL |
644 | struct kvm_run *run, |
645 | struct kvm_vcpu *vcpu); | |
646 | ||
31cf7498 | 647 | extern enum emulation_result kvm_mips_emulate_syscall(u32 cause, |
bdb7ed86 | 648 | u32 *opc, |
740765ce SL |
649 | struct kvm_run *run, |
650 | struct kvm_vcpu *vcpu); | |
651 | ||
31cf7498 | 652 | extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(u32 cause, |
bdb7ed86 | 653 | u32 *opc, |
740765ce SL |
654 | struct kvm_run *run, |
655 | struct kvm_vcpu *vcpu); | |
656 | ||
31cf7498 | 657 | extern enum emulation_result kvm_mips_emulate_tlbinv_ld(u32 cause, |
bdb7ed86 | 658 | u32 *opc, |
740765ce SL |
659 | struct kvm_run *run, |
660 | struct kvm_vcpu *vcpu); | |
661 | ||
31cf7498 | 662 | extern enum emulation_result kvm_mips_emulate_tlbmiss_st(u32 cause, |
bdb7ed86 | 663 | u32 *opc, |
740765ce SL |
664 | struct kvm_run *run, |
665 | struct kvm_vcpu *vcpu); | |
666 | ||
31cf7498 | 667 | extern enum emulation_result kvm_mips_emulate_tlbinv_st(u32 cause, |
bdb7ed86 | 668 | u32 *opc, |
740765ce SL |
669 | struct kvm_run *run, |
670 | struct kvm_vcpu *vcpu); | |
671 | ||
31cf7498 | 672 | extern enum emulation_result kvm_mips_emulate_tlbmod(u32 cause, |
bdb7ed86 | 673 | u32 *opc, |
740765ce SL |
674 | struct kvm_run *run, |
675 | struct kvm_vcpu *vcpu); | |
676 | ||
31cf7498 | 677 | extern enum emulation_result kvm_mips_emulate_fpu_exc(u32 cause, |
bdb7ed86 | 678 | u32 *opc, |
740765ce SL |
679 | struct kvm_run *run, |
680 | struct kvm_vcpu *vcpu); | |
681 | ||
31cf7498 | 682 | extern enum emulation_result kvm_mips_handle_ri(u32 cause, |
bdb7ed86 | 683 | u32 *opc, |
740765ce SL |
684 | struct kvm_run *run, |
685 | struct kvm_vcpu *vcpu); | |
686 | ||
31cf7498 | 687 | extern enum emulation_result kvm_mips_emulate_ri_exc(u32 cause, |
bdb7ed86 | 688 | u32 *opc, |
740765ce SL |
689 | struct kvm_run *run, |
690 | struct kvm_vcpu *vcpu); | |
691 | ||
31cf7498 | 692 | extern enum emulation_result kvm_mips_emulate_bp_exc(u32 cause, |
bdb7ed86 | 693 | u32 *opc, |
740765ce SL |
694 | struct kvm_run *run, |
695 | struct kvm_vcpu *vcpu); | |
696 | ||
31cf7498 | 697 | extern enum emulation_result kvm_mips_emulate_trap_exc(u32 cause, |
bdb7ed86 | 698 | u32 *opc, |
0a560427 JH |
699 | struct kvm_run *run, |
700 | struct kvm_vcpu *vcpu); | |
701 | ||
31cf7498 | 702 | extern enum emulation_result kvm_mips_emulate_msafpe_exc(u32 cause, |
bdb7ed86 | 703 | u32 *opc, |
c2537ed9 JH |
704 | struct kvm_run *run, |
705 | struct kvm_vcpu *vcpu); | |
706 | ||
31cf7498 | 707 | extern enum emulation_result kvm_mips_emulate_fpe_exc(u32 cause, |
bdb7ed86 | 708 | u32 *opc, |
1c0cd66a JH |
709 | struct kvm_run *run, |
710 | struct kvm_vcpu *vcpu); | |
711 | ||
31cf7498 | 712 | extern enum emulation_result kvm_mips_emulate_msadis_exc(u32 cause, |
bdb7ed86 | 713 | u32 *opc, |
c2537ed9 JH |
714 | struct kvm_run *run, |
715 | struct kvm_vcpu *vcpu); | |
716 | ||
740765ce SL |
717 | extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu, |
718 | struct kvm_run *run); | |
719 | ||
bdb7ed86 JH |
720 | u32 kvm_mips_read_count(struct kvm_vcpu *vcpu); |
721 | void kvm_mips_write_count(struct kvm_vcpu *vcpu, u32 count); | |
722 | void kvm_mips_write_compare(struct kvm_vcpu *vcpu, u32 compare, bool ack); | |
e30492bb | 723 | void kvm_mips_init_count(struct kvm_vcpu *vcpu); |
f8239342 JH |
724 | int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl); |
725 | int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume); | |
f74a8e22 | 726 | int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz); |
e30492bb JH |
727 | void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu); |
728 | void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu); | |
729 | enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu); | |
740765ce | 730 | |
31cf7498 | 731 | enum emulation_result kvm_mips_check_privilege(u32 cause, |
bdb7ed86 | 732 | u32 *opc, |
740765ce SL |
733 | struct kvm_run *run, |
734 | struct kvm_vcpu *vcpu); | |
735 | ||
bdb7ed86 JH |
736 | enum emulation_result kvm_mips_emulate_cache(u32 inst, |
737 | u32 *opc, | |
738 | u32 cause, | |
740765ce SL |
739 | struct kvm_run *run, |
740 | struct kvm_vcpu *vcpu); | |
bdb7ed86 JH |
741 | enum emulation_result kvm_mips_emulate_CP0(u32 inst, |
742 | u32 *opc, | |
743 | u32 cause, | |
740765ce SL |
744 | struct kvm_run *run, |
745 | struct kvm_vcpu *vcpu); | |
bdb7ed86 JH |
746 | enum emulation_result kvm_mips_emulate_store(u32 inst, |
747 | u32 cause, | |
740765ce SL |
748 | struct kvm_run *run, |
749 | struct kvm_vcpu *vcpu); | |
bdb7ed86 JH |
750 | enum emulation_result kvm_mips_emulate_load(u32 inst, |
751 | u32 cause, | |
740765ce SL |
752 | struct kvm_run *run, |
753 | struct kvm_vcpu *vcpu); | |
754 | ||
c771607a JH |
755 | unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu); |
756 | unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu); | |
757 | unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu); | |
758 | unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu); | |
759 | ||
740765ce | 760 | /* Dynamic binary translation */ |
bdb7ed86 | 761 | extern int kvm_mips_trans_cache_index(u32 inst, u32 *opc, |
740765ce | 762 | struct kvm_vcpu *vcpu); |
bdb7ed86 JH |
763 | extern int kvm_mips_trans_cache_va(u32 inst, u32 *opc, struct kvm_vcpu *vcpu); |
764 | extern int kvm_mips_trans_mfc0(u32 inst, u32 *opc, struct kvm_vcpu *vcpu); | |
765 | extern int kvm_mips_trans_mtc0(u32 inst, u32 *opc, struct kvm_vcpu *vcpu); | |
740765ce SL |
766 | |
767 | /* Misc */ | |
d98403a5 | 768 | extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu); |
740765ce SL |
769 | extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm); |
770 | ||
13a34e06 | 771 | static inline void kvm_arch_hardware_disable(void) {} |
0865e636 RK |
772 | static inline void kvm_arch_hardware_unsetup(void) {} |
773 | static inline void kvm_arch_sync_events(struct kvm *kvm) {} | |
774 | static inline void kvm_arch_free_memslot(struct kvm *kvm, | |
775 | struct kvm_memory_slot *free, struct kvm_memory_slot *dont) {} | |
15f46015 | 776 | static inline void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) {} |
0865e636 RK |
777 | static inline void kvm_arch_flush_shadow_all(struct kvm *kvm) {} |
778 | static inline void kvm_arch_flush_shadow_memslot(struct kvm *kvm, | |
779 | struct kvm_memory_slot *slot) {} | |
780 | static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {} | |
781 | static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {} | |
3217f7c2 CD |
782 | static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) {} |
783 | static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) {} | |
3491caf2 | 784 | static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} |
740765ce SL |
785 | |
786 | #endif /* __MIPS_KVM_HOST_H__ */ |