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d4a67d9d GJ |
1 | /* |
2 | * Atheros AR71XX/AR724X/AR913X SoC register definitions | |
3 | * | |
703327dd | 4 | * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> |
d4a67d9d GJ |
5 | * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org> |
6 | * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> | |
7 | * | |
703327dd | 8 | * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP |
d4a67d9d GJ |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License version 2 as published | |
12 | * by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #ifndef __ASM_MACH_AR71XX_REGS_H | |
16 | #define __ASM_MACH_AR71XX_REGS_H | |
17 | ||
18 | #include <linux/types.h> | |
d4a67d9d GJ |
19 | #include <linux/io.h> |
20 | #include <linux/bitops.h> | |
21 | ||
22 | #define AR71XX_APB_BASE 0x18000000 | |
7e98aa46 GJ |
23 | #define AR71XX_EHCI_BASE 0x1b000000 |
24 | #define AR71XX_EHCI_SIZE 0x1000 | |
25 | #define AR71XX_OHCI_BASE 0x1c000000 | |
26 | #define AR71XX_OHCI_SIZE 0x1000 | |
68a1d316 GJ |
27 | #define AR71XX_SPI_BASE 0x1f000000 |
28 | #define AR71XX_SPI_SIZE 0x01000000 | |
d4a67d9d GJ |
29 | |
30 | #define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) | |
31 | #define AR71XX_DDR_CTRL_SIZE 0x100 | |
32 | #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) | |
33 | #define AR71XX_UART_SIZE 0x100 | |
7e98aa46 GJ |
34 | #define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) |
35 | #define AR71XX_USB_CTRL_SIZE 0x100 | |
70342287 RB |
36 | #define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) |
37 | #define AR71XX_GPIO_SIZE 0x100 | |
d4a67d9d GJ |
38 | #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) |
39 | #define AR71XX_PLL_SIZE 0x100 | |
40 | #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) | |
41 | #define AR71XX_RESET_SIZE 0x100 | |
42 | ||
ad4ce92e GJ |
43 | #define AR71XX_PCI_MEM_BASE 0x10000000 |
44 | #define AR71XX_PCI_MEM_SIZE 0x07000000 | |
45 | ||
46 | #define AR71XX_PCI_WIN0_OFFS 0x10000000 | |
47 | #define AR71XX_PCI_WIN1_OFFS 0x11000000 | |
48 | #define AR71XX_PCI_WIN2_OFFS 0x12000000 | |
49 | #define AR71XX_PCI_WIN3_OFFS 0x13000000 | |
50 | #define AR71XX_PCI_WIN4_OFFS 0x14000000 | |
51 | #define AR71XX_PCI_WIN5_OFFS 0x15000000 | |
52 | #define AR71XX_PCI_WIN6_OFFS 0x16000000 | |
53 | #define AR71XX_PCI_WIN7_OFFS 0x07000000 | |
54 | ||
55 | #define AR71XX_PCI_CFG_BASE \ | |
56 | (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000) | |
57 | #define AR71XX_PCI_CFG_SIZE 0x100 | |
58 | ||
7e98aa46 GJ |
59 | #define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) |
60 | #define AR7240_USB_CTRL_SIZE 0x100 | |
61 | #define AR7240_OHCI_BASE 0x1b000000 | |
62 | #define AR7240_OHCI_SIZE 0x1000 | |
63 | ||
ad4ce92e GJ |
64 | #define AR724X_PCI_MEM_BASE 0x10000000 |
65 | #define AR724X_PCI_MEM_SIZE 0x04000000 | |
66 | ||
67 | #define AR724X_PCI_CFG_BASE 0x14000000 | |
68 | #define AR724X_PCI_CFG_SIZE 0x1000 | |
12401fc2 GJ |
69 | #define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000) |
70 | #define AR724X_PCI_CRP_SIZE 0x1000 | |
ad4ce92e GJ |
71 | #define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000) |
72 | #define AR724X_PCI_CTRL_SIZE 0x100 | |
73 | ||
7e98aa46 GJ |
74 | #define AR724X_EHCI_BASE 0x1b000000 |
75 | #define AR724X_EHCI_SIZE 0x1000 | |
76 | ||
77 | #define AR913X_EHCI_BASE 0x1b000000 | |
78 | #define AR913X_EHCI_SIZE 0x1000 | |
f5b35d0b GJ |
79 | #define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) |
80 | #define AR913X_WMAC_SIZE 0x30000 | |
81 | ||
0bd3acdf GJ |
82 | #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) |
83 | #define AR933X_UART_SIZE 0x14 | |
34cfcd26 GJ |
84 | #define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) |
85 | #define AR933X_WMAC_SIZE 0x20000 | |
c279b775 GJ |
86 | #define AR933X_EHCI_BASE 0x1b000000 |
87 | #define AR933X_EHCI_SIZE 0x1000 | |
88 | ||
574d6e70 GJ |
89 | #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) |
90 | #define AR934X_WMAC_SIZE 0x20000 | |
00ffed58 GJ |
91 | #define AR934X_EHCI_BASE 0x1b000000 |
92 | #define AR934X_EHCI_SIZE 0x200 | |
97541ccf GJ |
93 | #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) |
94 | #define AR934X_SRIF_SIZE 0x1000 | |
574d6e70 | 95 | |
0a5f3b1c GJ |
96 | #define QCA955X_PCI_MEM_BASE0 0x10000000 |
97 | #define QCA955X_PCI_MEM_BASE1 0x12000000 | |
98 | #define QCA955X_PCI_MEM_SIZE 0x02000000 | |
99 | #define QCA955X_PCI_CFG_BASE0 0x14000000 | |
100 | #define QCA955X_PCI_CFG_BASE1 0x16000000 | |
101 | #define QCA955X_PCI_CFG_SIZE 0x1000 | |
102 | #define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) | |
103 | #define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) | |
104 | #define QCA955X_PCI_CRP_SIZE 0x1000 | |
105 | #define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) | |
106 | #define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) | |
107 | #define QCA955X_PCI_CTRL_SIZE 0x100 | |
108 | ||
e9c0d0aa GJ |
109 | #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) |
110 | #define QCA955X_WMAC_SIZE 0x20000 | |
82c46840 GJ |
111 | #define QCA955X_EHCI0_BASE 0x1b000000 |
112 | #define QCA955X_EHCI1_BASE 0x1b400000 | |
113 | #define QCA955X_EHCI_SIZE 0x1000 | |
e9c0d0aa | 114 | |
d4a67d9d GJ |
115 | /* |
116 | * DDR_CTRL block | |
117 | */ | |
118 | #define AR71XX_DDR_REG_PCI_WIN0 0x7c | |
119 | #define AR71XX_DDR_REG_PCI_WIN1 0x80 | |
120 | #define AR71XX_DDR_REG_PCI_WIN2 0x84 | |
121 | #define AR71XX_DDR_REG_PCI_WIN3 0x88 | |
122 | #define AR71XX_DDR_REG_PCI_WIN4 0x8c | |
123 | #define AR71XX_DDR_REG_PCI_WIN5 0x90 | |
124 | #define AR71XX_DDR_REG_PCI_WIN6 0x94 | |
125 | #define AR71XX_DDR_REG_PCI_WIN7 0x98 | |
126 | #define AR71XX_DDR_REG_FLUSH_GE0 0x9c | |
127 | #define AR71XX_DDR_REG_FLUSH_GE1 0xa0 | |
128 | #define AR71XX_DDR_REG_FLUSH_USB 0xa4 | |
129 | #define AR71XX_DDR_REG_FLUSH_PCI 0xa8 | |
130 | ||
131 | #define AR724X_DDR_REG_FLUSH_GE0 0x7c | |
132 | #define AR724X_DDR_REG_FLUSH_GE1 0x80 | |
133 | #define AR724X_DDR_REG_FLUSH_USB 0x84 | |
134 | #define AR724X_DDR_REG_FLUSH_PCIE 0x88 | |
135 | ||
136 | #define AR913X_DDR_REG_FLUSH_GE0 0x7c | |
137 | #define AR913X_DDR_REG_FLUSH_GE1 0x80 | |
138 | #define AR913X_DDR_REG_FLUSH_USB 0x84 | |
139 | #define AR913X_DDR_REG_FLUSH_WMAC 0x88 | |
140 | ||
54eed4c7 GJ |
141 | #define AR933X_DDR_REG_FLUSH_GE0 0x7c |
142 | #define AR933X_DDR_REG_FLUSH_GE1 0x80 | |
143 | #define AR933X_DDR_REG_FLUSH_USB 0x84 | |
144 | #define AR933X_DDR_REG_FLUSH_WMAC 0x88 | |
145 | ||
fce5cc6e GJ |
146 | #define AR934X_DDR_REG_FLUSH_GE0 0x9c |
147 | #define AR934X_DDR_REG_FLUSH_GE1 0xa0 | |
148 | #define AR934X_DDR_REG_FLUSH_USB 0xa4 | |
149 | #define AR934X_DDR_REG_FLUSH_PCIE 0xa8 | |
150 | #define AR934X_DDR_REG_FLUSH_WMAC 0xac | |
151 | ||
d4a67d9d GJ |
152 | /* |
153 | * PLL block | |
154 | */ | |
155 | #define AR71XX_PLL_REG_CPU_CONFIG 0x00 | |
156 | #define AR71XX_PLL_REG_SEC_CONFIG 0x04 | |
157 | #define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 | |
158 | #define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 | |
159 | ||
626a0695 AB |
160 | #define AR71XX_PLL_FB_SHIFT 3 |
161 | #define AR71XX_PLL_FB_MASK 0x1f | |
d4a67d9d GJ |
162 | #define AR71XX_CPU_DIV_SHIFT 16 |
163 | #define AR71XX_CPU_DIV_MASK 0x3 | |
164 | #define AR71XX_DDR_DIV_SHIFT 18 | |
165 | #define AR71XX_DDR_DIV_MASK 0x3 | |
166 | #define AR71XX_AHB_DIV_SHIFT 20 | |
167 | #define AR71XX_AHB_DIV_MASK 0x7 | |
168 | ||
169 | #define AR724X_PLL_REG_CPU_CONFIG 0x00 | |
da54d84e | 170 | #define AR724X_PLL_REG_PCIE_CONFIG 0x10 |
d4a67d9d | 171 | |
626a0695 AB |
172 | #define AR724X_PLL_FB_SHIFT 0 |
173 | #define AR724X_PLL_FB_MASK 0x3ff | |
d4a67d9d GJ |
174 | #define AR724X_PLL_REF_DIV_SHIFT 10 |
175 | #define AR724X_PLL_REF_DIV_MASK 0xf | |
176 | #define AR724X_AHB_DIV_SHIFT 19 | |
177 | #define AR724X_AHB_DIV_MASK 0x1 | |
178 | #define AR724X_DDR_DIV_SHIFT 22 | |
179 | #define AR724X_DDR_DIV_MASK 0x3 | |
180 | ||
181 | #define AR913X_PLL_REG_CPU_CONFIG 0x00 | |
182 | #define AR913X_PLL_REG_ETH_CONFIG 0x04 | |
183 | #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 | |
184 | #define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18 | |
185 | ||
626a0695 AB |
186 | #define AR913X_PLL_FB_SHIFT 0 |
187 | #define AR913X_PLL_FB_MASK 0x3ff | |
d4a67d9d GJ |
188 | #define AR913X_DDR_DIV_SHIFT 22 |
189 | #define AR913X_DDR_DIV_MASK 0x3 | |
190 | #define AR913X_AHB_DIV_SHIFT 19 | |
191 | #define AR913X_AHB_DIV_MASK 0x1 | |
192 | ||
04225e1d GJ |
193 | #define AR933X_PLL_CPU_CONFIG_REG 0x00 |
194 | #define AR933X_PLL_CLOCK_CTRL_REG 0x08 | |
195 | ||
196 | #define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 | |
197 | #define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f | |
198 | #define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16 | |
199 | #define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f | |
200 | #define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 | |
201 | #define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 | |
202 | ||
203 | #define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2) | |
204 | #define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5 | |
205 | #define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3 | |
206 | #define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10 | |
207 | #define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3 | |
208 | #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15 | |
209 | #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7 | |
210 | ||
8889612b GJ |
211 | #define AR934X_PLL_CPU_CONFIG_REG 0x00 |
212 | #define AR934X_PLL_DDR_CONFIG_REG 0x04 | |
213 | #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 | |
214 | ||
215 | #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 | |
216 | #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f | |
217 | #define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6 | |
218 | #define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f | |
219 | #define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 | |
220 | #define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f | |
221 | #define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 | |
222 | #define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 | |
223 | ||
224 | #define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 | |
225 | #define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff | |
226 | #define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10 | |
227 | #define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f | |
228 | #define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 | |
229 | #define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f | |
230 | #define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 | |
231 | #define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 | |
232 | ||
233 | #define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2) | |
234 | #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3) | |
235 | #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4) | |
236 | #define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5 | |
237 | #define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f | |
238 | #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10 | |
239 | #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f | |
240 | #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15 | |
241 | #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f | |
242 | #define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) | |
243 | #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) | |
244 | #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) | |
245 | ||
41583c05 GJ |
246 | #define QCA955X_PLL_CPU_CONFIG_REG 0x00 |
247 | #define QCA955X_PLL_DDR_CONFIG_REG 0x04 | |
248 | #define QCA955X_PLL_CLK_CTRL_REG 0x08 | |
249 | ||
250 | #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 | |
251 | #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f | |
252 | #define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6 | |
253 | #define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f | |
254 | #define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 | |
255 | #define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f | |
256 | #define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 | |
257 | #define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 | |
258 | ||
259 | #define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 | |
260 | #define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff | |
261 | #define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10 | |
262 | #define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f | |
263 | #define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 | |
264 | #define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f | |
265 | #define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 | |
266 | #define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 | |
267 | ||
268 | #define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) | |
269 | #define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) | |
270 | #define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) | |
271 | #define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 | |
272 | #define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f | |
273 | #define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 | |
274 | #define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f | |
275 | #define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 | |
276 | #define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f | |
277 | #define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) | |
278 | #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) | |
279 | #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) | |
280 | ||
7e98aa46 GJ |
281 | /* |
282 | * USB_CONFIG block | |
283 | */ | |
284 | #define AR71XX_USB_CTRL_REG_FLADJ 0x00 | |
285 | #define AR71XX_USB_CTRL_REG_CONFIG 0x04 | |
286 | ||
d4a67d9d GJ |
287 | /* |
288 | * RESET block | |
289 | */ | |
290 | #define AR71XX_RESET_REG_TIMER 0x00 | |
291 | #define AR71XX_RESET_REG_TIMER_RELOAD 0x04 | |
292 | #define AR71XX_RESET_REG_WDOG_CTRL 0x08 | |
293 | #define AR71XX_RESET_REG_WDOG 0x0c | |
294 | #define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 | |
295 | #define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 | |
296 | #define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 | |
297 | #define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c | |
298 | #define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 | |
299 | #define AR71XX_RESET_REG_RESET_MODULE 0x24 | |
300 | #define AR71XX_RESET_REG_PERFC_CTRL 0x2c | |
301 | #define AR71XX_RESET_REG_PERFC0 0x30 | |
302 | #define AR71XX_RESET_REG_PERFC1 0x34 | |
303 | #define AR71XX_RESET_REG_REV_ID 0x90 | |
304 | ||
305 | #define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18 | |
306 | #define AR913X_RESET_REG_RESET_MODULE 0x1c | |
307 | #define AR913X_RESET_REG_PERF_CTRL 0x20 | |
308 | #define AR913X_RESET_REG_PERFC0 0x24 | |
309 | #define AR913X_RESET_REG_PERFC1 0x28 | |
310 | ||
311 | #define AR724X_RESET_REG_RESET_MODULE 0x1c | |
312 | ||
7ee15d8a | 313 | #define AR933X_RESET_REG_RESET_MODULE 0x1c |
04225e1d GJ |
314 | #define AR933X_RESET_REG_BOOTSTRAP 0xac |
315 | ||
42184768 | 316 | #define AR934X_RESET_REG_RESET_MODULE 0x1c |
8889612b | 317 | #define AR934X_RESET_REG_BOOTSTRAP 0xb0 |
fce5cc6e | 318 | #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac |
8889612b | 319 | |
7d4c2af9 | 320 | #define QCA955X_RESET_REG_RESET_MODULE 0x1c |
41583c05 | 321 | #define QCA955X_RESET_REG_BOOTSTRAP 0xb0 |
53330332 | 322 | #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac |
41583c05 | 323 | |
d2b4ac1e GJ |
324 | #define MISC_INT_ETHSW BIT(12) |
325 | #define MISC_INT_TIMER4 BIT(10) | |
326 | #define MISC_INT_TIMER3 BIT(9) | |
327 | #define MISC_INT_TIMER2 BIT(8) | |
d4a67d9d GJ |
328 | #define MISC_INT_DMA BIT(7) |
329 | #define MISC_INT_OHCI BIT(6) | |
330 | #define MISC_INT_PERFC BIT(5) | |
331 | #define MISC_INT_WDOG BIT(4) | |
332 | #define MISC_INT_UART BIT(3) | |
333 | #define MISC_INT_GPIO BIT(2) | |
334 | #define MISC_INT_ERROR BIT(1) | |
335 | #define MISC_INT_TIMER BIT(0) | |
336 | ||
337 | #define AR71XX_RESET_EXTERNAL BIT(28) | |
338 | #define AR71XX_RESET_FULL_CHIP BIT(24) | |
339 | #define AR71XX_RESET_CPU_NMI BIT(21) | |
340 | #define AR71XX_RESET_CPU_COLD BIT(20) | |
341 | #define AR71XX_RESET_DMA BIT(19) | |
342 | #define AR71XX_RESET_SLIC BIT(18) | |
343 | #define AR71XX_RESET_STEREO BIT(17) | |
344 | #define AR71XX_RESET_DDR BIT(16) | |
345 | #define AR71XX_RESET_GE1_MAC BIT(13) | |
346 | #define AR71XX_RESET_GE1_PHY BIT(12) | |
347 | #define AR71XX_RESET_USBSUS_OVERRIDE BIT(10) | |
348 | #define AR71XX_RESET_GE0_MAC BIT(9) | |
349 | #define AR71XX_RESET_GE0_PHY BIT(8) | |
350 | #define AR71XX_RESET_USB_OHCI_DLL BIT(6) | |
351 | #define AR71XX_RESET_USB_HOST BIT(5) | |
352 | #define AR71XX_RESET_USB_PHY BIT(4) | |
353 | #define AR71XX_RESET_PCI_BUS BIT(1) | |
354 | #define AR71XX_RESET_PCI_CORE BIT(0) | |
355 | ||
7e98aa46 GJ |
356 | #define AR7240_RESET_USB_HOST BIT(5) |
357 | #define AR7240_RESET_OHCI_DLL BIT(3) | |
358 | ||
d4a67d9d GJ |
359 | #define AR724X_RESET_GE1_MDIO BIT(23) |
360 | #define AR724X_RESET_GE0_MDIO BIT(22) | |
361 | #define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) | |
362 | #define AR724X_RESET_PCIE_PHY BIT(7) | |
363 | #define AR724X_RESET_PCIE BIT(6) | |
7e98aa46 GJ |
364 | #define AR724X_RESET_USB_HOST BIT(5) |
365 | #define AR724X_RESET_USB_PHY BIT(4) | |
366 | #define AR724X_RESET_USBSUS_OVERRIDE BIT(3) | |
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367 | |
368 | #define AR913X_RESET_AMBA2WMAC BIT(22) | |
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369 | #define AR913X_RESET_USBSUS_OVERRIDE BIT(10) |
370 | #define AR913X_RESET_USB_HOST BIT(5) | |
371 | #define AR913X_RESET_USB_PHY BIT(4) | |
d4a67d9d | 372 | |
34cfcd26 | 373 | #define AR933X_RESET_WMAC BIT(11) |
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374 | #define AR933X_RESET_USB_HOST BIT(5) |
375 | #define AR933X_RESET_USB_PHY BIT(4) | |
376 | #define AR933X_RESET_USBSUS_OVERRIDE BIT(3) | |
377 | ||
00ffed58 GJ |
378 | #define AR934X_RESET_USB_PHY_ANALOG BIT(11) |
379 | #define AR934X_RESET_USB_HOST BIT(5) | |
380 | #define AR934X_RESET_USB_PHY BIT(4) | |
381 | #define AR934X_RESET_USBSUS_OVERRIDE BIT(3) | |
382 | ||
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383 | #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) |
384 | ||
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385 | #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) |
386 | #define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22) | |
387 | #define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21) | |
388 | #define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20) | |
389 | #define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19) | |
390 | #define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18) | |
391 | #define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17) | |
392 | #define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16) | |
393 | #define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7) | |
394 | #define AR934X_BOOTSTRAP_PCIE_RC BIT(6) | |
395 | #define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5) | |
396 | #define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4) | |
397 | #define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2) | |
70342287 | 398 | #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) |
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399 | #define AR934X_BOOTSTRAP_DDR1 BIT(0) |
400 | ||
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401 | #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) |
402 | ||
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403 | #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) |
404 | #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) | |
405 | #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) | |
406 | #define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) | |
407 | #define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4) | |
408 | #define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) | |
409 | #define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) | |
410 | #define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) | |
411 | #define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) | |
412 | #define AR934X_PCIE_WMAC_INT_WMAC_ALL \ | |
413 | (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \ | |
414 | AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP) | |
415 | ||
416 | #define AR934X_PCIE_WMAC_INT_PCIE_ALL \ | |
417 | (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \ | |
418 | AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ | |
419 | AR934X_PCIE_WMAC_INT_PCIE_RC3) | |
420 | ||
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421 | #define QCA955X_EXT_INT_WMAC_MISC BIT(0) |
422 | #define QCA955X_EXT_INT_WMAC_TX BIT(1) | |
423 | #define QCA955X_EXT_INT_WMAC_RXLP BIT(2) | |
424 | #define QCA955X_EXT_INT_WMAC_RXHP BIT(3) | |
425 | #define QCA955X_EXT_INT_PCIE_RC1 BIT(4) | |
426 | #define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5) | |
427 | #define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6) | |
428 | #define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7) | |
429 | #define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8) | |
430 | #define QCA955X_EXT_INT_PCIE_RC2 BIT(12) | |
431 | #define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13) | |
432 | #define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14) | |
433 | #define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15) | |
434 | #define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16) | |
435 | #define QCA955X_EXT_INT_USB1 BIT(24) | |
436 | #define QCA955X_EXT_INT_USB2 BIT(28) | |
437 | ||
438 | #define QCA955X_EXT_INT_WMAC_ALL \ | |
439 | (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \ | |
440 | QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP) | |
441 | ||
442 | #define QCA955X_EXT_INT_PCIE_RC1_ALL \ | |
443 | (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \ | |
444 | QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \ | |
445 | QCA955X_EXT_INT_PCIE_RC1_INT3) | |
446 | ||
447 | #define QCA955X_EXT_INT_PCIE_RC2_ALL \ | |
448 | (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \ | |
449 | QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ | |
450 | QCA955X_EXT_INT_PCIE_RC2_INT3) | |
451 | ||
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452 | #define REV_ID_MAJOR_MASK 0xfff0 |
453 | #define REV_ID_MAJOR_AR71XX 0x00a0 | |
454 | #define REV_ID_MAJOR_AR913X 0x00b0 | |
455 | #define REV_ID_MAJOR_AR7240 0x00c0 | |
456 | #define REV_ID_MAJOR_AR7241 0x0100 | |
457 | #define REV_ID_MAJOR_AR7242 0x1100 | |
6d1c8fde GJ |
458 | #define REV_ID_MAJOR_AR9330 0x0110 |
459 | #define REV_ID_MAJOR_AR9331 0x1110 | |
703327dd GJ |
460 | #define REV_ID_MAJOR_AR9341 0x0120 |
461 | #define REV_ID_MAJOR_AR9342 0x1120 | |
462 | #define REV_ID_MAJOR_AR9344 0x2120 | |
90898779 GJ |
463 | #define REV_ID_MAJOR_QCA9556 0x0130 |
464 | #define REV_ID_MAJOR_QCA9558 0x1130 | |
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465 | |
466 | #define AR71XX_REV_ID_MINOR_MASK 0x3 | |
467 | #define AR71XX_REV_ID_MINOR_AR7130 0x0 | |
468 | #define AR71XX_REV_ID_MINOR_AR7141 0x1 | |
469 | #define AR71XX_REV_ID_MINOR_AR7161 0x2 | |
470 | #define AR71XX_REV_ID_REVISION_MASK 0x3 | |
471 | #define AR71XX_REV_ID_REVISION_SHIFT 2 | |
472 | ||
473 | #define AR913X_REV_ID_MINOR_MASK 0x3 | |
474 | #define AR913X_REV_ID_MINOR_AR9130 0x0 | |
475 | #define AR913X_REV_ID_MINOR_AR9132 0x1 | |
476 | #define AR913X_REV_ID_REVISION_MASK 0x3 | |
477 | #define AR913X_REV_ID_REVISION_SHIFT 2 | |
478 | ||
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479 | #define AR933X_REV_ID_REVISION_MASK 0x3 |
480 | ||
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481 | #define AR724X_REV_ID_REVISION_MASK 0x3 |
482 | ||
70342287 | 483 | #define AR934X_REV_ID_REVISION_MASK 0xf |
d8411466 | 484 | |
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485 | #define QCA955X_REV_ID_REVISION_MASK 0xf |
486 | ||
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487 | /* |
488 | * SPI block | |
489 | */ | |
490 | #define AR71XX_SPI_REG_FS 0x00 /* Function Select */ | |
491 | #define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */ | |
492 | #define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */ | |
493 | #define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */ | |
494 | ||
495 | #define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */ | |
496 | ||
497 | #define AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */ | |
498 | #define AR71XX_SPI_CTRL_DIV_MASK 0x3f | |
499 | ||
500 | #define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */ | |
501 | #define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */ | |
502 | #define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) | |
503 | #define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0) | |
504 | #define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1) | |
505 | #define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2) | |
506 | #define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \ | |
507 | AR71XX_SPI_IOC_CS2) | |
508 | ||
6eae43c5 GJ |
509 | /* |
510 | * GPIO block | |
511 | */ | |
512 | #define AR71XX_GPIO_REG_OE 0x00 | |
513 | #define AR71XX_GPIO_REG_IN 0x04 | |
514 | #define AR71XX_GPIO_REG_OUT 0x08 | |
515 | #define AR71XX_GPIO_REG_SET 0x0c | |
516 | #define AR71XX_GPIO_REG_CLEAR 0x10 | |
517 | #define AR71XX_GPIO_REG_INT_MODE 0x14 | |
518 | #define AR71XX_GPIO_REG_INT_TYPE 0x18 | |
519 | #define AR71XX_GPIO_REG_INT_POLARITY 0x1c | |
520 | #define AR71XX_GPIO_REG_INT_PENDING 0x20 | |
521 | #define AR71XX_GPIO_REG_INT_ENABLE 0x24 | |
522 | #define AR71XX_GPIO_REG_FUNC 0x28 | |
523 | ||
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524 | #define AR934X_GPIO_REG_FUNC 0x6c |
525 | ||
6eae43c5 | 526 | #define AR71XX_GPIO_COUNT 16 |
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527 | #define AR7240_GPIO_COUNT 18 |
528 | #define AR7241_GPIO_COUNT 20 | |
6eae43c5 | 529 | #define AR913X_GPIO_COUNT 22 |
fdfbcf47 | 530 | #define AR933X_GPIO_COUNT 30 |
5b5b544e | 531 | #define AR934X_GPIO_COUNT 23 |
f818ca3e | 532 | #define QCA955X_GPIO_COUNT 24 |
6eae43c5 | 533 | |
97541ccf GJ |
534 | /* |
535 | * SRIF block | |
536 | */ | |
537 | #define AR934X_SRIF_CPU_DPLL1_REG 0x1c0 | |
538 | #define AR934X_SRIF_CPU_DPLL2_REG 0x1c4 | |
539 | #define AR934X_SRIF_CPU_DPLL3_REG 0x1c8 | |
540 | ||
541 | #define AR934X_SRIF_DDR_DPLL1_REG 0x240 | |
542 | #define AR934X_SRIF_DDR_DPLL2_REG 0x244 | |
543 | #define AR934X_SRIF_DDR_DPLL3_REG 0x248 | |
544 | ||
545 | #define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27 | |
546 | #define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f | |
547 | #define AR934X_SRIF_DPLL1_NINT_SHIFT 18 | |
548 | #define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff | |
549 | #define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff | |
550 | ||
551 | #define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30) | |
552 | #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 | |
553 | #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 | |
554 | ||
d4a67d9d | 555 | #endif /* __ASM_MACH_AR71XX_REGS_H */ |