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1da177e4
LT		 1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Include file for Alchemy Semiconductor's Au1k CPU.
5 *
01675095
SS		 6 * Copyright 2000-2001, 2006-2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30 /*
31 * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp
32 */
33
34#ifndef _AU1000_H_
35#define _AU1000_H_
36
1da177e4
LT		 37
38#ifndef _LANGUAGE_ASSEMBLY
39
40#include <linux/delay.h>
786d7cdd 41#include <linux/types.h>
9d360ab4 42
ff6814d5
SS		 43#include <linux/io.h>
44#include <linux/irq.h>
1da177e4
LT		 45
46/* cpu pipeline flush */
47void static inline au_sync(void)
48{
49 __asm__ volatile ("sync");
50}
51
52void static inline au_sync_udelay(int us)
53{
54 __asm__ volatile ("sync");
55 udelay(us);
56}
57
58void static inline au_sync_delay(int ms)
59{
60 __asm__ volatile ("sync");
61 mdelay(ms);
62}
63
7de8d232 64void static inline au_writeb(u8 val, unsigned long reg)
1da177e4 65{
ff6814d5 66 *(volatile u8 *)reg = val;
1da177e4
LT		 67}
68
7de8d232 69void static inline au_writew(u16 val, unsigned long reg)
1da177e4 70{
ff6814d5 71 *(volatile u16 *)reg = val;
1da177e4
LT		 72}
73
7de8d232 74void static inline au_writel(u32 val, unsigned long reg)
1da177e4 75{
ff6814d5 76 *(volatile u32 *)reg = val;
1da177e4
LT		 77}
78
7de8d232 79static inline u8 au_readb(unsigned long reg)
1da177e4 80{
ff6814d5 81 return *(volatile u8 *)reg;
1da177e4
LT		 82}
83
7de8d232 84static inline u16 au_readw(unsigned long reg)
1da177e4 85{
ff6814d5 86 return *(volatile u16 *)reg;
1da177e4
LT		 87}
88
7de8d232 89static inline u32 au_readl(unsigned long reg)
1da177e4 90{
ff6814d5 91 return *(volatile u32 *)reg;
1da177e4
LT		 92}
93
074cf656
ML		 94/* Early Au1000 have a write-only SYS_CPUPLL register. */
95static inline int au1xxx_cpu_has_pll_wo(void)
96{
97 switch (read_c0_prid()) {
98 case 0x00030100: /* Au1000 DA */
99 case 0x00030201: /* Au1000 HA */
100 case 0x00030202: /* Au1000 HB */
101 return 1;
102 }
103 return 0;
104}
105
106/* does CPU need CONFIG[OD] set to fix tons of errata? */
107static inline int au1xxx_cpu_needs_config_od(void)
108{
109 /*
110 * c0_config.od (bit 19) was write only (and read as 0) on the
111 * early revisions of Alchemy SOCs. It disables the bus trans-
112 * action overlapping and needs to be set to fix various errata.
113 */
114 switch (read_c0_prid()) {
115 case 0x00030100: /* Au1000 DA */
116 case 0x00030201: /* Au1000 HA */
117 case 0x00030202: /* Au1000 HB */
118 case 0x01030200: /* Au1500 AB */
119 /*
120 * Au1100/Au1200 errata actually keep silence about this bit,
121 * so we set it just in case for those revisions that require
122 * it to be set according to the (now gone) cpu_table.
123 */
124 case 0x02030200: /* Au1100 AB */
125 case 0x02030201: /* Au1100 BA */
126 case 0x02030202: /* Au1100 BC */
127 case 0x04030201: /* Au1200 AC */
128 return 1;
129 }
130 return 0;
131}
1da177e4 132
93e9cd84
ML		 133#define ALCHEMY_CPU_UNKNOWN -1
134#define ALCHEMY_CPU_AU1000 0
135#define ALCHEMY_CPU_AU1500 1
136#define ALCHEMY_CPU_AU1100 2
137#define ALCHEMY_CPU_AU1550 3
138#define ALCHEMY_CPU_AU1200 4
809f36c6 139#define ALCHEMY_CPU_AU1300 5
93e9cd84
ML		 140
141static inline int alchemy_get_cputype(void)
142{
143 switch (read_c0_prid() & 0xffff0000) {
144 case 0x00030000:
145 return ALCHEMY_CPU_AU1000;
146 break;
147 case 0x01030000:
148 return ALCHEMY_CPU_AU1500;
149 break;
150 case 0x02030000:
151 return ALCHEMY_CPU_AU1100;
152 break;
153 case 0x03030000:
154 return ALCHEMY_CPU_AU1550;
155 break;
156 case 0x04030000:
157 case 0x05030000:
158 return ALCHEMY_CPU_AU1200;
159 break;
809f36c6
ML		 160 case 0x800c0000:
161 return ALCHEMY_CPU_AU1300;
162 break;
93e9cd84
ML		 163 }
164
165 return ALCHEMY_CPU_UNKNOWN;
166}
167
80130204
ML		 168/* return number of uarts on a given cputype */
169static inline int alchemy_get_uarts(int type)
170{
171 switch (type) {
172 case ALCHEMY_CPU_AU1000:
809f36c6 173 case ALCHEMY_CPU_AU1300:
80130204
ML		 174 return 4;
175 case ALCHEMY_CPU_AU1500:
176 case ALCHEMY_CPU_AU1200:
177 return 2;
178 case ALCHEMY_CPU_AU1100:
179 case ALCHEMY_CPU_AU1550:
180 return 3;
181 }
182 return 0;
183}
184
185/* enable an UART block if it isn't already */
186static inline void alchemy_uart_enable(u32 uart_phys)
187{
188 void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys);
189
190 /* reset, enable clock, deassert reset */
191 if ((__raw_readl(addr + 0x100) & 3) != 3) {
192 __raw_writel(0, addr + 0x100);
193 wmb();
194 __raw_writel(1, addr + 0x100);
195 wmb();
196 }
197 __raw_writel(3, addr + 0x100);
198 wmb();
199}
200
201static inline void alchemy_uart_disable(u32 uart_phys)
202{
203 void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys);
204 __raw_writel(0, addr + 0x100); /* UART_MOD_CNTRL */
205 wmb();
206}
207
8402a158
ML		 208static inline void alchemy_uart_putchar(u32 uart_phys, u8 c)
209{
210 void __iomem *base = (void __iomem *)KSEG1ADDR(uart_phys);
211 int timeout, i;
212
213 /* check LSR TX_EMPTY bit */
214 timeout = 0xffffff;
215 do {
216 if (__raw_readl(base + 0x1c) & 0x20)
217 break;
218 /* slow down */
219 for (i = 10000; i; i--)
220 asm volatile ("nop");
221 } while (--timeout);
222
223 __raw_writel(c, base + 0x04); /* tx */
224 wmb();
225}
226
40d8bc28
ML		 227/* return number of ethernet MACs on a given cputype */
228static inline int alchemy_get_macs(int type)
229{
230 switch (type) {
231 case ALCHEMY_CPU_AU1000:
232 case ALCHEMY_CPU_AU1500:
233 case ALCHEMY_CPU_AU1550:
234 return 2;
235 case ALCHEMY_CPU_AU1100:
236 return 1;
237 }
238 return 0;
239}
240
1da177e4
LT		 241/* arch/mips/au1000/common/clocks.c */
242extern void set_au1x00_speed(unsigned int new_freq);
243extern unsigned int get_au1x00_speed(void);
244extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
245extern unsigned long get_au1x00_uart_baud_base(void);
2699cdfb 246extern unsigned long au1xxx_calc_clock(void);
1da177e4 247
564365b0 248/* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */
2e93d1ec
ML		 249void alchemy_sleep_au1000(void);
250void alchemy_sleep_au1550(void);
809f36c6 251void alchemy_sleep_au1300(void);
564365b0 252void au_sleep(void);
564365b0 253
ce6bc922
ML		 254/* USB: drivers/usb/host/alchemy-common.c */
255enum alchemy_usb_block {
256 ALCHEMY_USB_OHCI0,
257 ALCHEMY_USB_UDC0,
258 ALCHEMY_USB_EHCI0,
259 ALCHEMY_USB_OTG0,
809f36c6 260 ALCHEMY_USB_OHCI1,
ce6bc922
ML		 261};
262int alchemy_usb_control(int block, int enable);
263
7517de34
ML		 264/* PCI controller platform data */
265struct alchemy_pci_platdata {
266 int (*board_map_irq)(const struct pci_dev *d, u8 slot, u8 pin);
267 int (*board_pci_idsel)(unsigned int devsel, int assert);
268 /* bits to set/clear in PCI_CONFIG register */
269 unsigned long pci_cfg_set;
270 unsigned long pci_cfg_clr;
271};
78814465 272
809f36c6
ML		 273/* Multifunction pins: Each of these pins can either be assigned to the
274 * GPIO controller or a on-chip peripheral.
275 * Call "au1300_pinfunc_to_dev()" or "au1300_pinfunc_to_gpio()" to
276 * assign one of these to either the GPIO controller or the device.
277 */
278enum au1300_multifunc_pins {
279 /* wake-from-str pins 0-3 */
280 AU1300_PIN_WAKE0 = 0, AU1300_PIN_WAKE1, AU1300_PIN_WAKE2,
281 AU1300_PIN_WAKE3,
282 /* external clock sources for PSCs: 4-5 */
283 AU1300_PIN_EXTCLK0, AU1300_PIN_EXTCLK1,
284 /* 8bit MMC interface on SD0: 6-9 */
285 AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6,
286 AU1300_PIN_SD0DAT7,
287 /* aux clk input for freqgen 3: 10 */
288 AU1300_PIN_FG3AUX,
289 /* UART1 pins: 11-18 */
290 AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR,
291 AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR,
292 AU1300_PIN_U1RX, AU1300_PIN_U1TX,
293 /* UART0 pins: 19-24 */
294 AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR,
295 AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR,
296 /* UART2: 25-26 */
297 AU1300_PIN_U2RX, AU1300_PIN_U2TX,
298 /* UART3: 27-28 */
299 AU1300_PIN_U3RX, AU1300_PIN_U3TX,
300 /* LCD controller PWMs, ext pixclock: 29-31 */
301 AU1300_PIN_LCDPWM0, AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN,
302 /* SD1 interface: 32-37 */
303 AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2,
304 AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK,
305 /* SD2 interface: 38-43 */
306 AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2,
307 AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK,
308 /* PSC0/1 clocks: 44-45 */
309 AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK,
310 /* PSCs: 46-49/50-53/54-57/58-61 */
311 AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0,
312 AU1300_PIN_PSC0D1,
313 AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0,
314 AU1300_PIN_PSC1D1,
315 AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_PSC2D0,
316 AU1300_PIN_PSC2D1,
317 AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0,
318 AU1300_PIN_PSC3D1,
319 /* PCMCIA interface: 62-70 */
320 AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16,
321 AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT,
322 AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW,
323 /* camera interface H/V sync inputs: 71-72 */
324 AU1300_PIN_CIMLS, AU1300_PIN_CIMFS,
325 /* PSC2/3 clocks: 73-74 */
326 AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK,
327};
328
329/* GPIC (Au1300) pin management: arch/mips/alchemy/common/gpioint.c */
330extern void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins gpio);
331extern void au1300_pinfunc_to_dev(enum au1300_multifunc_pins gpio);
332extern void au1300_set_irq_priority(unsigned int irq, int p);
333extern void au1300_set_dbdma_gpio(int dchan, unsigned int gpio);
334
335/* Au1300 allows to disconnect certain blocks from internal power supply */
336enum au1300_vss_block {
337 AU1300_VSS_MPE = 0,
338 AU1300_VSS_BSA,
339 AU1300_VSS_GPE,
340 AU1300_VSS_MGP,
341};
342
343extern void au1300_vss_block_control(int block, int enable);
344
78814465 345
809f36c6
ML		 346/* SOC Interrupt numbers */
347/* Au1000-style (IC0/1): 2 controllers with 32 sources each */
78814465
ML		 348#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
349#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
350#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1)
351#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
70342287 352#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
78814465 353
809f36c6
ML		 354/* Au1300-style (GPIC): 1 controller with up to 128 sources */
355#define ALCHEMY_GPIC_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
356#define ALCHEMY_GPIC_INT_NUM 128
357#define ALCHEMY_GPIC_INT_LAST (ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1)
358
78814465
ML		 359enum soc_au1000_ints {
360 AU1000_FIRST_INT = AU1000_INTC0_INT_BASE,
361 AU1000_UART0_INT = AU1000_FIRST_INT,
362 AU1000_UART1_INT,
363 AU1000_UART2_INT,
364 AU1000_UART3_INT,
365 AU1000_SSI0_INT,
366 AU1000_SSI1_INT,
367 AU1000_DMA_INT_BASE,
368
369 AU1000_TOY_INT = AU1000_FIRST_INT + 14,
370 AU1000_TOY_MATCH0_INT,
371 AU1000_TOY_MATCH1_INT,
372 AU1000_TOY_MATCH2_INT,
373 AU1000_RTC_INT,
374 AU1000_RTC_MATCH0_INT,
375 AU1000_RTC_MATCH1_INT,
376 AU1000_RTC_MATCH2_INT,
377 AU1000_IRDA_TX_INT,
378 AU1000_IRDA_RX_INT,
379 AU1000_USB_DEV_REQ_INT,
380 AU1000_USB_DEV_SUS_INT,
381 AU1000_USB_HOST_INT,
382 AU1000_ACSYNC_INT,
383 AU1000_MAC0_DMA_INT,
384 AU1000_MAC1_DMA_INT,
385 AU1000_I2S_UO_INT,
386 AU1000_AC97C_INT,
387 AU1000_GPIO0_INT,
388 AU1000_GPIO1_INT,
389 AU1000_GPIO2_INT,
390 AU1000_GPIO3_INT,
391 AU1000_GPIO4_INT,
392 AU1000_GPIO5_INT,
393 AU1000_GPIO6_INT,
394 AU1000_GPIO7_INT,
395 AU1000_GPIO8_INT,
396 AU1000_GPIO9_INT,
397 AU1000_GPIO10_INT,
398 AU1000_GPIO11_INT,
399 AU1000_GPIO12_INT,
400 AU1000_GPIO13_INT,
401 AU1000_GPIO14_INT,
402 AU1000_GPIO15_INT,
403 AU1000_GPIO16_INT,
404 AU1000_GPIO17_INT,
405 AU1000_GPIO18_INT,
406 AU1000_GPIO19_INT,
407 AU1000_GPIO20_INT,
408 AU1000_GPIO21_INT,
409 AU1000_GPIO22_INT,
410 AU1000_GPIO23_INT,
411 AU1000_GPIO24_INT,
412 AU1000_GPIO25_INT,
413 AU1000_GPIO26_INT,
414 AU1000_GPIO27_INT,
415 AU1000_GPIO28_INT,
416 AU1000_GPIO29_INT,
417 AU1000_GPIO30_INT,
418 AU1000_GPIO31_INT,
419};
420
421enum soc_au1100_ints {
422 AU1100_FIRST_INT = AU1000_INTC0_INT_BASE,
423 AU1100_UART0_INT = AU1100_FIRST_INT,
424 AU1100_UART1_INT,
425 AU1100_SD_INT,
426 AU1100_UART3_INT,
427 AU1100_SSI0_INT,
428 AU1100_SSI1_INT,
429 AU1100_DMA_INT_BASE,
430
431 AU1100_TOY_INT = AU1100_FIRST_INT + 14,
432 AU1100_TOY_MATCH0_INT,
433 AU1100_TOY_MATCH1_INT,
434 AU1100_TOY_MATCH2_INT,
435 AU1100_RTC_INT,
436 AU1100_RTC_MATCH0_INT,
437 AU1100_RTC_MATCH1_INT,
438 AU1100_RTC_MATCH2_INT,
439 AU1100_IRDA_TX_INT,
440 AU1100_IRDA_RX_INT,
441 AU1100_USB_DEV_REQ_INT,
442 AU1100_USB_DEV_SUS_INT,
443 AU1100_USB_HOST_INT,
444 AU1100_ACSYNC_INT,
445 AU1100_MAC0_DMA_INT,
446 AU1100_GPIO208_215_INT,
447 AU1100_LCD_INT,
448 AU1100_AC97C_INT,
449 AU1100_GPIO0_INT,
450 AU1100_GPIO1_INT,
451 AU1100_GPIO2_INT,
452 AU1100_GPIO3_INT,
453 AU1100_GPIO4_INT,
454 AU1100_GPIO5_INT,
455 AU1100_GPIO6_INT,
456 AU1100_GPIO7_INT,
457 AU1100_GPIO8_INT,
458 AU1100_GPIO9_INT,
459 AU1100_GPIO10_INT,
460 AU1100_GPIO11_INT,
461 AU1100_GPIO12_INT,
462 AU1100_GPIO13_INT,
463 AU1100_GPIO14_INT,
464 AU1100_GPIO15_INT,
465 AU1100_GPIO16_INT,
466 AU1100_GPIO17_INT,
467 AU1100_GPIO18_INT,
468 AU1100_GPIO19_INT,
469 AU1100_GPIO20_INT,
470 AU1100_GPIO21_INT,
471 AU1100_GPIO22_INT,
472 AU1100_GPIO23_INT,
473 AU1100_GPIO24_INT,
474 AU1100_GPIO25_INT,
475 AU1100_GPIO26_INT,
476 AU1100_GPIO27_INT,
477 AU1100_GPIO28_INT,
478 AU1100_GPIO29_INT,
479 AU1100_GPIO30_INT,
480 AU1100_GPIO31_INT,
481};
482
483enum soc_au1500_ints {
484 AU1500_FIRST_INT = AU1000_INTC0_INT_BASE,
485 AU1500_UART0_INT = AU1500_FIRST_INT,
486 AU1500_PCI_INTA,
487 AU1500_PCI_INTB,
488 AU1500_UART3_INT,
489 AU1500_PCI_INTC,
490 AU1500_PCI_INTD,
491 AU1500_DMA_INT_BASE,
492
493 AU1500_TOY_INT = AU1500_FIRST_INT + 14,
494 AU1500_TOY_MATCH0_INT,
495 AU1500_TOY_MATCH1_INT,
496 AU1500_TOY_MATCH2_INT,
497 AU1500_RTC_INT,
498 AU1500_RTC_MATCH0_INT,
499 AU1500_RTC_MATCH1_INT,
500 AU1500_RTC_MATCH2_INT,
501 AU1500_PCI_ERR_INT,
502 AU1500_RESERVED_INT,
503 AU1500_USB_DEV_REQ_INT,
504 AU1500_USB_DEV_SUS_INT,
505 AU1500_USB_HOST_INT,
506 AU1500_ACSYNC_INT,
507 AU1500_MAC0_DMA_INT,
508 AU1500_MAC1_DMA_INT,
509 AU1500_AC97C_INT = AU1500_FIRST_INT + 31,
510 AU1500_GPIO0_INT,
511 AU1500_GPIO1_INT,
512 AU1500_GPIO2_INT,
513 AU1500_GPIO3_INT,
514 AU1500_GPIO4_INT,
515 AU1500_GPIO5_INT,
516 AU1500_GPIO6_INT,
517 AU1500_GPIO7_INT,
518 AU1500_GPIO8_INT,
519 AU1500_GPIO9_INT,
520 AU1500_GPIO10_INT,
521 AU1500_GPIO11_INT,
522 AU1500_GPIO12_INT,
523 AU1500_GPIO13_INT,
524 AU1500_GPIO14_INT,
525 AU1500_GPIO15_INT,
526 AU1500_GPIO200_INT,
527 AU1500_GPIO201_INT,
528 AU1500_GPIO202_INT,
529 AU1500_GPIO203_INT,
530 AU1500_GPIO20_INT,
531 AU1500_GPIO204_INT,
532 AU1500_GPIO205_INT,
533 AU1500_GPIO23_INT,
534 AU1500_GPIO24_INT,
535 AU1500_GPIO25_INT,
536 AU1500_GPIO26_INT,
537 AU1500_GPIO27_INT,
538 AU1500_GPIO28_INT,
539 AU1500_GPIO206_INT,
540 AU1500_GPIO207_INT,
541 AU1500_GPIO208_215_INT,
542};
543
544enum soc_au1550_ints {
545 AU1550_FIRST_INT = AU1000_INTC0_INT_BASE,
546 AU1550_UART0_INT = AU1550_FIRST_INT,
547 AU1550_PCI_INTA,
548 AU1550_PCI_INTB,
549 AU1550_DDMA_INT,
550 AU1550_CRYPTO_INT,
551 AU1550_PCI_INTC,
552 AU1550_PCI_INTD,
553 AU1550_PCI_RST_INT,
554 AU1550_UART1_INT,
555 AU1550_UART3_INT,
556 AU1550_PSC0_INT,
557 AU1550_PSC1_INT,
558 AU1550_PSC2_INT,
559 AU1550_PSC3_INT,
560 AU1550_TOY_INT,
561 AU1550_TOY_MATCH0_INT,
562 AU1550_TOY_MATCH1_INT,
563 AU1550_TOY_MATCH2_INT,
564 AU1550_RTC_INT,
565 AU1550_RTC_MATCH0_INT,
566 AU1550_RTC_MATCH1_INT,
567 AU1550_RTC_MATCH2_INT,
568
569 AU1550_NAND_INT = AU1550_FIRST_INT + 23,
570 AU1550_USB_DEV_REQ_INT,
571 AU1550_USB_DEV_SUS_INT,
572 AU1550_USB_HOST_INT,
573 AU1550_MAC0_DMA_INT,
574 AU1550_MAC1_DMA_INT,
575 AU1550_GPIO0_INT = AU1550_FIRST_INT + 32,
576 AU1550_GPIO1_INT,
577 AU1550_GPIO2_INT,
578 AU1550_GPIO3_INT,
579 AU1550_GPIO4_INT,
580 AU1550_GPIO5_INT,
581 AU1550_GPIO6_INT,
582 AU1550_GPIO7_INT,
583 AU1550_GPIO8_INT,
584 AU1550_GPIO9_INT,
585 AU1550_GPIO10_INT,
586 AU1550_GPIO11_INT,
587 AU1550_GPIO12_INT,
588 AU1550_GPIO13_INT,
589 AU1550_GPIO14_INT,
590 AU1550_GPIO15_INT,
591 AU1550_GPIO200_INT,
70342287 592 AU1550_GPIO201_205_INT, /* Logical or of GPIO201:205 */
78814465
ML		 593 AU1550_GPIO16_INT,
594 AU1550_GPIO17_INT,
595 AU1550_GPIO20_INT,
596 AU1550_GPIO21_INT,
597 AU1550_GPIO22_INT,
598 AU1550_GPIO23_INT,
599 AU1550_GPIO24_INT,
600 AU1550_GPIO25_INT,
601 AU1550_GPIO26_INT,
602 AU1550_GPIO27_INT,
603 AU1550_GPIO28_INT,
604 AU1550_GPIO206_INT,
605 AU1550_GPIO207_INT,
70342287 606 AU1550_GPIO208_215_INT, /* Logical or of GPIO208:215 */
78814465
ML		 607};
608
609enum soc_au1200_ints {
610 AU1200_FIRST_INT = AU1000_INTC0_INT_BASE,
611 AU1200_UART0_INT = AU1200_FIRST_INT,
612 AU1200_SWT_INT,
613 AU1200_SD_INT,
614 AU1200_DDMA_INT,
615 AU1200_MAE_BE_INT,
616 AU1200_GPIO200_INT,
617 AU1200_GPIO201_INT,
618 AU1200_GPIO202_INT,
619 AU1200_UART1_INT,
620 AU1200_MAE_FE_INT,
621 AU1200_PSC0_INT,
622 AU1200_PSC1_INT,
623 AU1200_AES_INT,
624 AU1200_CAMERA_INT,
625 AU1200_TOY_INT,
626 AU1200_TOY_MATCH0_INT,
627 AU1200_TOY_MATCH1_INT,
628 AU1200_TOY_MATCH2_INT,
629 AU1200_RTC_INT,
630 AU1200_RTC_MATCH0_INT,
631 AU1200_RTC_MATCH1_INT,
632 AU1200_RTC_MATCH2_INT,
633 AU1200_GPIO203_INT,
634 AU1200_NAND_INT,
635 AU1200_GPIO204_INT,
636 AU1200_GPIO205_INT,
637 AU1200_GPIO206_INT,
638 AU1200_GPIO207_INT,
70342287 639 AU1200_GPIO208_215_INT, /* Logical OR of 208:215 */
78814465
ML		 640 AU1200_USB_INT,
641 AU1200_LCD_INT,
642 AU1200_MAE_BOTH_INT,
643 AU1200_GPIO0_INT,
644 AU1200_GPIO1_INT,
645 AU1200_GPIO2_INT,
646 AU1200_GPIO3_INT,
647 AU1200_GPIO4_INT,
648 AU1200_GPIO5_INT,
649 AU1200_GPIO6_INT,
650 AU1200_GPIO7_INT,
651 AU1200_GPIO8_INT,
652 AU1200_GPIO9_INT,
653 AU1200_GPIO10_INT,
654 AU1200_GPIO11_INT,
655 AU1200_GPIO12_INT,
656 AU1200_GPIO13_INT,
657 AU1200_GPIO14_INT,
658 AU1200_GPIO15_INT,
659 AU1200_GPIO16_INT,
660 AU1200_GPIO17_INT,
661 AU1200_GPIO18_INT,
662 AU1200_GPIO19_INT,
663 AU1200_GPIO20_INT,
664 AU1200_GPIO21_INT,
665 AU1200_GPIO22_INT,
666 AU1200_GPIO23_INT,
667 AU1200_GPIO24_INT,
668 AU1200_GPIO25_INT,
669 AU1200_GPIO26_INT,
670 AU1200_GPIO27_INT,
671 AU1200_GPIO28_INT,
672 AU1200_GPIO29_INT,
673 AU1200_GPIO30_INT,
674 AU1200_GPIO31_INT,
675};
676
1da177e4
LT		 677#endif /* !defined (_LANGUAGE_ASSEMBLY) */
678
809f36c6
ML		 679/* Au1300 peripheral interrupt numbers */
680#define AU1300_FIRST_INT (ALCHEMY_GPIC_INT_BASE)
681#define AU1300_UART1_INT (AU1300_FIRST_INT + 17)
682#define AU1300_UART2_INT (AU1300_FIRST_INT + 25)
683#define AU1300_UART3_INT (AU1300_FIRST_INT + 27)
684#define AU1300_SD1_INT (AU1300_FIRST_INT + 32)
685#define AU1300_SD2_INT (AU1300_FIRST_INT + 38)
686#define AU1300_PSC0_INT (AU1300_FIRST_INT + 48)
687#define AU1300_PSC1_INT (AU1300_FIRST_INT + 52)
688#define AU1300_PSC2_INT (AU1300_FIRST_INT + 56)
689#define AU1300_PSC3_INT (AU1300_FIRST_INT + 60)
690#define AU1300_NAND_INT (AU1300_FIRST_INT + 62)
691#define AU1300_DDMA_INT (AU1300_FIRST_INT + 75)
692#define AU1300_MMU_INT (AU1300_FIRST_INT + 76)
693#define AU1300_MPU_INT (AU1300_FIRST_INT + 77)
694#define AU1300_GPU_INT (AU1300_FIRST_INT + 78)
695#define AU1300_UDMA_INT (AU1300_FIRST_INT + 79)
696#define AU1300_TOY_INT (AU1300_FIRST_INT + 80)
697#define AU1300_TOY_MATCH0_INT (AU1300_FIRST_INT + 81)
698#define AU1300_TOY_MATCH1_INT (AU1300_FIRST_INT + 82)
699#define AU1300_TOY_MATCH2_INT (AU1300_FIRST_INT + 83)
700#define AU1300_RTC_INT (AU1300_FIRST_INT + 84)
701#define AU1300_RTC_MATCH0_INT (AU1300_FIRST_INT + 85)
702#define AU1300_RTC_MATCH1_INT (AU1300_FIRST_INT + 86)
703#define AU1300_RTC_MATCH2_INT (AU1300_FIRST_INT + 87)
704#define AU1300_UART0_INT (AU1300_FIRST_INT + 88)
705#define AU1300_SD0_INT (AU1300_FIRST_INT + 89)
706#define AU1300_USB_INT (AU1300_FIRST_INT + 90)
707#define AU1300_LCD_INT (AU1300_FIRST_INT + 91)
708#define AU1300_BSA_INT (AU1300_FIRST_INT + 92)
709#define AU1300_MPE_INT (AU1300_FIRST_INT + 93)
710#define AU1300_ITE_INT (AU1300_FIRST_INT + 94)
711#define AU1300_AES_INT (AU1300_FIRST_INT + 95)
712#define AU1300_CIM_INT (AU1300_FIRST_INT + 96)
713
714/**********************************************************************/
715
e3ad1c23
PP		 716/*
717 * Physical base addresses for integrated peripherals
809f36c6 718 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300
e3ad1c23
PP		 719 */
720
5d4ddcb4 721#define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */
809f36c6
ML		 722#define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */
723#define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */
724#define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */
725#define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */
726#define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */
727#define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */
728#define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */
ce6bc922
ML		 729#define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */
730#define AU1000_USB_UDC_PHYS_ADDR 0x10200000 /* 0123 */
809f36c6 731#define AU1300_GPIC_PHYS_ADDR 0x10200000 /* 5 */
7cc2e272 732#define AU1000_IRDA_PHYS_ADDR 0x10300000 /* 02 */
809f36c6 733#define AU1200_AES_PHYS_ADDR 0x10300000 /* 45 */
dca75871 734#define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */
809f36c6 735#define AU1300_GPU_PHYS_ADDR 0x10500000 /* 5 */
40d8bc28
ML		 736#define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */
737#define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */
738#define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */
809f36c6
ML		 739#define AU1100_SD0_PHYS_ADDR 0x10600000 /* 245 */
740#define AU1300_SD1_PHYS_ADDR 0x10601000 /* 5 */
741#define AU1300_SD2_PHYS_ADDR 0x10602000 /* 5 */
5d4ddcb4 742#define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */
809f36c6 743#define AU1300_SYS_PHYS_ADDR 0x10900000 /* 5 */
7cc2e272
ML		 744#define AU1550_PSC2_PHYS_ADDR 0x10A00000 /* 3 */
745#define AU1550_PSC3_PHYS_ADDR 0x10B00000 /* 3 */
809f36c6
ML		 746#define AU1300_PSC0_PHYS_ADDR 0x10A00000 /* 5 */
747#define AU1300_PSC1_PHYS_ADDR 0x10A01000 /* 5 */
748#define AU1300_PSC2_PHYS_ADDR 0x10A02000 /* 5 */
749#define AU1300_PSC3_PHYS_ADDR 0x10A03000 /* 5 */
5d4ddcb4 750#define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */
40d8bc28
ML		 751#define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */
752#define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */
753#define AU1500_MACEN_PHYS_ADDR 0x11520000 /* 1 */
80130204 754#define AU1000_UART0_PHYS_ADDR 0x11100000 /* 01234 */
7cc2e272 755#define AU1200_SWCNT_PHYS_ADDR 0x1110010C /* 4 */
80130204
ML		 756#define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */
757#define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */
758#define AU1000_UART3_PHYS_ADDR 0x11400000 /* 0123 */
7cc2e272
ML		 759#define AU1000_SSI0_PHYS_ADDR 0x11600000 /* 02 */
760#define AU1000_SSI1_PHYS_ADDR 0x11680000 /* 02 */
b7f720d6 761#define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */
dca75871 762#define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */
809f36c6 763#define AU1000_SYS_PHYS_ADDR 0x11900000 /* 012345 */
7cc2e272
ML		 764#define AU1550_PSC0_PHYS_ADDR 0x11A00000 /* 34 */
765#define AU1550_PSC1_PHYS_ADDR 0x11B00000 /* 34 */
766#define AU1000_MEM_PHYS_ADDR 0x14000000 /* 01234 */
767#define AU1000_STATIC_MEM_PHYS_ADDR 0x14001000 /* 01234 */
809f36c6 768#define AU1300_UDMA_PHYS_ADDR 0x14001800 /* 5 */
5d4ddcb4 769#define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */
809f36c6
ML		 770#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 345 */
771#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 345 */
40d8bc28
ML		 772#define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */
773#define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */
809f36c6 774#define AU1200_CIM_PHYS_ADDR 0x14004000 /* 45 */
7cc2e272
ML		 775#define AU1500_PCI_PHYS_ADDR 0x14005000 /* 13 */
776#define AU1550_PE_PHYS_ADDR 0x14008000 /* 3 */
777#define AU1200_MAEBE_PHYS_ADDR 0x14010000 /* 4 */
778#define AU1200_MAEFE_PHYS_ADDR 0x14012000 /* 4 */
809f36c6
ML		 779#define AU1300_MAEITE_PHYS_ADDR 0x14010000 /* 5 */
780#define AU1300_MAEMPE_PHYS_ADDR 0x14014000 /* 5 */
ce6bc922
ML		 781#define AU1550_USB_OHCI_PHYS_ADDR 0x14020000 /* 3 */
782#define AU1200_USB_CTL_PHYS_ADDR 0x14020000 /* 4 */
783#define AU1200_USB_OTG_PHYS_ADDR 0x14020020 /* 4 */
784#define AU1200_USB_OHCI_PHYS_ADDR 0x14020100 /* 4 */
785#define AU1200_USB_EHCI_PHYS_ADDR 0x14020200 /* 4 */
786#define AU1200_USB_UDC_PHYS_ADDR 0x14022000 /* 4 */
809f36c6
ML		 787#define AU1300_USB_EHCI_PHYS_ADDR 0x14020000 /* 5 */
788#define AU1300_USB_OHCI0_PHYS_ADDR 0x14020400 /* 5 */
789#define AU1300_USB_OHCI1_PHYS_ADDR 0x14020800 /* 5 */
790#define AU1300_USB_CTL_PHYS_ADDR 0x14021000 /* 5 */
791#define AU1300_USB_OTG_PHYS_ADDR 0x14022000 /* 5 */
792#define AU1300_MAEBSA_PHYS_ADDR 0x14030000 /* 5 */
7cc2e272 793#define AU1100_LCD_PHYS_ADDR 0x15000000 /* 2 */
809f36c6 794#define AU1200_LCD_PHYS_ADDR 0x15000000 /* 45 */
7cc2e272
ML		 795#define AU1500_PCI_MEM_PHYS_ADDR 0x400000000ULL /* 13 */
796#define AU1500_PCI_IO_PHYS_ADDR 0x500000000ULL /* 13 */
797#define AU1500_PCI_CONFIG0_PHYS_ADDR 0x600000000ULL /* 13 */
798#define AU1500_PCI_CONFIG1_PHYS_ADDR 0x680000000ULL /* 13 */
809f36c6
ML		 799#define AU1000_PCMCIA_IO_PHYS_ADDR 0xF00000000ULL /* 012345 */
800#define AU1000_PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL /* 012345 */
801#define AU1000_PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL /* 012345 */
802
803/**********************************************************************/
dca75871
ML		 804
805
809f36c6
ML		 806/*
807 * Au1300 GPIO+INT controller (GPIC) register offsets and bits
808 * Registers are 128bits (0x10 bytes), divided into 4 "banks".
809 */
810#define AU1300_GPIC_PINVAL 0x0000
811#define AU1300_GPIC_PINVALCLR 0x0010
812#define AU1300_GPIC_IPEND 0x0020
813#define AU1300_GPIC_PRIENC 0x0030
814#define AU1300_GPIC_IEN 0x0040 /* int_mask in manual */
815#define AU1300_GPIC_IDIS 0x0050 /* int_maskclr in manual */
816#define AU1300_GPIC_DMASEL 0x0060
817#define AU1300_GPIC_DEVSEL 0x0080
818#define AU1300_GPIC_DEVCLR 0x0090
819#define AU1300_GPIC_RSTVAL 0x00a0
820/* pin configuration space. one 32bit register for up to 128 IRQs */
821#define AU1300_GPIC_PINCFG 0x1000
822
823#define GPIC_GPIO_TO_BIT(gpio) \
824 (1 << ((gpio) & 0x1f))
825
70342287 826#define GPIC_GPIO_BANKOFF(gpio) \
809f36c6
ML		 827 (((gpio) >> 5) * 4)
828
829/* Pin Control bits: who owns the pin, what does it do */
830#define GPIC_CFG_PC_GPIN 0
831#define GPIC_CFG_PC_DEV 1
832#define GPIC_CFG_PC_GPOLOW 2
833#define GPIC_CFG_PC_GPOHIGH 3
834#define GPIC_CFG_PC_MASK 3
835
836/* assign pin to MIPS IRQ line */
837#define GPIC_CFG_IL_SET(x) (((x) & 3) << 2)
838#define GPIC_CFG_IL_MASK (3 << 2)
839
840/* pin interrupt type setup */
841#define GPIC_CFG_IC_OFF (0 << 4)
842#define GPIC_CFG_IC_LEVEL_LOW (1 << 4)
843#define GPIC_CFG_IC_LEVEL_HIGH (2 << 4)
844#define GPIC_CFG_IC_EDGE_FALL (5 << 4)
845#define GPIC_CFG_IC_EDGE_RISE (6 << 4)
846#define GPIC_CFG_IC_EDGE_BOTH (7 << 4)
847#define GPIC_CFG_IC_MASK (7 << 4)
848
849/* allow interrupt to wake cpu from 'wait' */
850#define GPIC_CFG_IDLEWAKE (1 << 7)
851
852/***********************************************************************/
853
37663860
ML		 854/* Au1000 SDRAM memory controller register offsets */
855#define AU1000_MEM_SDMODE0 0x0000
856#define AU1000_MEM_SDMODE1 0x0004
857#define AU1000_MEM_SDMODE2 0x0008
858#define AU1000_MEM_SDADDR0 0x000C
859#define AU1000_MEM_SDADDR1 0x0010
860#define AU1000_MEM_SDADDR2 0x0014
861#define AU1000_MEM_SDREFCFG 0x0018
862#define AU1000_MEM_SDPRECMD 0x001C
863#define AU1000_MEM_SDAUTOREF 0x0020
864#define AU1000_MEM_SDWRMD0 0x0024
865#define AU1000_MEM_SDWRMD1 0x0028
866#define AU1000_MEM_SDWRMD2 0x002C
867#define AU1000_MEM_SDSLEEP 0x0030
868#define AU1000_MEM_SDSMCKE 0x0034
869
870/* MEM_SDMODE register content definitions */
871#define MEM_SDMODE_F (1 << 22)
872#define MEM_SDMODE_SR (1 << 21)
873#define MEM_SDMODE_BS (1 << 20)
874#define MEM_SDMODE_RS (3 << 18)
875#define MEM_SDMODE_CS (7 << 15)
876#define MEM_SDMODE_TRAS (15 << 11)
877#define MEM_SDMODE_TMRD (3 << 9)
878#define MEM_SDMODE_TWR (3 << 7)
879#define MEM_SDMODE_TRP (3 << 5)
880#define MEM_SDMODE_TRCD (3 << 3)
881#define MEM_SDMODE_TCL (7 << 0)
882
883#define MEM_SDMODE_BS_2Bank (0 << 20)
884#define MEM_SDMODE_BS_4Bank (1 << 20)
885#define MEM_SDMODE_RS_11Row (0 << 18)
886#define MEM_SDMODE_RS_12Row (1 << 18)
887#define MEM_SDMODE_RS_13Row (2 << 18)
888#define MEM_SDMODE_RS_N(N) ((N) << 18)
889#define MEM_SDMODE_CS_7Col (0 << 15)
890#define MEM_SDMODE_CS_8Col (1 << 15)
891#define MEM_SDMODE_CS_9Col (2 << 15)
892#define MEM_SDMODE_CS_10Col (3 << 15)
893#define MEM_SDMODE_CS_11Col (4 << 15)
894#define MEM_SDMODE_CS_N(N) ((N) << 15)
895#define MEM_SDMODE_TRAS_N(N) ((N) << 11)
896#define MEM_SDMODE_TMRD_N(N) ((N) << 9)
897#define MEM_SDMODE_TWR_N(N) ((N) << 7)
898#define MEM_SDMODE_TRP_N(N) ((N) << 5)
899#define MEM_SDMODE_TRCD_N(N) ((N) << 3)
900#define MEM_SDMODE_TCL_N(N) ((N) << 0)
901
902/* MEM_SDADDR register contents definitions */
903#define MEM_SDADDR_E (1 << 20)
904#define MEM_SDADDR_CSBA (0x03FF << 10)
905#define MEM_SDADDR_CSMASK (0x03FF << 0)
906#define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12)
907#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22)
908
909/* MEM_SDREFCFG register content definitions */
910#define MEM_SDREFCFG_TRC (15 << 28)
911#define MEM_SDREFCFG_TRPM (3 << 26)
912#define MEM_SDREFCFG_E (1 << 25)
913#define MEM_SDREFCFG_RE (0x1ffffff << 0)
914#define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC)
915#define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM)
916#define MEM_SDREFCFG_REF_N(N) (N)
917
918/* Au1550 SDRAM Register Offsets */
919#define AU1550_MEM_SDMODE0 0x0800
920#define AU1550_MEM_SDMODE1 0x0808
921#define AU1550_MEM_SDMODE2 0x0810
922#define AU1550_MEM_SDADDR0 0x0820
923#define AU1550_MEM_SDADDR1 0x0828
924#define AU1550_MEM_SDADDR2 0x0830
925#define AU1550_MEM_SDCONFIGA 0x0840
926#define AU1550_MEM_SDCONFIGB 0x0848
927#define AU1550_MEM_SDSTAT 0x0850
928#define AU1550_MEM_SDERRADDR 0x0858
929#define AU1550_MEM_SDSTRIDE0 0x0860
930#define AU1550_MEM_SDSTRIDE1 0x0868
931#define AU1550_MEM_SDSTRIDE2 0x0870
932#define AU1550_MEM_SDWRMD0 0x0880
933#define AU1550_MEM_SDWRMD1 0x0888
934#define AU1550_MEM_SDWRMD2 0x0890
935#define AU1550_MEM_SDPRECMD 0x08C0
936#define AU1550_MEM_SDAUTOREF 0x08C8
937#define AU1550_MEM_SDSREF 0x08D0
938#define AU1550_MEM_SDSLEEP MEM_SDSREF
939
1da177e4 940/* Static Bus Controller */
ff6814d5
SS		 941#define MEM_STCFG0 0xB4001000
942#define MEM_STTIME0 0xB4001004
943#define MEM_STADDR0 0xB4001008
1da177e4 944
ff6814d5
SS		 945#define MEM_STCFG1 0xB4001010
946#define MEM_STTIME1 0xB4001014
947#define MEM_STADDR1 0xB4001018
1da177e4 948
ff6814d5
SS		 949#define MEM_STCFG2 0xB4001020
950#define MEM_STTIME2 0xB4001024
951#define MEM_STADDR2 0xB4001028
1da177e4 952
ff6814d5
SS		 953#define MEM_STCFG3 0xB4001030
954#define MEM_STTIME3 0xB4001034
955#define MEM_STADDR3 0xB4001038
1da177e4 956
ff6814d5
SS		 957#define MEM_STNDCTL 0xB4001100
958#define MEM_STSTAT 0xB4001104
1da177e4 959
ff6814d5 960#define MEM_STNAND_CMD 0x0
70342287
RB		 961#define MEM_STNAND_ADDR 0x4
962#define MEM_STNAND_DATA 0x20
1da177e4 963
0f0d85bc 964
1da177e4 965/* Programmable Counters 0 and 1 */
ff6814d5
SS		 966#define SYS_BASE 0xB1900000
967#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
70342287
RB		 968# define SYS_CNTRL_E1S (1 << 23)
969# define SYS_CNTRL_T1S (1 << 20)
970# define SYS_CNTRL_M21 (1 << 19)
971# define SYS_CNTRL_M11 (1 << 18)
972# define SYS_CNTRL_M01 (1 << 17)
973# define SYS_CNTRL_C1S (1 << 16)
ff6814d5 974# define SYS_CNTRL_BP (1 << 14)
70342287
RB		 975# define SYS_CNTRL_EN1 (1 << 13)
976# define SYS_CNTRL_BT1 (1 << 12)
977# define SYS_CNTRL_EN0 (1 << 11)
978# define SYS_CNTRL_BT0 (1 << 10)
ff6814d5 979# define SYS_CNTRL_E0 (1 << 8)
70342287
RB		 980# define SYS_CNTRL_E0S (1 << 7)
981# define SYS_CNTRL_32S (1 << 5)
982# define SYS_CNTRL_T0S (1 << 4)
983# define SYS_CNTRL_M20 (1 << 3)
984# define SYS_CNTRL_M10 (1 << 2)
985# define SYS_CNTRL_M00 (1 << 1)
986# define SYS_CNTRL_C0S (1 << 0)
1da177e4
LT		 987
988/* Programmable Counter 0 Registers */
ff6814d5
SS		 989#define SYS_TOYTRIM (SYS_BASE + 0)
990#define SYS_TOYWRITE (SYS_BASE + 4)
991#define SYS_TOYMATCH0 (SYS_BASE + 8)
992#define SYS_TOYMATCH1 (SYS_BASE + 0xC)
993#define SYS_TOYMATCH2 (SYS_BASE + 0x10)
994#define SYS_TOYREAD (SYS_BASE + 0x40)
1da177e4
LT		 995
996/* Programmable Counter 1 Registers */
ff6814d5
SS		 997#define SYS_RTCTRIM (SYS_BASE + 0x44)
998#define SYS_RTCWRITE (SYS_BASE + 0x48)
999#define SYS_RTCMATCH0 (SYS_BASE + 0x4C)
1000#define SYS_RTCMATCH1 (SYS_BASE + 0x50)
1001#define SYS_RTCMATCH2 (SYS_BASE + 0x54)
1002#define SYS_RTCREAD (SYS_BASE + 0x58)
1da177e4
LT		 1003
1004/* I2S Controller */
ff6814d5 1005#define I2S_DATA 0xB1000000
70342287 1006# define I2S_DATA_MASK 0xffffff
ff6814d5 1007#define I2S_CONFIG 0xB1000004
70342287
RB		 1008# define I2S_CONFIG_XU (1 << 25)
1009# define I2S_CONFIG_XO (1 << 24)
1010# define I2S_CONFIG_RU (1 << 23)
1011# define I2S_CONFIG_RO (1 << 22)
1012# define I2S_CONFIG_TR (1 << 21)
1013# define I2S_CONFIG_TE (1 << 20)
1014# define I2S_CONFIG_TF (1 << 19)
1015# define I2S_CONFIG_RR (1 << 18)
1016# define I2S_CONFIG_RE (1 << 17)
1017# define I2S_CONFIG_RF (1 << 16)
1018# define I2S_CONFIG_PD (1 << 11)
1019# define I2S_CONFIG_LB (1 << 10)
1020# define I2S_CONFIG_IC (1 << 9)
ff6814d5
SS		 1021# define I2S_CONFIG_FM_BIT 7
1022# define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
1023# define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
1024# define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
1025# define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
70342287
RB		 1026# define I2S_CONFIG_TN (1 << 6)
1027# define I2S_CONFIG_RN (1 << 5)
ff6814d5
SS		 1028# define I2S_CONFIG_SZ_BIT 0
1029# define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
1030
1031#define I2S_CONTROL 0xB1000008
70342287 1032# define I2S_CONTROL_D (1 << 1)
ff6814d5 1033# define I2S_CONTROL_CE (1 << 0)
1da177e4 1034
e3ad1c23 1035
1da177e4
LT		 1036/* Ethernet Controllers */
1037
1038/* 4 byte offsets from AU1000_ETH_BASE */
ff6814d5 1039#define MAC_CONTROL 0x0
70342287
RB		 1040# define MAC_RX_ENABLE (1 << 2)
1041# define MAC_TX_ENABLE (1 << 3)
1042# define MAC_DEF_CHECK (1 << 5)
1043# define MAC_SET_BL(X) (((X) & 0x3) << 6)
ff6814d5
SS		 1044# define MAC_AUTO_PAD (1 << 8)
1045# define MAC_DISABLE_RETRY (1 << 10)
1046# define MAC_DISABLE_BCAST (1 << 11)
1047# define MAC_LATE_COL (1 << 12)
70342287
RB		 1048# define MAC_HASH_MODE (1 << 13)
1049# define MAC_HASH_ONLY (1 << 15)
ff6814d5
SS		 1050# define MAC_PASS_ALL (1 << 16)
1051# define MAC_INVERSE_FILTER (1 << 17)
1052# define MAC_PROMISCUOUS (1 << 18)
1053# define MAC_PASS_ALL_MULTI (1 << 19)
1054# define MAC_FULL_DUPLEX (1 << 20)
1055# define MAC_NORMAL_MODE 0
1056# define MAC_INT_LOOPBACK (1 << 21)
1057# define MAC_EXT_LOOPBACK (1 << 22)
1058# define MAC_DISABLE_RX_OWN (1 << 23)
1059# define MAC_BIG_ENDIAN (1 << 30)
1060# define MAC_RX_ALL (1 << 31)
1061#define MAC_ADDRESS_HIGH 0x4
1062#define MAC_ADDRESS_LOW 0x8
1063#define MAC_MCAST_HIGH 0xC
1064#define MAC_MCAST_LOW 0x10
1065#define MAC_MII_CNTRL 0x14
1066# define MAC_MII_BUSY (1 << 0)
1067# define MAC_MII_READ 0
1068# define MAC_MII_WRITE (1 << 1)
1069# define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6)
1070# define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11)
1071#define MAC_MII_DATA 0x18
1072#define MAC_FLOW_CNTRL 0x1C
1073# define MAC_FLOW_CNTRL_BUSY (1 << 0)
1074# define MAC_FLOW_CNTRL_ENABLE (1 << 1)
1075# define MAC_PASS_CONTROL (1 << 2)
1076# define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16)
1077#define MAC_VLAN1_TAG 0x20
1078#define MAC_VLAN2_TAG 0x24
1da177e4
LT		 1079
1080/* Ethernet Controller Enable */
1081
ff6814d5
SS		 1082# define MAC_EN_CLOCK_ENABLE (1 << 0)
1083# define MAC_EN_RESET0 (1 << 1)
1084# define MAC_EN_TOSS (0 << 2)
1085# define MAC_EN_CACHEABLE (1 << 3)
70342287
RB		 1086# define MAC_EN_RESET1 (1 << 4)
1087# define MAC_EN_RESET2 (1 << 5)
1088# define MAC_DMA_RESET (1 << 6)
1da177e4
LT		 1089
1090/* Ethernet Controller DMA Channels */
1091
ff6814d5
SS		 1092#define MAC0_TX_DMA_ADDR 0xB4004000
1093#define MAC1_TX_DMA_ADDR 0xB4004200
1da177e4 1094/* offsets from MAC_TX_RING_ADDR address */
ff6814d5
SS		 1095#define MAC_TX_BUFF0_STATUS 0x0
1096# define TX_FRAME_ABORTED (1 << 0)
1097# define TX_JAB_TIMEOUT (1 << 1)
70342287 1098# define TX_NO_CARRIER (1 << 2)
ff6814d5
SS		 1099# define TX_LOSS_CARRIER (1 << 3)
1100# define TX_EXC_DEF (1 << 4)
1101# define TX_LATE_COLL_ABORT (1 << 5)
1102# define TX_EXC_COLL (1 << 6)
1103# define TX_UNDERRUN (1 << 7)
1104# define TX_DEFERRED (1 << 8)
1105# define TX_LATE_COLL (1 << 9)
1106# define TX_COLL_CNT_MASK (0xF << 10)
1107# define TX_PKT_RETRY (1 << 31)
1108#define MAC_TX_BUFF0_ADDR 0x4
70342287 1109# define TX_DMA_ENABLE (1 << 0)
ff6814d5
SS		 1110# define TX_T_DONE (1 << 1)
1111# define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
1112#define MAC_TX_BUFF0_LEN 0x8
1113#define MAC_TX_BUFF1_STATUS 0x10
1114#define MAC_TX_BUFF1_ADDR 0x14
1115#define MAC_TX_BUFF1_LEN 0x18
1116#define MAC_TX_BUFF2_STATUS 0x20
1117#define MAC_TX_BUFF2_ADDR 0x24
1118#define MAC_TX_BUFF2_LEN 0x28
1119#define MAC_TX_BUFF3_STATUS 0x30
1120#define MAC_TX_BUFF3_ADDR 0x34
1121#define MAC_TX_BUFF3_LEN 0x38
1122
1123#define MAC0_RX_DMA_ADDR 0xB4004100
1124#define MAC1_RX_DMA_ADDR 0xB4004300
1da177e4 1125/* offsets from MAC_RX_RING_ADDR */
ff6814d5
SS		 1126#define MAC_RX_BUFF0_STATUS 0x0
1127# define RX_FRAME_LEN_MASK 0x3fff
70342287 1128# define RX_WDOG_TIMER (1 << 14)
ff6814d5
SS		 1129# define RX_RUNT (1 << 15)
1130# define RX_OVERLEN (1 << 16)
1131# define RX_COLL (1 << 17)
1132# define RX_ETHER (1 << 18)
1133# define RX_MII_ERROR (1 << 19)
1134# define RX_DRIBBLING (1 << 20)
1135# define RX_CRC_ERROR (1 << 21)
1136# define RX_VLAN1 (1 << 22)
1137# define RX_VLAN2 (1 << 23)
1138# define RX_LEN_ERROR (1 << 24)
1139# define RX_CNTRL_FRAME (1 << 25)
1140# define RX_U_CNTRL_FRAME (1 << 26)
1141# define RX_MCAST_FRAME (1 << 27)
1142# define RX_BCAST_FRAME (1 << 28)
1143# define RX_FILTER_FAIL (1 << 29)
1144# define RX_PACKET_FILTER (1 << 30)
1145# define RX_MISSED_FRAME (1 << 31)
49a89efb
RB		 1146
1147# define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
ff6814d5
SS		 1148 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
1149 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
1150#define MAC_RX_BUFF0_ADDR 0x4
70342287 1151# define RX_DMA_ENABLE (1 << 0)
ff6814d5
SS		 1152# define RX_T_DONE (1 << 1)
1153# define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
1154# define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0)
1155#define MAC_RX_BUFF1_STATUS 0x10
1156#define MAC_RX_BUFF1_ADDR 0x14
1157#define MAC_RX_BUFF2_STATUS 0x20
1158#define MAC_RX_BUFF2_ADDR 0x24
1159#define MAC_RX_BUFF3_STATUS 0x30
1160#define MAC_RX_BUFF3_ADDR 0x34
1da177e4 1161
1da177e4
LT		 1162#define UART_RX 0 /* Receive buffer */
1163#define UART_TX 4 /* Transmit buffer */
1164#define UART_IER 8 /* Interrupt Enable Register */
1165#define UART_IIR 0xC /* Interrupt ID Register */
1166#define UART_FCR 0x10 /* FIFO Control Register */
1167#define UART_LCR 0x14 /* Line Control Register */
1168#define UART_MCR 0x18 /* Modem Control Register */
1169#define UART_LSR 0x1C /* Line Status Register */
1170#define UART_MSR 0x20 /* Modem Status Register */
1171#define UART_CLK 0x28 /* Baud Rate Clock Divider */
1172#define UART_MOD_CNTRL 0x100 /* Module Control */
1173
1da177e4 1174/* SSIO */
ff6814d5 1175#define SSI0_STATUS 0xB1600000
70342287
RB		 1176# define SSI_STATUS_BF (1 << 4)
1177# define SSI_STATUS_OF (1 << 3)
1178# define SSI_STATUS_UF (1 << 2)
ff6814d5
SS		 1179# define SSI_STATUS_D (1 << 1)
1180# define SSI_STATUS_B (1 << 0)
1181#define SSI0_INT 0xB1600004
1182# define SSI_INT_OI (1 << 3)
1183# define SSI_INT_UI (1 << 2)
1184# define SSI_INT_DI (1 << 1)
70342287 1185#define SSI0_INT_ENABLE 0xB1600008
ff6814d5
SS		 1186# define SSI_INTE_OIE (1 << 3)
1187# define SSI_INTE_UIE (1 << 2)
1188# define SSI_INTE_DIE (1 << 1)
1189#define SSI0_CONFIG 0xB1600020
70342287
RB		 1190# define SSI_CONFIG_AO (1 << 24)
1191# define SSI_CONFIG_DO (1 << 23)
ff6814d5
SS		 1192# define SSI_CONFIG_ALEN_BIT 20
1193# define SSI_CONFIG_ALEN_MASK (0x7 << 20)
1194# define SSI_CONFIG_DLEN_BIT 16
1195# define SSI_CONFIG_DLEN_MASK (0x7 << 16)
70342287
RB		 1196# define SSI_CONFIG_DD (1 << 11)
1197# define SSI_CONFIG_AD (1 << 10)
ff6814d5
SS		 1198# define SSI_CONFIG_BM_BIT 8
1199# define SSI_CONFIG_BM_MASK (0x3 << 8)
70342287
RB		 1200# define SSI_CONFIG_CE (1 << 7)
1201# define SSI_CONFIG_DP (1 << 6)
1202# define SSI_CONFIG_DL (1 << 5)
1203# define SSI_CONFIG_EP (1 << 4)
ff6814d5
SS		 1204#define SSI0_ADATA 0xB1600024
1205# define SSI_AD_D (1 << 24)
1206# define SSI_AD_ADDR_BIT 16
1207# define SSI_AD_ADDR_MASK (0xff << 16)
1208# define SSI_AD_DATA_BIT 0
1209# define SSI_AD_DATA_MASK (0xfff << 0)
1210#define SSI0_CLKDIV 0xB1600028
1211#define SSI0_CONTROL 0xB1600100
1212# define SSI_CONTROL_CD (1 << 1)
70342287 1213# define SSI_CONTROL_E (1 << 0)
1da177e4
LT		 1214
1215/* SSI1 */
ff6814d5
SS		 1216#define SSI1_STATUS 0xB1680000
1217#define SSI1_INT 0xB1680004
70342287 1218#define SSI1_INT_ENABLE 0xB1680008
ff6814d5
SS		 1219#define SSI1_CONFIG 0xB1680020
1220#define SSI1_ADATA 0xB1680024
1221#define SSI1_CLKDIV 0xB1680028
1222#define SSI1_ENABLE 0xB1680100
1da177e4
LT		 1223
1224/*
1225 * Register content definitions
1226 */
ff6814d5
SS		 1227#define SSI_STATUS_BF (1 << 4)
1228#define SSI_STATUS_OF (1 << 3)
1229#define SSI_STATUS_UF (1 << 2)
1230#define SSI_STATUS_D (1 << 1)
1231#define SSI_STATUS_B (1 << 0)
1da177e4
LT		 1232
1233/* SSI_INT */
ff6814d5
SS		 1234#define SSI_INT_OI (1 << 3)
1235#define SSI_INT_UI (1 << 2)
1236#define SSI_INT_DI (1 << 1)
1da177e4
LT		 1237
1238/* SSI_INTEN */
ff6814d5
SS		 1239#define SSI_INTEN_OIE (1 << 3)
1240#define SSI_INTEN_UIE (1 << 2)
1241#define SSI_INTEN_DIE (1 << 1)
1242
1243#define SSI_CONFIG_AO (1 << 24)
1244#define SSI_CONFIG_DO (1 << 23)
70342287
RB		 1245#define SSI_CONFIG_ALEN (7 << 20)
1246#define SSI_CONFIG_DLEN (15 << 16)
ff6814d5
SS		 1247#define SSI_CONFIG_DD (1 << 11)
1248#define SSI_CONFIG_AD (1 << 10)
1249#define SSI_CONFIG_BM (3 << 8)
1250#define SSI_CONFIG_CE (1 << 7)
1251#define SSI_CONFIG_DP (1 << 6)
1252#define SSI_CONFIG_DL (1 << 5)
1253#define SSI_CONFIG_EP (1 << 4)
1254#define SSI_CONFIG_ALEN_N(N) ((N-1) << 20)
1255#define SSI_CONFIG_DLEN_N(N) ((N-1) << 16)
1256#define SSI_CONFIG_BM_HI (0 << 8)
1257#define SSI_CONFIG_BM_LO (1 << 8)
1258#define SSI_CONFIG_BM_CY (2 << 8)
1259
1260#define SSI_ADATA_D (1 << 24)
1261#define SSI_ADATA_ADDR (0xFF << 16)
1262#define SSI_ADATA_DATA 0x0FFF
1263#define SSI_ADATA_ADDR_N(N) (N << 16)
1264
1265#define SSI_ENABLE_CD (1 << 1)
1266#define SSI_ENABLE_E (1 << 0)
1da177e4 1267
cd671c16
ML		 1268
1269/*
1270 * The IrDA peripheral has an IRFIRSEL pin, but on the DB/PB boards it's not
1271 * used to select FIR/SIR mode on the transceiver but as a GPIO. Instead a
1272 * CPLD has to be told about the mode.
1273 */
1274#define AU1000_IRDA_PHY_MODE_OFF 0
1275#define AU1000_IRDA_PHY_MODE_SIR 1
1276#define AU1000_IRDA_PHY_MODE_FIR 2
1277
1278struct au1k_irda_platform_data {
1279 void(*set_phy_mode)(int mode);
1280};
1281
1da177e4
LT		 1282
1283/* GPIO */
ff6814d5
SS		 1284#define SYS_PINFUNC 0xB190002C
1285# define SYS_PF_USB (1 << 15) /* 2nd USB device/host */
1286# define SYS_PF_U3 (1 << 14) /* GPIO23/U3TXD */
1287# define SYS_PF_U2 (1 << 13) /* GPIO22/U2TXD */
1288# define SYS_PF_U1 (1 << 12) /* GPIO21/U1TXD */
1289# define SYS_PF_SRC (1 << 11) /* GPIO6/SROMCKE */
1290# define SYS_PF_CK5 (1 << 10) /* GPIO3/CLK5 */
1291# define SYS_PF_CK4 (1 << 9) /* GPIO2/CLK4 */
1292# define SYS_PF_IRF (1 << 8) /* GPIO15/IRFIRSEL */
1293# define SYS_PF_UR3 (1 << 7) /* GPIO[14:9]/UART3 */
1294# define SYS_PF_I2D (1 << 6) /* GPIO8/I2SDI */
1295# define SYS_PF_I2S (1 << 5) /* I2S/GPIO[29:31] */
1296# define SYS_PF_NI2 (1 << 4) /* NI2/GPIO[24:28] */
1297# define SYS_PF_U0 (1 << 3) /* U0TXD/GPIO20 */
1298# define SYS_PF_RD (1 << 2) /* IRTXD/GPIO19 */
1299# define SYS_PF_A97 (1 << 1) /* AC97/SSL1 */
1300# define SYS_PF_S0 (1 << 0) /* SSI_0/GPIO[16:18] */
1301
1302/* Au1100 only */
1303# define SYS_PF_PC (1 << 18) /* PCMCIA/GPIO[207:204] */
1304# define SYS_PF_LCD (1 << 17) /* extern lcd/GPIO[203:200] */
1305# define SYS_PF_CS (1 << 16) /* EXTCLK0/32KHz to gpio2 */
1306# define SYS_PF_EX0 (1 << 9) /* GPIO2/clock */
1307
70342287 1308/* Au1550 only. Redefines lots of pins */
ff6814d5
SS		 1309# define SYS_PF_PSC2_MASK (7 << 17)
1310# define SYS_PF_PSC2_AC97 0
1311# define SYS_PF_PSC2_SPI 0
1312# define SYS_PF_PSC2_I2S (1 << 17)
1313# define SYS_PF_PSC2_SMBUS (3 << 17)
1314# define SYS_PF_PSC2_GPIO (7 << 17)
1315# define SYS_PF_PSC3_MASK (7 << 20)
1316# define SYS_PF_PSC3_AC97 0
1317# define SYS_PF_PSC3_SPI 0
1318# define SYS_PF_PSC3_I2S (1 << 20)
1319# define SYS_PF_PSC3_SMBUS (3 << 20)
1320# define SYS_PF_PSC3_GPIO (7 << 20)
1321# define SYS_PF_PSC1_S1 (1 << 1)
1322# define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
1323
1324/* Au1200 only */
70342287
RB		 1325#define SYS_PINFUNC_DMA (1 << 31)
1326#define SYS_PINFUNC_S0A (1 << 30)
1327#define SYS_PINFUNC_S1A (1 << 29)
1328#define SYS_PINFUNC_LP0 (1 << 28)
1329#define SYS_PINFUNC_LP1 (1 << 27)
1330#define SYS_PINFUNC_LD16 (1 << 26)
1331#define SYS_PINFUNC_LD8 (1 << 25)
1332#define SYS_PINFUNC_LD1 (1 << 24)
1333#define SYS_PINFUNC_LD0 (1 << 23)
1334#define SYS_PINFUNC_P1A (3 << 21)
1335#define SYS_PINFUNC_P1B (1 << 20)
1336#define SYS_PINFUNC_FS3 (1 << 19)
1337#define SYS_PINFUNC_P0A (3 << 17)
ff6814d5 1338#define SYS_PINFUNC_CS (1 << 16)
70342287
RB		 1339#define SYS_PINFUNC_CIM (1 << 15)
1340#define SYS_PINFUNC_P1C (1 << 14)
1341#define SYS_PINFUNC_U1T (1 << 12)
1342#define SYS_PINFUNC_U1R (1 << 11)
1343#define SYS_PINFUNC_EX1 (1 << 10)
1344#define SYS_PINFUNC_EX0 (1 << 9)
1345#define SYS_PINFUNC_U0R (1 << 8)
ff6814d5 1346#define SYS_PINFUNC_MC (1 << 7)
70342287
RB		 1347#define SYS_PINFUNC_S0B (1 << 6)
1348#define SYS_PINFUNC_S0C (1 << 5)
1349#define SYS_PINFUNC_P0B (1 << 4)
1350#define SYS_PINFUNC_U0T (1 << 3)
1351#define SYS_PINFUNC_S1B (1 << 2)
e3ad1c23 1352
1da177e4 1353/* Power Management */
ff6814d5
SS		 1354#define SYS_SCRATCH0 0xB1900018
1355#define SYS_SCRATCH1 0xB190001C
1356#define SYS_WAKEMSK 0xB1900034
1357#define SYS_ENDIAN 0xB1900038
1358#define SYS_POWERCTRL 0xB190003C
1359#define SYS_WAKESRC 0xB190005C
1360#define SYS_SLPPWR 0xB1900078
1361#define SYS_SLEEP 0xB190007C
1da177e4 1362
61f9c58d
ML		 1363#define SYS_WAKEMSK_D2 (1 << 9)
1364#define SYS_WAKEMSK_M2 (1 << 8)
1365#define SYS_WAKEMSK_GPIO(x) (1 << (x))
1366
1da177e4 1367/* Clock Controller */
ff6814d5
SS		 1368#define SYS_FREQCTRL0 0xB1900020
1369# define SYS_FC_FRDIV2_BIT 22
1370# define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT)
1371# define SYS_FC_FE2 (1 << 21)
1372# define SYS_FC_FS2 (1 << 20)
1373# define SYS_FC_FRDIV1_BIT 12
1374# define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT)
1375# define SYS_FC_FE1 (1 << 11)
1376# define SYS_FC_FS1 (1 << 10)
1377# define SYS_FC_FRDIV0_BIT 2
1378# define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT)
1379# define SYS_FC_FE0 (1 << 1)
1380# define SYS_FC_FS0 (1 << 0)
1381#define SYS_FREQCTRL1 0xB1900024
1382# define SYS_FC_FRDIV5_BIT 22
1383# define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT)
1384# define SYS_FC_FE5 (1 << 21)
1385# define SYS_FC_FS5 (1 << 20)
1386# define SYS_FC_FRDIV4_BIT 12
1387# define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT)
1388# define SYS_FC_FE4 (1 << 11)
1389# define SYS_FC_FS4 (1 << 10)
1390# define SYS_FC_FRDIV3_BIT 2
1391# define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT)
1392# define SYS_FC_FE3 (1 << 1)
1393# define SYS_FC_FS3 (1 << 0)
1394#define SYS_CLKSRC 0xB1900028
1395# define SYS_CS_ME1_BIT 27
1396# define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT)
1397# define SYS_CS_DE1 (1 << 26)
1398# define SYS_CS_CE1 (1 << 25)
1399# define SYS_CS_ME0_BIT 22
1400# define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT)
1401# define SYS_CS_DE0 (1 << 21)
1402# define SYS_CS_CE0 (1 << 20)
1403# define SYS_CS_MI2_BIT 17
1404# define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
1405# define SYS_CS_DI2 (1 << 16)
1406# define SYS_CS_CI2 (1 << 15)
37663860 1407
70342287 1408# define SYS_CS_ML_BIT 7
ff6814d5
SS		 1409# define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT)
1410# define SYS_CS_DL (1 << 6)
1411# define SYS_CS_CL (1 << 5)
37663860 1412
ff6814d5
SS		 1413# define SYS_CS_MUH_BIT 12
1414# define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
1415# define SYS_CS_DUH (1 << 11)
1416# define SYS_CS_CUH (1 << 10)
1417# define SYS_CS_MUD_BIT 7
1418# define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
1419# define SYS_CS_DUD (1 << 6)
1420# define SYS_CS_CUD (1 << 5)
37663860 1421
ff6814d5
SS		 1422# define SYS_CS_MIR_BIT 2
1423# define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
1424# define SYS_CS_DIR (1 << 1)
1425# define SYS_CS_CIR (1 << 0)
1426
1427# define SYS_CS_MUX_AUX 0x1
1428# define SYS_CS_MUX_FQ0 0x2
1429# define SYS_CS_MUX_FQ1 0x3
1430# define SYS_CS_MUX_FQ2 0x4
1431# define SYS_CS_MUX_FQ3 0x5
1432# define SYS_CS_MUX_FQ4 0x6
1433# define SYS_CS_MUX_FQ5 0x7
1434#define SYS_CPUPLL 0xB1900060
1435#define SYS_AUXPLL 0xB1900064
1da177e4
LT		 1436
1437/* AC97 Controller */
ff6814d5
SS		 1438#define AC97C_CONFIG 0xB0000000
1439# define AC97C_RECV_SLOTS_BIT 13
49a89efb 1440# define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
ff6814d5 1441# define AC97C_XMIT_SLOTS_BIT 3
49a89efb 1442# define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
ff6814d5
SS		 1443# define AC97C_SG (1 << 2)
1444# define AC97C_SYNC (1 << 1)
1445# define AC97C_RESET (1 << 0)
1446#define AC97C_STATUS 0xB0000004
1447# define AC97C_XU (1 << 11)
1448# define AC97C_XO (1 << 10)
1449# define AC97C_RU (1 << 9)
1450# define AC97C_RO (1 << 8)
1451# define AC97C_READY (1 << 7)
1452# define AC97C_CP (1 << 6)
1453# define AC97C_TR (1 << 5)
1454# define AC97C_TE (1 << 4)
1455# define AC97C_TF (1 << 3)
1456# define AC97C_RR (1 << 2)
1457# define AC97C_RE (1 << 1)
1458# define AC97C_RF (1 << 0)
1459#define AC97C_DATA 0xB0000008
1460#define AC97C_CMD 0xB000000C
1461# define AC97C_WD_BIT 16
1462# define AC97C_READ (1 << 7)
1463# define AC97C_INDEX_MASK 0x7f
1464#define AC97C_CNTRL 0xB0000010
1465# define AC97C_RS (1 << 1)
1466# define AC97C_CE (1 << 0)
1da177e4 1467
1da177e4 1468
7517de34
ML		 1469/* The PCI chip selects are outside the 32bit space, and since we can't
1470 * just program the 36bit addresses into BARs, we have to take a chunk
1471 * out of the 32bit space and reserve it for PCI. When these addresses
1472 * are ioremap()ed, they'll be fixed up to the real 36bit address before
1473 * being passed to the real ioremap function.
1da177e4 1474 */
7517de34
ML		 1475#define ALCHEMY_PCI_MEMWIN_START (AU1500_PCI_MEM_PHYS_ADDR >> 4)
1476#define ALCHEMY_PCI_MEMWIN_END (ALCHEMY_PCI_MEMWIN_START + 0x0FFFFFFF)
1da177e4 1477
7517de34
ML		 1478/* for PCI IO it's simpler because we get to do the ioremap ourselves and then
1479 * adjust the device's resources.
1480 */
1481#define ALCHEMY_PCI_IOWIN_START 0x00001000
1482#define ALCHEMY_PCI_IOWIN_END 0x0000FFFF
dd99d966 1483
7517de34 1484#ifdef CONFIG_PCI
1da177e4 1485
ff6814d5
SS		 1486#define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
1487#define IOPORT_RESOURCE_END 0xffffffff
1488#define IOMEM_RESOURCE_START 0x10000000
60ec6571 1489#define IOMEM_RESOURCE_END 0xfffffffffULL
1da177e4 1490
7517de34 1491#else
1da177e4 1492
ff6814d5
SS		 1493/* Don't allow any legacy ports probing */
1494#define IOPORT_RESOURCE_START 0x10000000
1495#define IOPORT_RESOURCE_END 0xffffffff
1496#define IOMEM_RESOURCE_START 0x10000000
60ec6571 1497#define IOMEM_RESOURCE_END 0xfffffffffULL
1da177e4 1498
1da177e4
LT		 1499#endif
1500
7517de34
ML		 1501/* PCI controller block register offsets */
1502#define PCI_REG_CMEM 0x0000
1503#define PCI_REG_CONFIG 0x0004
1504#define PCI_REG_B2BMASK_CCH 0x0008
1505#define PCI_REG_B2BBASE0_VID 0x000C
1506#define PCI_REG_B2BBASE1_SID 0x0010
1507#define PCI_REG_MWMASK_DEV 0x0014
1508#define PCI_REG_MWBASE_REV_CCL 0x0018
1509#define PCI_REG_ERR_ADDR 0x001C
1510#define PCI_REG_SPEC_INTACK 0x0020
1511#define PCI_REG_ID 0x0100
1512#define PCI_REG_STATCMD 0x0104
1513#define PCI_REG_CLASSREV 0x0108
1514#define PCI_REG_PARAM 0x010C
1515#define PCI_REG_MBAR 0x0110
1516#define PCI_REG_TIMEOUT 0x0140
1517
1518/* PCI controller block register bits */
1519#define PCI_CMEM_E (1 << 28) /* enable cacheable memory */
1520#define PCI_CMEM_CMBASE(x) (((x) & 0x3fff) << 14)
1521#define PCI_CMEM_CMMASK(x) ((x) & 0x3fff)
1522#define PCI_CONFIG_ERD (1 << 27) /* pci error during R/W */
1523#define PCI_CONFIG_ET (1 << 26) /* error in target mode */
1524#define PCI_CONFIG_EF (1 << 25) /* fatal error */
1525#define PCI_CONFIG_EP (1 << 24) /* parity error */
1526#define PCI_CONFIG_EM (1 << 23) /* multiple errors */
1527#define PCI_CONFIG_BM (1 << 22) /* bad master error */
1528#define PCI_CONFIG_PD (1 << 20) /* PCI Disable */
1529#define PCI_CONFIG_BME (1 << 19) /* Byte Mask Enable for reads */
1530#define PCI_CONFIG_NC (1 << 16) /* mark mem access non-coherent */
1531#define PCI_CONFIG_IA (1 << 15) /* INTA# enabled (target mode) */
1532#define PCI_CONFIG_IP (1 << 13) /* int on PCI_PERR# */
1533#define PCI_CONFIG_IS (1 << 12) /* int on PCI_SERR# */
1534#define PCI_CONFIG_IMM (1 << 11) /* int on master abort */
1535#define PCI_CONFIG_ITM (1 << 10) /* int on target abort (as master) */
1536#define PCI_CONFIG_ITT (1 << 9) /* int on target abort (as target) */
1537#define PCI_CONFIG_IPB (1 << 8) /* int on PERR# in bus master acc */
1538#define PCI_CONFIG_SIC_NO (0 << 6) /* no byte mask changes */
1539#define PCI_CONFIG_SIC_BA_ADR (1 << 6) /* on byte/hw acc, invert adr bits */
1540#define PCI_CONFIG_SIC_HWA_DAT (2 << 6) /* on halfword acc, swap data */
1541#define PCI_CONFIG_SIC_ALL (3 << 6) /* swap data bytes on all accesses */
1542#define PCI_CONFIG_ST (1 << 5) /* swap data by target transactions */
1543#define PCI_CONFIG_SM (1 << 4) /* swap data from PCI ctl */
1544#define PCI_CONFIG_AEN (1 << 3) /* enable internal arbiter */
1545#define PCI_CONFIG_R2H (1 << 2) /* REQ2# to hi-prio arbiter */
1546#define PCI_CONFIG_R1H (1 << 1) /* REQ1# to hi-prio arbiter */
1547#define PCI_CONFIG_CH (1 << 0) /* PCI ctl to hi-prio arbiter */
1548#define PCI_B2BMASK_B2BMASK(x) (((x) & 0xffff) << 16)
1549#define PCI_B2BMASK_CCH(x) ((x) & 0xffff) /* 16 upper bits of class code */
1550#define PCI_B2BBASE0_VID_B0(x) (((x) & 0xffff) << 16)
1551#define PCI_B2BBASE0_VID_SV(x) ((x) & 0xffff)
1552#define PCI_B2BBASE1_SID_B1(x) (((x) & 0xffff) << 16)
1553#define PCI_B2BBASE1_SID_SI(x) ((x) & 0xffff)
1554#define PCI_MWMASKDEV_MWMASK(x) (((x) & 0xffff) << 16)
1555#define PCI_MWMASKDEV_DEVID(x) ((x) & 0xffff)
1556#define PCI_MWBASEREVCCL_BASE(x) (((x) & 0xffff) << 16)
70342287
RB		 1557#define PCI_MWBASEREVCCL_REV(x) (((x) & 0xff) << 8)
1558#define PCI_MWBASEREVCCL_CCL(x) ((x) & 0xff)
7517de34
ML		 1559#define PCI_ID_DID(x) (((x) & 0xffff) << 16)
1560#define PCI_ID_VID(x) ((x) & 0xffff)
1561#define PCI_STATCMD_STATUS(x) (((x) & 0xffff) << 16)
1562#define PCI_STATCMD_CMD(x) ((x) & 0xffff)
1563#define PCI_CLASSREV_CLASS(x) (((x) & 0x00ffffff) << 8)
1564#define PCI_CLASSREV_REV(x) ((x) & 0xff)
1565#define PCI_PARAM_BIST(x) (((x) & 0xff) << 24)
1566#define PCI_PARAM_HT(x) (((x) & 0xff) << 16)
1567#define PCI_PARAM_LT(x) (((x) & 0xff) << 8)
1568#define PCI_PARAM_CLS(x) ((x) & 0xff)
1569#define PCI_TIMEOUT_RETRIES(x) (((x) & 0xff) << 8) /* max retries */
1570#define PCI_TIMEOUT_TO(x) ((x) & 0xff) /* target ready timeout */
1571
e3ad1c23 1572#endif
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