projects / mirror_ubuntu-bionic-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| e7300d04 MB |
1 | #ifndef BCM63XX_CPU_H_ |
| 2 | #define BCM63XX_CPU_H_ | |
| 3 | ||
| 4 | #include <linux/types.h> | |
| 5 | #include <linux/init.h> | |
| 6 | ||
| 7 | /* | |
| 8 | * Macro to fetch bcm63xx cpu id and revision, should be optimized at | |
| 9 | * compile time if only one CPU support is enabled (idea stolen from | |
| 10 | * arm mach-types) | |
| 11 | */ | |
| 12 | #define BCM6338_CPU_ID 0x6338 | |
| 13 | #define BCM6345_CPU_ID 0x6345 | |
| 14 | #define BCM6348_CPU_ID 0x6348 | |
| 15 | #define BCM6358_CPU_ID 0x6358 | |
| 04712f3f | 16 | #define BCM6368_CPU_ID 0x6368 |
| e7300d04 MB |
17 | |
| 18 | void __init bcm63xx_cpu_init(void); | |
| 19 | u16 __bcm63xx_get_cpu_id(void); | |
| 20 | u16 bcm63xx_get_cpu_rev(void); | |
| 21 | unsigned int bcm63xx_get_cpu_freq(void); | |
| 22 | ||
| 23 | #ifdef CONFIG_BCM63XX_CPU_6338 | |
| 24 | # ifdef bcm63xx_get_cpu_id | |
| 25 | # undef bcm63xx_get_cpu_id | |
| 26 | # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() | |
| 27 | # define BCMCPU_RUNTIME_DETECT | |
| 28 | # else | |
| 29 | # define bcm63xx_get_cpu_id() BCM6338_CPU_ID | |
| 30 | # endif | |
| 31 | # define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID) | |
| 32 | #else | |
| 33 | # define BCMCPU_IS_6338() (0) | |
| 34 | #endif | |
| 35 | ||
| 36 | #ifdef CONFIG_BCM63XX_CPU_6345 | |
| 37 | # ifdef bcm63xx_get_cpu_id | |
| 38 | # undef bcm63xx_get_cpu_id | |
| 39 | # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() | |
| 40 | # define BCMCPU_RUNTIME_DETECT | |
| 41 | # else | |
| 42 | # define bcm63xx_get_cpu_id() BCM6345_CPU_ID | |
| 43 | # endif | |
| 44 | # define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID) | |
| 45 | #else | |
| 46 | # define BCMCPU_IS_6345() (0) | |
| 47 | #endif | |
| 48 | ||
| 49 | #ifdef CONFIG_BCM63XX_CPU_6348 | |
| 50 | # ifdef bcm63xx_get_cpu_id | |
| 51 | # undef bcm63xx_get_cpu_id | |
| 52 | # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() | |
| 53 | # define BCMCPU_RUNTIME_DETECT | |
| 54 | # else | |
| 55 | # define bcm63xx_get_cpu_id() BCM6348_CPU_ID | |
| 56 | # endif | |
| 57 | # define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID) | |
| 58 | #else | |
| 59 | # define BCMCPU_IS_6348() (0) | |
| 60 | #endif | |
| 61 | ||
| 62 | #ifdef CONFIG_BCM63XX_CPU_6358 | |
| 63 | # ifdef bcm63xx_get_cpu_id | |
| 64 | # undef bcm63xx_get_cpu_id | |
| 65 | # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() | |
| 66 | # define BCMCPU_RUNTIME_DETECT | |
| 67 | # else | |
| 68 | # define bcm63xx_get_cpu_id() BCM6358_CPU_ID | |
| 69 | # endif | |
| 70 | # define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID) | |
| 71 | #else | |
| 72 | # define BCMCPU_IS_6358() (0) | |
| 73 | #endif | |
| 74 | ||
| 04712f3f MB |
75 | #ifdef CONFIG_BCM63XX_CPU_6368 |
| 76 | # ifdef bcm63xx_get_cpu_id | |
| 77 | # undef bcm63xx_get_cpu_id | |
| 78 | # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() | |
| 79 | # define BCMCPU_RUNTIME_DETECT | |
| 80 | # else | |
| 81 | # define bcm63xx_get_cpu_id() BCM6368_CPU_ID | |
| 82 | # endif | |
| 83 | # define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID) | |
| 84 | #else | |
| 85 | # define BCMCPU_IS_6368() (0) | |
| 86 | #endif | |
| 87 | ||
| e7300d04 MB |
88 | #ifndef bcm63xx_get_cpu_id |
| 89 | #error "No CPU support configured" | |
| 90 | #endif | |
| 91 | ||
| 92 | /* | |
| 93 | * While registers sets are (mostly) the same across 63xx CPU, base | |
| 94 | * address of these sets do change. | |
| 95 | */ | |
| 96 | enum bcm63xx_regs_set { | |
| 97 | RSET_DSL_LMEM = 0, | |
| 98 | RSET_PERF, | |
| 99 | RSET_TIMER, | |
| 100 | RSET_WDT, | |
| 101 | RSET_UART0, | |
| 524ef29c | 102 | RSET_UART1, |
| e7300d04 MB |
103 | RSET_GPIO, |
| 104 | RSET_SPI, | |
| d430b6c5 | 105 | RSET_SPI2, |
| e7300d04 MB |
106 | RSET_UDC0, |
| 107 | RSET_OHCI0, | |
| 108 | RSET_OHCI_PRIV, | |
| 109 | RSET_USBH_PRIV, | |
| 110 | RSET_MPI, | |
| 111 | RSET_PCMCIA, | |
| 112 | RSET_DSL, | |
| 113 | RSET_ENET0, | |
| 114 | RSET_ENET1, | |
| 115 | RSET_ENETDMA, | |
| d430b6c5 MB |
116 | RSET_ENETDMAC, |
| 117 | RSET_ENETDMAS, | |
| 118 | RSET_ENETSW, | |
| e7300d04 MB |
119 | RSET_EHCI0, |
| 120 | RSET_SDRAM, | |
| 121 | RSET_MEMC, | |
| 122 | RSET_DDR, | |
| d430b6c5 MB |
123 | RSET_M2M, |
| 124 | RSET_ATM, | |
| 125 | RSET_XTM, | |
| 126 | RSET_XTMDMA, | |
| 127 | RSET_XTMDMAC, | |
| 128 | RSET_XTMDMAS, | |
| 129 | RSET_PCM, | |
| 130 | RSET_PCMDMA, | |
| 131 | RSET_PCMDMAC, | |
| 132 | RSET_PCMDMAS, | |
| e7300d04 MB |
133 | }; |
| 134 | ||
| 135 | #define RSET_DSL_LMEM_SIZE (64 * 1024 * 4) | |
| 136 | #define RSET_DSL_SIZE 4096 | |
| 137 | #define RSET_WDT_SIZE 12 | |
| 7546d71a FF |
138 | #define BCM_6338_RSET_SPI_SIZE 64 |
| 139 | #define BCM_6348_RSET_SPI_SIZE 64 | |
| 140 | #define BCM_6358_RSET_SPI_SIZE 1804 | |
| 141 | #define BCM_6368_RSET_SPI_SIZE 1804 | |
| e7300d04 MB |
142 | #define RSET_ENET_SIZE 2048 |
| 143 | #define RSET_ENETDMA_SIZE 2048 | |
| d430b6c5 | 144 | #define RSET_ENETSW_SIZE 65536 |
| e7300d04 MB |
145 | #define RSET_UART_SIZE 24 |
| 146 | #define RSET_UDC_SIZE 256 | |
| 147 | #define RSET_OHCI_SIZE 256 | |
| 148 | #define RSET_EHCI_SIZE 256 | |
| 149 | #define RSET_PCMCIA_SIZE 12 | |
| d430b6c5 MB |
150 | #define RSET_M2M_SIZE 256 |
| 151 | #define RSET_ATM_SIZE 4096 | |
| 152 | #define RSET_XTM_SIZE 10240 | |
| 153 | #define RSET_XTMDMA_SIZE 256 | |
| 154 | #define RSET_XTMDMAC_SIZE(chans) (16 * (chans)) | |
| 155 | #define RSET_XTMDMAS_SIZE(chans) (16 * (chans)) | |
| e7300d04 MB |
156 | |
| 157 | /* | |
| 158 | * 6338 register sets base address | |
| 159 | */ | |
| 160 | #define BCM_6338_DSL_LMEM_BASE (0xfff00000) | |
| 161 | #define BCM_6338_PERF_BASE (0xfffe0000) | |
| 162 | #define BCM_6338_BB_BASE (0xfffe0100) | |
| 163 | #define BCM_6338_TIMER_BASE (0xfffe0200) | |
| 164 | #define BCM_6338_WDT_BASE (0xfffe021c) | |
| 165 | #define BCM_6338_UART0_BASE (0xfffe0300) | |
| 524ef29c | 166 | #define BCM_6338_UART1_BASE (0xdeadbeef) |
| e7300d04 MB |
167 | #define BCM_6338_GPIO_BASE (0xfffe0400) |
| 168 | #define BCM_6338_SPI_BASE (0xfffe0c00) | |
| d430b6c5 | 169 | #define BCM_6338_SPI2_BASE (0xdeadbeef) |
| e7300d04 MB |
170 | #define BCM_6338_UDC0_BASE (0xdeadbeef) |
| 171 | #define BCM_6338_USBDMA_BASE (0xfffe2400) | |
| 172 | #define BCM_6338_OHCI0_BASE (0xdeadbeef) | |
| 173 | #define BCM_6338_OHCI_PRIV_BASE (0xfffe3000) | |
| 174 | #define BCM_6338_USBH_PRIV_BASE (0xdeadbeef) | |
| 175 | #define BCM_6338_MPI_BASE (0xfffe3160) | |
| 176 | #define BCM_6338_PCMCIA_BASE (0xdeadbeef) | |
| 177 | #define BCM_6338_SDRAM_REGS_BASE (0xfffe3100) | |
| 178 | #define BCM_6338_DSL_BASE (0xfffe1000) | |
| e7300d04 MB |
179 | #define BCM_6338_UBUS_BASE (0xdeadbeef) |
| 180 | #define BCM_6338_ENET0_BASE (0xfffe2800) | |
| 181 | #define BCM_6338_ENET1_BASE (0xdeadbeef) | |
| 182 | #define BCM_6338_ENETDMA_BASE (0xfffe2400) | |
| d430b6c5 MB |
183 | #define BCM_6338_ENETDMAC_BASE (0xfffe2500) |
| 184 | #define BCM_6338_ENETDMAS_BASE (0xfffe2600) | |
| 185 | #define BCM_6338_ENETSW_BASE (0xdeadbeef) | |
| e7300d04 MB |
186 | #define BCM_6338_EHCI0_BASE (0xdeadbeef) |
| 187 | #define BCM_6338_SDRAM_BASE (0xfffe3100) | |
| 188 | #define BCM_6338_MEMC_BASE (0xdeadbeef) | |
| 189 | #define BCM_6338_DDR_BASE (0xdeadbeef) | |
| d430b6c5 MB |
190 | #define BCM_6338_M2M_BASE (0xdeadbeef) |
| 191 | #define BCM_6338_ATM_BASE (0xfffe2000) | |
| 192 | #define BCM_6338_XTM_BASE (0xdeadbeef) | |
| 193 | #define BCM_6338_XTMDMA_BASE (0xdeadbeef) | |
| 194 | #define BCM_6338_XTMDMAC_BASE (0xdeadbeef) | |
| 195 | #define BCM_6338_XTMDMAS_BASE (0xdeadbeef) | |
| 196 | #define BCM_6338_PCM_BASE (0xdeadbeef) | |
| 197 | #define BCM_6338_PCMDMA_BASE (0xdeadbeef) | |
| 198 | #define BCM_6338_PCMDMAC_BASE (0xdeadbeef) | |
| 199 | #define BCM_6338_PCMDMAS_BASE (0xdeadbeef) | |
| e7300d04 MB |
200 | |
| 201 | /* | |
| 202 | * 6345 register sets base address | |
| 203 | */ | |
| 204 | #define BCM_6345_DSL_LMEM_BASE (0xfff00000) | |
| 205 | #define BCM_6345_PERF_BASE (0xfffe0000) | |
| 206 | #define BCM_6345_BB_BASE (0xfffe0100) | |
| 207 | #define BCM_6345_TIMER_BASE (0xfffe0200) | |
| 208 | #define BCM_6345_WDT_BASE (0xfffe021c) | |
| 209 | #define BCM_6345_UART0_BASE (0xfffe0300) | |
| 524ef29c | 210 | #define BCM_6345_UART1_BASE (0xdeadbeef) |
| e7300d04 MB |
211 | #define BCM_6345_GPIO_BASE (0xfffe0400) |
| 212 | #define BCM_6345_SPI_BASE (0xdeadbeef) | |
| d430b6c5 | 213 | #define BCM_6345_SPI2_BASE (0xdeadbeef) |
| e7300d04 MB |
214 | #define BCM_6345_UDC0_BASE (0xdeadbeef) |
| 215 | #define BCM_6345_USBDMA_BASE (0xfffe2800) | |
| 216 | #define BCM_6345_ENET0_BASE (0xfffe1800) | |
| 217 | #define BCM_6345_ENETDMA_BASE (0xfffe2800) | |
| d430b6c5 MB |
218 | #define BCM_6345_ENETDMAC_BASE (0xfffe2900) |
| 219 | #define BCM_6345_ENETDMAS_BASE (0xfffe2a00) | |
| 220 | #define BCM_6345_ENETSW_BASE (0xdeadbeef) | |
| e7300d04 | 221 | #define BCM_6345_PCMCIA_BASE (0xfffe2028) |
| e1c96c86 | 222 | #define BCM_6345_MPI_BASE (0xfffe2000) |
| e7300d04 MB |
223 | #define BCM_6345_OHCI0_BASE (0xfffe2100) |
| 224 | #define BCM_6345_OHCI_PRIV_BASE (0xfffe2200) | |
| 225 | #define BCM_6345_USBH_PRIV_BASE (0xdeadbeef) | |
| 226 | #define BCM_6345_SDRAM_REGS_BASE (0xfffe2300) | |
| 227 | #define BCM_6345_DSL_BASE (0xdeadbeef) | |
| e7300d04 MB |
228 | #define BCM_6345_UBUS_BASE (0xdeadbeef) |
| 229 | #define BCM_6345_ENET1_BASE (0xdeadbeef) | |
| 230 | #define BCM_6345_EHCI0_BASE (0xdeadbeef) | |
| 231 | #define BCM_6345_SDRAM_BASE (0xfffe2300) | |
| 232 | #define BCM_6345_MEMC_BASE (0xdeadbeef) | |
| 233 | #define BCM_6345_DDR_BASE (0xdeadbeef) | |
| d430b6c5 MB |
234 | #define BCM_6345_M2M_BASE (0xdeadbeef) |
| 235 | #define BCM_6345_ATM_BASE (0xfffe4000) | |
| 236 | #define BCM_6345_XTM_BASE (0xdeadbeef) | |
| 237 | #define BCM_6345_XTMDMA_BASE (0xdeadbeef) | |
| 238 | #define BCM_6345_XTMDMAC_BASE (0xdeadbeef) | |
| 239 | #define BCM_6345_XTMDMAS_BASE (0xdeadbeef) | |
| 240 | #define BCM_6345_PCM_BASE (0xdeadbeef) | |
| 241 | #define BCM_6345_PCMDMA_BASE (0xdeadbeef) | |
| 242 | #define BCM_6345_PCMDMAC_BASE (0xdeadbeef) | |
| 243 | #define BCM_6345_PCMDMAS_BASE (0xdeadbeef) | |
| e7300d04 MB |
244 | |
| 245 | /* | |
| 246 | * 6348 register sets base address | |
| 247 | */ | |
| 248 | #define BCM_6348_DSL_LMEM_BASE (0xfff00000) | |
| 249 | #define BCM_6348_PERF_BASE (0xfffe0000) | |
| 250 | #define BCM_6348_TIMER_BASE (0xfffe0200) | |
| 251 | #define BCM_6348_WDT_BASE (0xfffe021c) | |
| 252 | #define BCM_6348_UART0_BASE (0xfffe0300) | |
| 524ef29c | 253 | #define BCM_6348_UART1_BASE (0xdeadbeef) |
| e7300d04 MB |
254 | #define BCM_6348_GPIO_BASE (0xfffe0400) |
| 255 | #define BCM_6348_SPI_BASE (0xfffe0c00) | |
| d430b6c5 | 256 | #define BCM_6348_SPI2_BASE (0xdeadbeef) |
| e7300d04 MB |
257 | #define BCM_6348_UDC0_BASE (0xfffe1000) |
| 258 | #define BCM_6348_OHCI0_BASE (0xfffe1b00) | |
| 259 | #define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00) | |
| 260 | #define BCM_6348_USBH_PRIV_BASE (0xdeadbeef) | |
| 261 | #define BCM_6348_MPI_BASE (0xfffe2000) | |
| 262 | #define BCM_6348_PCMCIA_BASE (0xfffe2054) | |
| 263 | #define BCM_6348_SDRAM_REGS_BASE (0xfffe2300) | |
| d430b6c5 | 264 | #define BCM_6348_M2M_BASE (0xfffe2800) |
| e7300d04 MB |
265 | #define BCM_6348_DSL_BASE (0xfffe3000) |
| 266 | #define BCM_6348_ENET0_BASE (0xfffe6000) | |
| 267 | #define BCM_6348_ENET1_BASE (0xfffe6800) | |
| 268 | #define BCM_6348_ENETDMA_BASE (0xfffe7000) | |
| d430b6c5 MB |
269 | #define BCM_6348_ENETDMAC_BASE (0xfffe7100) |
| 270 | #define BCM_6348_ENETDMAS_BASE (0xfffe7200) | |
| 271 | #define BCM_6348_ENETSW_BASE (0xdeadbeef) | |
| e7300d04 MB |
272 | #define BCM_6348_EHCI0_BASE (0xdeadbeef) |
| 273 | #define BCM_6348_SDRAM_BASE (0xfffe2300) | |
| 274 | #define BCM_6348_MEMC_BASE (0xdeadbeef) | |
| 275 | #define BCM_6348_DDR_BASE (0xdeadbeef) | |
| d430b6c5 MB |
276 | #define BCM_6348_ATM_BASE (0xfffe4000) |
| 277 | #define BCM_6348_XTM_BASE (0xdeadbeef) | |
| 278 | #define BCM_6348_XTMDMA_BASE (0xdeadbeef) | |
| 279 | #define BCM_6348_XTMDMAC_BASE (0xdeadbeef) | |
| 280 | #define BCM_6348_XTMDMAS_BASE (0xdeadbeef) | |
| 281 | #define BCM_6348_PCM_BASE (0xdeadbeef) | |
| 282 | #define BCM_6348_PCMDMA_BASE (0xdeadbeef) | |
| 283 | #define BCM_6348_PCMDMAC_BASE (0xdeadbeef) | |
| 284 | #define BCM_6348_PCMDMAS_BASE (0xdeadbeef) | |
| e7300d04 MB |
285 | |
| 286 | /* | |
| 287 | * 6358 register sets base address | |
| 288 | */ | |
| 289 | #define BCM_6358_DSL_LMEM_BASE (0xfff00000) | |
| 290 | #define BCM_6358_PERF_BASE (0xfffe0000) | |
| 291 | #define BCM_6358_TIMER_BASE (0xfffe0040) | |
| 292 | #define BCM_6358_WDT_BASE (0xfffe005c) | |
| 293 | #define BCM_6358_UART0_BASE (0xfffe0100) | |
| 524ef29c | 294 | #define BCM_6358_UART1_BASE (0xfffe0120) |
| e7300d04 | 295 | #define BCM_6358_GPIO_BASE (0xfffe0080) |
| 9e368e49 | 296 | #define BCM_6358_SPI_BASE (0xfffe0800) |
| d430b6c5 | 297 | #define BCM_6358_SPI2_BASE (0xfffe0800) |
| e7300d04 MB |
298 | #define BCM_6358_UDC0_BASE (0xfffe0800) |
| 299 | #define BCM_6358_OHCI0_BASE (0xfffe1400) | |
| 300 | #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef) | |
| 301 | #define BCM_6358_USBH_PRIV_BASE (0xfffe1500) | |
| 302 | #define BCM_6358_MPI_BASE (0xfffe1000) | |
| 303 | #define BCM_6358_PCMCIA_BASE (0xfffe1054) | |
| 304 | #define BCM_6358_SDRAM_REGS_BASE (0xfffe2300) | |
| d430b6c5 | 305 | #define BCM_6358_M2M_BASE (0xdeadbeef) |
| e7300d04 MB |
306 | #define BCM_6358_DSL_BASE (0xfffe3000) |
| 307 | #define BCM_6358_ENET0_BASE (0xfffe4000) | |
| 308 | #define BCM_6358_ENET1_BASE (0xfffe4800) | |
| 309 | #define BCM_6358_ENETDMA_BASE (0xfffe5000) | |
| d430b6c5 MB |
310 | #define BCM_6358_ENETDMAC_BASE (0xfffe5100) |
| 311 | #define BCM_6358_ENETDMAS_BASE (0xfffe5200) | |
| 312 | #define BCM_6358_ENETSW_BASE (0xdeadbeef) | |
| e7300d04 MB |
313 | #define BCM_6358_EHCI0_BASE (0xfffe1300) |
| 314 | #define BCM_6358_SDRAM_BASE (0xdeadbeef) | |
| 315 | #define BCM_6358_MEMC_BASE (0xfffe1200) | |
| 316 | #define BCM_6358_DDR_BASE (0xfffe12a0) | |
| d430b6c5 MB |
317 | #define BCM_6358_ATM_BASE (0xfffe2000) |
| 318 | #define BCM_6358_XTM_BASE (0xdeadbeef) | |
| 319 | #define BCM_6358_XTMDMA_BASE (0xdeadbeef) | |
| 320 | #define BCM_6358_XTMDMAC_BASE (0xdeadbeef) | |
| 321 | #define BCM_6358_XTMDMAS_BASE (0xdeadbeef) | |
| 322 | #define BCM_6358_PCM_BASE (0xfffe1600) | |
| 323 | #define BCM_6358_PCMDMA_BASE (0xfffe1800) | |
| 324 | #define BCM_6358_PCMDMAC_BASE (0xfffe1900) | |
| 325 | #define BCM_6358_PCMDMAS_BASE (0xfffe1a00) | |
| 326 | ||
| e7300d04 | 327 | |
| 04712f3f MB |
328 | /* |
| 329 | * 6368 register sets base address | |
| 330 | */ | |
| 331 | #define BCM_6368_DSL_LMEM_BASE (0xdeadbeef) | |
| 332 | #define BCM_6368_PERF_BASE (0xb0000000) | |
| 333 | #define BCM_6368_TIMER_BASE (0xb0000040) | |
| 334 | #define BCM_6368_WDT_BASE (0xb000005c) | |
| 335 | #define BCM_6368_UART0_BASE (0xb0000100) | |
| 336 | #define BCM_6368_UART1_BASE (0xb0000120) | |
| 337 | #define BCM_6368_GPIO_BASE (0xb0000080) | |
| 338 | #define BCM_6368_SPI_BASE (0xdeadbeef) | |
| 339 | #define BCM_6368_SPI2_BASE (0xb0000800) | |
| 340 | #define BCM_6368_UDC0_BASE (0xdeadbeef) | |
| 341 | #define BCM_6368_OHCI0_BASE (0xb0001600) | |
| 342 | #define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef) | |
| 343 | #define BCM_6368_USBH_PRIV_BASE (0xb0001700) | |
| 344 | #define BCM_6368_MPI_BASE (0xb0001000) | |
| 345 | #define BCM_6368_PCMCIA_BASE (0xb0001054) | |
| 346 | #define BCM_6368_SDRAM_REGS_BASE (0xdeadbeef) | |
| 347 | #define BCM_6368_M2M_BASE (0xdeadbeef) | |
| 348 | #define BCM_6368_DSL_BASE (0xdeadbeef) | |
| 349 | #define BCM_6368_ENET0_BASE (0xdeadbeef) | |
| 350 | #define BCM_6368_ENET1_BASE (0xdeadbeef) | |
| 351 | #define BCM_6368_ENETDMA_BASE (0xb0006800) | |
| 352 | #define BCM_6368_ENETDMAC_BASE (0xb0006a00) | |
| 353 | #define BCM_6368_ENETDMAS_BASE (0xb0006c00) | |
| 354 | #define BCM_6368_ENETSW_BASE (0xb0f00000) | |
| 355 | #define BCM_6368_EHCI0_BASE (0xb0001500) | |
| 356 | #define BCM_6368_SDRAM_BASE (0xdeadbeef) | |
| 357 | #define BCM_6368_MEMC_BASE (0xb0001200) | |
| 358 | #define BCM_6368_DDR_BASE (0xb0001280) | |
| 359 | #define BCM_6368_ATM_BASE (0xdeadbeef) | |
| 360 | #define BCM_6368_XTM_BASE (0xb0001800) | |
| 361 | #define BCM_6368_XTMDMA_BASE (0xb0005000) | |
| 362 | #define BCM_6368_XTMDMAC_BASE (0xb0005200) | |
| 363 | #define BCM_6368_XTMDMAS_BASE (0xb0005400) | |
| 364 | #define BCM_6368_PCM_BASE (0xb0004000) | |
| 365 | #define BCM_6368_PCMDMA_BASE (0xb0005800) | |
| 366 | #define BCM_6368_PCMDMAC_BASE (0xb0005a00) | |
| 367 | #define BCM_6368_PCMDMAS_BASE (0xb0005c00) | |
| 368 | ||
| e7300d04 MB |
369 | |
| 370 | extern const unsigned long *bcm63xx_regs_base; | |
| 371 | ||
| ec68c520 MB |
372 | #define __GEN_RSET_BASE(__cpu, __rset) \ |
| 373 | case RSET_## __rset : \ | |
| 374 | return BCM_## __cpu ##_## __rset ##_BASE; | |
| 375 | ||
| 376 | #define __GEN_RSET(__cpu) \ | |
| 377 | switch (set) { \ | |
| 378 | __GEN_RSET_BASE(__cpu, DSL_LMEM) \ | |
| 379 | __GEN_RSET_BASE(__cpu, PERF) \ | |
| 380 | __GEN_RSET_BASE(__cpu, TIMER) \ | |
| 381 | __GEN_RSET_BASE(__cpu, WDT) \ | |
| 382 | __GEN_RSET_BASE(__cpu, UART0) \ | |
| 383 | __GEN_RSET_BASE(__cpu, UART1) \ | |
| 384 | __GEN_RSET_BASE(__cpu, GPIO) \ | |
| 385 | __GEN_RSET_BASE(__cpu, SPI) \ | |
| d430b6c5 | 386 | __GEN_RSET_BASE(__cpu, SPI2) \ |
| ec68c520 MB |
387 | __GEN_RSET_BASE(__cpu, UDC0) \ |
| 388 | __GEN_RSET_BASE(__cpu, OHCI0) \ | |
| 389 | __GEN_RSET_BASE(__cpu, OHCI_PRIV) \ | |
| 390 | __GEN_RSET_BASE(__cpu, USBH_PRIV) \ | |
| 391 | __GEN_RSET_BASE(__cpu, MPI) \ | |
| 392 | __GEN_RSET_BASE(__cpu, PCMCIA) \ | |
| 393 | __GEN_RSET_BASE(__cpu, DSL) \ | |
| 394 | __GEN_RSET_BASE(__cpu, ENET0) \ | |
| 395 | __GEN_RSET_BASE(__cpu, ENET1) \ | |
| 396 | __GEN_RSET_BASE(__cpu, ENETDMA) \ | |
| d430b6c5 MB |
397 | __GEN_RSET_BASE(__cpu, ENETDMAC) \ |
| 398 | __GEN_RSET_BASE(__cpu, ENETDMAS) \ | |
| 399 | __GEN_RSET_BASE(__cpu, ENETSW) \ | |
| ec68c520 MB |
400 | __GEN_RSET_BASE(__cpu, EHCI0) \ |
| 401 | __GEN_RSET_BASE(__cpu, SDRAM) \ | |
| 402 | __GEN_RSET_BASE(__cpu, MEMC) \ | |
| 403 | __GEN_RSET_BASE(__cpu, DDR) \ | |
| d430b6c5 MB |
404 | __GEN_RSET_BASE(__cpu, M2M) \ |
| 405 | __GEN_RSET_BASE(__cpu, ATM) \ | |
| 406 | __GEN_RSET_BASE(__cpu, XTM) \ | |
| 407 | __GEN_RSET_BASE(__cpu, XTMDMA) \ | |
| 408 | __GEN_RSET_BASE(__cpu, XTMDMAC) \ | |
| 409 | __GEN_RSET_BASE(__cpu, XTMDMAS) \ | |
| 410 | __GEN_RSET_BASE(__cpu, PCM) \ | |
| 411 | __GEN_RSET_BASE(__cpu, PCMDMA) \ | |
| 412 | __GEN_RSET_BASE(__cpu, PCMDMAC) \ | |
| 413 | __GEN_RSET_BASE(__cpu, PCMDMAS) \ | |
| ec68c520 MB |
414 | } |
| 415 | ||
| 416 | #define __GEN_CPU_REGS_TABLE(__cpu) \ | |
| 417 | [RSET_DSL_LMEM] = BCM_## __cpu ##_DSL_LMEM_BASE, \ | |
| 418 | [RSET_PERF] = BCM_## __cpu ##_PERF_BASE, \ | |
| 419 | [RSET_TIMER] = BCM_## __cpu ##_TIMER_BASE, \ | |
| 420 | [RSET_WDT] = BCM_## __cpu ##_WDT_BASE, \ | |
| 421 | [RSET_UART0] = BCM_## __cpu ##_UART0_BASE, \ | |
| 422 | [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \ | |
| 423 | [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \ | |
| 424 | [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \ | |
| d430b6c5 | 425 | [RSET_SPI2] = BCM_## __cpu ##_SPI2_BASE, \ |
| ec68c520 MB |
426 | [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \ |
| 427 | [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \ | |
| 428 | [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \ | |
| 429 | [RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \ | |
| 430 | [RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \ | |
| 431 | [RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \ | |
| 432 | [RSET_DSL] = BCM_## __cpu ##_DSL_BASE, \ | |
| 433 | [RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \ | |
| 434 | [RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \ | |
| 435 | [RSET_ENETDMA] = BCM_## __cpu ##_ENETDMA_BASE, \ | |
| d430b6c5 MB |
436 | [RSET_ENETDMAC] = BCM_## __cpu ##_ENETDMAC_BASE, \ |
| 437 | [RSET_ENETDMAS] = BCM_## __cpu ##_ENETDMAS_BASE, \ | |
| 438 | [RSET_ENETSW] = BCM_## __cpu ##_ENETSW_BASE, \ | |
| ec68c520 MB |
439 | [RSET_EHCI0] = BCM_## __cpu ##_EHCI0_BASE, \ |
| 440 | [RSET_SDRAM] = BCM_## __cpu ##_SDRAM_BASE, \ | |
| 441 | [RSET_MEMC] = BCM_## __cpu ##_MEMC_BASE, \ | |
| 442 | [RSET_DDR] = BCM_## __cpu ##_DDR_BASE, \ | |
| d430b6c5 MB |
443 | [RSET_M2M] = BCM_## __cpu ##_M2M_BASE, \ |
| 444 | [RSET_ATM] = BCM_## __cpu ##_ATM_BASE, \ | |
| 445 | [RSET_XTM] = BCM_## __cpu ##_XTM_BASE, \ | |
| 446 | [RSET_XTMDMA] = BCM_## __cpu ##_XTMDMA_BASE, \ | |
| 447 | [RSET_XTMDMAC] = BCM_## __cpu ##_XTMDMAC_BASE, \ | |
| 448 | [RSET_XTMDMAS] = BCM_## __cpu ##_XTMDMAS_BASE, \ | |
| 449 | [RSET_PCM] = BCM_## __cpu ##_PCM_BASE, \ | |
| 450 | [RSET_PCMDMA] = BCM_## __cpu ##_PCMDMA_BASE, \ | |
| 451 | [RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \ | |
| 452 | [RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \ | |
| ec68c520 MB |
453 | |
| 454 | ||
| e7300d04 MB |
455 | static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) |
| 456 | { | |
| 457 | #ifdef BCMCPU_RUNTIME_DETECT | |
| 458 | return bcm63xx_regs_base[set]; | |
| 459 | #else | |
| 460 | #ifdef CONFIG_BCM63XX_CPU_6338 | |
| ec68c520 | 461 | __GEN_RSET(6338) |
| e7300d04 MB |
462 | #endif |
| 463 | #ifdef CONFIG_BCM63XX_CPU_6345 | |
| ec68c520 | 464 | __GEN_RSET(6345) |
| e7300d04 MB |
465 | #endif |
| 466 | #ifdef CONFIG_BCM63XX_CPU_6348 | |
| ec68c520 | 467 | __GEN_RSET(6348) |
| e7300d04 MB |
468 | #endif |
| 469 | #ifdef CONFIG_BCM63XX_CPU_6358 | |
| ec68c520 | 470 | __GEN_RSET(6358) |
| e7300d04 | 471 | #endif |
| 04712f3f MB |
472 | #ifdef CONFIG_BCM63XX_CPU_6368 |
| 473 | __GEN_RSET(6368) | |
| 474 | #endif | |
| e7300d04 MB |
475 | #endif |
| 476 | /* unreached */ | |
| 477 | return 0; | |
| 478 | } | |
| 479 | ||
| 480 | /* | |
| 481 | * IRQ number changes across CPU too | |
| 482 | */ | |
| 483 | enum bcm63xx_irq { | |
| 484 | IRQ_TIMER = 0, | |
| 0aeee715 | 485 | IRQ_SPI, |
| e7300d04 | 486 | IRQ_UART0, |
| 524ef29c | 487 | IRQ_UART1, |
| e7300d04 MB |
488 | IRQ_DSL, |
| 489 | IRQ_ENET0, | |
| 490 | IRQ_ENET1, | |
| 491 | IRQ_ENET_PHY, | |
| 492 | IRQ_OHCI0, | |
| 493 | IRQ_EHCI0, | |
| e7300d04 MB |
494 | IRQ_ENET0_RXDMA, |
| 495 | IRQ_ENET0_TXDMA, | |
| 496 | IRQ_ENET1_RXDMA, | |
| 497 | IRQ_ENET1_TXDMA, | |
| 498 | IRQ_PCI, | |
| 499 | IRQ_PCMCIA, | |
| d430b6c5 MB |
500 | IRQ_ATM, |
| 501 | IRQ_ENETSW_RXDMA0, | |
| 502 | IRQ_ENETSW_RXDMA1, | |
| 503 | IRQ_ENETSW_RXDMA2, | |
| 504 | IRQ_ENETSW_RXDMA3, | |
| 505 | IRQ_ENETSW_TXDMA0, | |
| 506 | IRQ_ENETSW_TXDMA1, | |
| 507 | IRQ_ENETSW_TXDMA2, | |
| 508 | IRQ_ENETSW_TXDMA3, | |
| 509 | IRQ_XTM, | |
| 510 | IRQ_XTM_DMA0, | |
| e7300d04 MB |
511 | }; |
| 512 | ||
| 513 | /* | |
| 514 | * 6338 irqs | |
| 515 | */ | |
| 516 | #define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) | |
| 0aeee715 | 517 | #define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1) |
| e7300d04 | 518 | #define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2) |
| ec68c520 | 519 | #define BCM_6338_UART1_IRQ 0 |
| e7300d04 | 520 | #define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5) |
| e7300d04 | 521 | #define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) |
| ec68c520 | 522 | #define BCM_6338_ENET1_IRQ 0 |
| e7300d04 | 523 | #define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) |
| ec68c520 MB |
524 | #define BCM_6338_OHCI0_IRQ 0 |
| 525 | #define BCM_6338_EHCI0_IRQ 0 | |
| e7300d04 MB |
526 | #define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) |
| 527 | #define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) | |
| ec68c520 MB |
528 | #define BCM_6338_ENET1_RXDMA_IRQ 0 |
| 529 | #define BCM_6338_ENET1_TXDMA_IRQ 0 | |
| 530 | #define BCM_6338_PCI_IRQ 0 | |
| 531 | #define BCM_6338_PCMCIA_IRQ 0 | |
| d430b6c5 MB |
532 | #define BCM_6338_ATM_IRQ 0 |
| 533 | #define BCM_6338_ENETSW_RXDMA0_IRQ 0 | |
| 534 | #define BCM_6338_ENETSW_RXDMA1_IRQ 0 | |
| 535 | #define BCM_6338_ENETSW_RXDMA2_IRQ 0 | |
| 536 | #define BCM_6338_ENETSW_RXDMA3_IRQ 0 | |
| 537 | #define BCM_6338_ENETSW_TXDMA0_IRQ 0 | |
| 538 | #define BCM_6338_ENETSW_TXDMA1_IRQ 0 | |
| 539 | #define BCM_6338_ENETSW_TXDMA2_IRQ 0 | |
| 540 | #define BCM_6338_ENETSW_TXDMA3_IRQ 0 | |
| 541 | #define BCM_6338_XTM_IRQ 0 | |
| 542 | #define BCM_6338_XTM_DMA0_IRQ 0 | |
| e7300d04 MB |
543 | |
| 544 | /* | |
| 545 | * 6345 irqs | |
| 546 | */ | |
| 547 | #define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) | |
| 0aeee715 | 548 | #define BCM_6345_SPI_IRQ 0 |
| e7300d04 | 549 | #define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2) |
| ec68c520 | 550 | #define BCM_6345_UART1_IRQ 0 |
| e7300d04 | 551 | #define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3) |
| e7300d04 | 552 | #define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) |
| ec68c520 | 553 | #define BCM_6345_ENET1_IRQ 0 |
| e7300d04 | 554 | #define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) |
| ec68c520 MB |
555 | #define BCM_6345_OHCI0_IRQ 0 |
| 556 | #define BCM_6345_EHCI0_IRQ 0 | |
| e7300d04 MB |
557 | #define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1) |
| 558 | #define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2) | |
| ec68c520 MB |
559 | #define BCM_6345_ENET1_RXDMA_IRQ 0 |
| 560 | #define BCM_6345_ENET1_TXDMA_IRQ 0 | |
| 561 | #define BCM_6345_PCI_IRQ 0 | |
| 562 | #define BCM_6345_PCMCIA_IRQ 0 | |
| d430b6c5 MB |
563 | #define BCM_6345_ATM_IRQ 0 |
| 564 | #define BCM_6345_ENETSW_RXDMA0_IRQ 0 | |
| 565 | #define BCM_6345_ENETSW_RXDMA1_IRQ 0 | |
| 566 | #define BCM_6345_ENETSW_RXDMA2_IRQ 0 | |
| 567 | #define BCM_6345_ENETSW_RXDMA3_IRQ 0 | |
| 568 | #define BCM_6345_ENETSW_TXDMA0_IRQ 0 | |
| 569 | #define BCM_6345_ENETSW_TXDMA1_IRQ 0 | |
| 570 | #define BCM_6345_ENETSW_TXDMA2_IRQ 0 | |
| 571 | #define BCM_6345_ENETSW_TXDMA3_IRQ 0 | |
| 572 | #define BCM_6345_XTM_IRQ 0 | |
| 573 | #define BCM_6345_XTM_DMA0_IRQ 0 | |
| e7300d04 MB |
574 | |
| 575 | /* | |
| 576 | * 6348 irqs | |
| 577 | */ | |
| 578 | #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) | |
| 0aeee715 | 579 | #define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1) |
| e7300d04 | 580 | #define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2) |
| ec68c520 | 581 | #define BCM_6348_UART1_IRQ 0 |
| e7300d04 | 582 | #define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4) |
| e7300d04 | 583 | #define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) |
| ec68c520 | 584 | #define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7) |
| e7300d04 MB |
585 | #define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) |
| 586 | #define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12) | |
| ec68c520 | 587 | #define BCM_6348_EHCI0_IRQ 0 |
| e7300d04 MB |
588 | #define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20) |
| 589 | #define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21) | |
| 590 | #define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22) | |
| 591 | #define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23) | |
| e7300d04 | 592 | #define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24) |
| ec68c520 | 593 | #define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) |
| d430b6c5 MB |
594 | #define BCM_6348_ATM_IRQ (IRQ_INTERNAL_BASE + 5) |
| 595 | #define BCM_6348_ENETSW_RXDMA0_IRQ 0 | |
| 596 | #define BCM_6348_ENETSW_RXDMA1_IRQ 0 | |
| 597 | #define BCM_6348_ENETSW_RXDMA2_IRQ 0 | |
| 598 | #define BCM_6348_ENETSW_RXDMA3_IRQ 0 | |
| 599 | #define BCM_6348_ENETSW_TXDMA0_IRQ 0 | |
| 600 | #define BCM_6348_ENETSW_TXDMA1_IRQ 0 | |
| 601 | #define BCM_6348_ENETSW_TXDMA2_IRQ 0 | |
| 602 | #define BCM_6348_ENETSW_TXDMA3_IRQ 0 | |
| 603 | #define BCM_6348_XTM_IRQ 0 | |
| 604 | #define BCM_6348_XTM_DMA0_IRQ 0 | |
| e7300d04 MB |
605 | |
| 606 | /* | |
| 607 | * 6358 irqs | |
| 608 | */ | |
| 609 | #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) | |
| 0aeee715 | 610 | #define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1) |
| e7300d04 | 611 | #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2) |
| 524ef29c | 612 | #define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3) |
| ec68c520 | 613 | #define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29) |
| e7300d04 | 614 | #define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) |
| ec68c520 | 615 | #define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6) |
| e7300d04 | 616 | #define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) |
| ec68c520 | 617 | #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) |
| e7300d04 MB |
618 | #define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) |
| 619 | #define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) | |
| 620 | #define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) | |
| 621 | #define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17) | |
| 622 | #define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18) | |
| e7300d04 MB |
623 | #define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31) |
| 624 | #define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) | |
| d430b6c5 MB |
625 | #define BCM_6358_ATM_IRQ (IRQ_INTERNAL_BASE + 19) |
| 626 | #define BCM_6358_ENETSW_RXDMA0_IRQ 0 | |
| 627 | #define BCM_6358_ENETSW_RXDMA1_IRQ 0 | |
| 628 | #define BCM_6358_ENETSW_RXDMA2_IRQ 0 | |
| 629 | #define BCM_6358_ENETSW_RXDMA3_IRQ 0 | |
| 630 | #define BCM_6358_ENETSW_TXDMA0_IRQ 0 | |
| 631 | #define BCM_6358_ENETSW_TXDMA1_IRQ 0 | |
| 632 | #define BCM_6358_ENETSW_TXDMA2_IRQ 0 | |
| 633 | #define BCM_6358_ENETSW_TXDMA3_IRQ 0 | |
| 634 | #define BCM_6358_XTM_IRQ 0 | |
| 635 | #define BCM_6358_XTM_DMA0_IRQ 0 | |
| 636 | ||
| 637 | #define BCM_6358_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 23) | |
| 638 | #define BCM_6358_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 24) | |
| 639 | #define BCM_6358_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25) | |
| 640 | #define BCM_6358_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26) | |
| 641 | #define BCM_6358_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27) | |
| 642 | #define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28) | |
| e7300d04 | 643 | |
| 04712f3f MB |
644 | /* |
| 645 | * 6368 irqs | |
| 646 | */ | |
| 647 | #define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) | |
| 648 | ||
| 649 | #define BCM_6368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) | |
| 0aeee715 | 650 | #define BCM_6368_SPI_IRQ (IRQ_INTERNAL_BASE + 1) |
| 04712f3f MB |
651 | #define BCM_6368_UART0_IRQ (IRQ_INTERNAL_BASE + 2) |
| 652 | #define BCM_6368_UART1_IRQ (IRQ_INTERNAL_BASE + 3) | |
| 653 | #define BCM_6368_DSL_IRQ (IRQ_INTERNAL_BASE + 4) | |
| 654 | #define BCM_6368_ENET0_IRQ 0 | |
| 655 | #define BCM_6368_ENET1_IRQ 0 | |
| 656 | #define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15) | |
| 657 | #define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) | |
| 658 | #define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7) | |
| 659 | #define BCM_6368_PCMCIA_IRQ 0 | |
| 660 | #define BCM_6368_ENET0_RXDMA_IRQ 0 | |
| 661 | #define BCM_6368_ENET0_TXDMA_IRQ 0 | |
| 662 | #define BCM_6368_ENET1_RXDMA_IRQ 0 | |
| 663 | #define BCM_6368_ENET1_TXDMA_IRQ 0 | |
| 664 | #define BCM_6368_PCI_IRQ (IRQ_INTERNAL_BASE + 13) | |
| 665 | #define BCM_6368_ATM_IRQ 0 | |
| 666 | #define BCM_6368_ENETSW_RXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 0) | |
| 667 | #define BCM_6368_ENETSW_RXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 1) | |
| 668 | #define BCM_6368_ENETSW_RXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 2) | |
| 669 | #define BCM_6368_ENETSW_RXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 3) | |
| 670 | #define BCM_6368_ENETSW_TXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 4) | |
| 671 | #define BCM_6368_ENETSW_TXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 5) | |
| 672 | #define BCM_6368_ENETSW_TXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 6) | |
| 673 | #define BCM_6368_ENETSW_TXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 7) | |
| 674 | #define BCM_6368_XTM_IRQ (IRQ_INTERNAL_BASE + 11) | |
| 675 | #define BCM_6368_XTM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 8) | |
| 676 | ||
| 677 | #define BCM_6368_PCM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 30) | |
| 678 | #define BCM_6368_PCM_DMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 31) | |
| 679 | #define BCM_6368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 20) | |
| 680 | #define BCM_6368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 21) | |
| 681 | #define BCM_6368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 22) | |
| 682 | #define BCM_6368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 23) | |
| 683 | #define BCM_6368_EXT_IRQ4 (IRQ_INTERNAL_BASE + 24) | |
| 684 | #define BCM_6368_EXT_IRQ5 (IRQ_INTERNAL_BASE + 25) | |
| 685 | ||
| e7300d04 MB |
686 | extern const int *bcm63xx_irqs; |
| 687 | ||
| ec68c520 MB |
688 | #define __GEN_CPU_IRQ_TABLE(__cpu) \ |
| 689 | [IRQ_TIMER] = BCM_## __cpu ##_TIMER_IRQ, \ | |
| 0aeee715 | 690 | [IRQ_SPI] = BCM_## __cpu ##_SPI_IRQ, \ |
| ec68c520 MB |
691 | [IRQ_UART0] = BCM_## __cpu ##_UART0_IRQ, \ |
| 692 | [IRQ_UART1] = BCM_## __cpu ##_UART1_IRQ, \ | |
| 693 | [IRQ_DSL] = BCM_## __cpu ##_DSL_IRQ, \ | |
| 694 | [IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \ | |
| 695 | [IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \ | |
| 696 | [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \ | |
| 697 | [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \ | |
| 698 | [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \ | |
| 699 | [IRQ_ENET0_RXDMA] = BCM_## __cpu ##_ENET0_RXDMA_IRQ, \ | |
| 700 | [IRQ_ENET0_TXDMA] = BCM_## __cpu ##_ENET0_TXDMA_IRQ, \ | |
| 701 | [IRQ_ENET1_RXDMA] = BCM_## __cpu ##_ENET1_RXDMA_IRQ, \ | |
| 702 | [IRQ_ENET1_TXDMA] = BCM_## __cpu ##_ENET1_TXDMA_IRQ, \ | |
| 703 | [IRQ_PCI] = BCM_## __cpu ##_PCI_IRQ, \ | |
| 704 | [IRQ_PCMCIA] = BCM_## __cpu ##_PCMCIA_IRQ, \ | |
| d430b6c5 MB |
705 | [IRQ_ATM] = BCM_## __cpu ##_ATM_IRQ, \ |
| 706 | [IRQ_ENETSW_RXDMA0] = BCM_## __cpu ##_ENETSW_RXDMA0_IRQ, \ | |
| 707 | [IRQ_ENETSW_RXDMA1] = BCM_## __cpu ##_ENETSW_RXDMA1_IRQ, \ | |
| 708 | [IRQ_ENETSW_RXDMA2] = BCM_## __cpu ##_ENETSW_RXDMA2_IRQ, \ | |
| 709 | [IRQ_ENETSW_RXDMA3] = BCM_## __cpu ##_ENETSW_RXDMA3_IRQ, \ | |
| 710 | [IRQ_ENETSW_TXDMA0] = BCM_## __cpu ##_ENETSW_TXDMA0_IRQ, \ | |
| 711 | [IRQ_ENETSW_TXDMA1] = BCM_## __cpu ##_ENETSW_TXDMA1_IRQ, \ | |
| 712 | [IRQ_ENETSW_TXDMA2] = BCM_## __cpu ##_ENETSW_TXDMA2_IRQ, \ | |
| 713 | [IRQ_ENETSW_TXDMA3] = BCM_## __cpu ##_ENETSW_TXDMA3_IRQ, \ | |
| 714 | [IRQ_XTM] = BCM_## __cpu ##_XTM_IRQ, \ | |
| 715 | [IRQ_XTM_DMA0] = BCM_## __cpu ##_XTM_DMA0_IRQ, \ | |
| ec68c520 | 716 | |
| e7300d04 MB |
717 | static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq) |
| 718 | { | |
| 719 | return bcm63xx_irqs[irq]; | |
| 720 | } | |
| 721 | ||
| 722 | /* | |
| 723 | * return installed memory size | |
| 724 | */ | |
| 725 | unsigned int bcm63xx_get_memory_size(void); | |
| 726 | ||
| d430b6c5 MB |
727 | void bcm63xx_machine_halt(void); |
| 728 | ||
| 729 | void bcm63xx_machine_reboot(void); | |
| 730 | ||
| e7300d04 | 731 | #endif /* !BCM63XX_CPU_H_ */ |