[mirror_ubuntu-bionic-kernel.git] / arch / mips / include / asm / mach-bcm63xx / bcm63xx_dev_enet.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef BCM63XX_DEV_ENET_H_
#define BCM63XX_DEV_ENET_H_

#include <linux/if_ether.h>
#include <linux/init.h>

#include <bcm63xx_regs.h>

/*
 * on board ethernet platform data
 */
struct bcm63xx_enet_platform_data {
	char mac_addr[ETH_ALEN];

	int has_phy;

	/* if has_phy, then set use_internal_phy */
	int use_internal_phy;

	/* or fill phy info to use an external one */
	int phy_id;
	int has_phy_interrupt;
	int phy_interrupt;

	/* if has_phy, use autonegotiated pause parameters or force
	 * them */
	int pause_auto;
	int pause_rx;
	int pause_tx;

	/* if !has_phy, set desired forced speed/duplex */
	int force_speed_100;
	int force_duplex_full;

	/* if !has_phy, set callback to perform mii device
	 * init/remove */
	int (*mii_config)(struct net_device *dev, int probe,
			  int (*mii_read)(struct net_device *dev,
					  int phy_id, int reg),
			  void (*mii_write)(struct net_device *dev,
					    int phy_id, int reg, int val));

	/* DMA channel enable mask */
	u32 dma_chan_en_mask;

	/* DMA channel interrupt mask */
	u32 dma_chan_int_mask;

	/* DMA engine has internal SRAM */
	bool dma_has_sram;

	/* DMA channel register width */
	unsigned int dma_chan_width;

	/* DMA descriptor shift */
	unsigned int dma_desc_shift;
};

/*
 * on board ethernet switch platform data
 */
#define ENETSW_MAX_PORT	8
#define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
#define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */

#define ENETSW_RGMII_PORT0	4

struct bcm63xx_enetsw_port {
	int		used;
	int		phy_id;

	int		bypass_link;
	int		force_speed;
	int		force_duplex_full;

	const char	*name;
};

struct bcm63xx_enetsw_platform_data {
	char mac_addr[ETH_ALEN];
	int num_ports;
	struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];

	/* DMA channel enable mask */
	u32 dma_chan_en_mask;

	/* DMA channel interrupt mask */
	u32 dma_chan_int_mask;

	/* DMA channel register width */
	unsigned int dma_chan_width;

	/* DMA engine has internal SRAM */
	bool dma_has_sram;
};

int __init bcm63xx_enet_register(int unit,
				 const struct bcm63xx_enet_platform_data *pd);

int bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd);

enum bcm63xx_regs_enetdmac {
	ENETDMAC_CHANCFG,
	ENETDMAC_IR,
	ENETDMAC_IRMASK,
	ENETDMAC_MAXBURST,
	ENETDMAC_BUFALLOC,
	ENETDMAC_RSTART,
	ENETDMAC_FC,
	ENETDMAC_LEN,
};

static inline unsigned long bcm63xx_enetdmacreg(enum bcm63xx_regs_enetdmac reg)
{
	extern const unsigned long *bcm63xx_regs_enetdmac;

	return bcm63xx_regs_enetdmac[reg];
}


#endif /* ! BCM63XX_DEV_ENET_H_ */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
e7300d04 MB	2	#ifndef BCM63XX_DEV_ENET_H_
	3	#define BCM63XX_DEV_ENET_H_
	4
	5	#include <linux/if_ether.h>
	6	#include <linux/init.h>
	7
3dc6475c FF	8	#include <bcm63xx_regs.h>
3dc6475c FF	9
e7300d04 MB	10	/*
	11	* on board ethernet platform data
	12	*/
	13	struct bcm63xx_enet_platform_data {
	14	char mac_addr[ETH_ALEN];
	15
	16	int has_phy;
	17
	18	/* if has_phy, then set use_internal_phy */
	19	int use_internal_phy;
	20
	21	/* or fill phy info to use an external one */
	22	int phy_id;
	23	int has_phy_interrupt;
	24	int phy_interrupt;
	25
e904b94a	26	/* if has_phy, use autonegotiated pause parameters or force
e7300d04 MB	27	* them */
	28	int pause_auto;
	29	int pause_rx;
	30	int pause_tx;
	31
	32	/* if !has_phy, set desired forced speed/duplex */
	33	int force_speed_100;
	34	int force_duplex_full;
	35
	36	/* if !has_phy, set callback to perform mii device
	37	* init/remove */
	38	int (mii_config)(struct net_device dev, int probe,
	39	int (mii_read)(struct net_device dev,
	40	int phy_id, int reg),
	41	void (mii_write)(struct net_device dev,
	42	int phy_id, int reg, int val));
3dc6475c FF	43
	44	/* DMA channel enable mask */
	45	u32 dma_chan_en_mask;
	46
	47	/* DMA channel interrupt mask */
	48	u32 dma_chan_int_mask;
	49
	50	/* DMA engine has internal SRAM */
	51	bool dma_has_sram;
	52
	53	/* DMA channel register width */
	54	unsigned int dma_chan_width;
	55
	56	/* DMA descriptor shift */
	57	unsigned int dma_desc_shift;
e7300d04 MB	58	};
e7300d04 MB	59
6f00a022 MB	60	/*
	61	* on board ethernet switch platform data
	62	*/
	63	#define ENETSW_MAX_PORT 8
	64	#define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
	65	#define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
	66
	67	#define ENETSW_RGMII_PORT0 4
	68
	69	struct bcm63xx_enetsw_port {
	70	int used;
	71	int phy_id;
	72
	73	int bypass_link;
	74	int force_speed;
	75	int force_duplex_full;
	76
	77	const char *name;
	78	};
	79
	80	struct bcm63xx_enetsw_platform_data {
	81	char mac_addr[ETH_ALEN];
	82	int num_ports;
	83	struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
3dc6475c FF	84
	85	/* DMA channel enable mask */
	86	u32 dma_chan_en_mask;
	87
	88	/* DMA channel interrupt mask */
	89	u32 dma_chan_int_mask;
	90
	91	/* DMA channel register width */
	92	unsigned int dma_chan_width;
	93
	94	/* DMA engine has internal SRAM */
	95	bool dma_has_sram;
6f00a022 MB	96	};
6f00a022 MB	97
e7300d04 MB	98	int __init bcm63xx_enet_register(int unit,
	99	const struct bcm63xx_enet_platform_data *pd);
	100
6f00a022 MB	101	int bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd);
6f00a022 MB	102
3dc6475c FF	103	enum bcm63xx_regs_enetdmac {
	104	ENETDMAC_CHANCFG,
	105	ENETDMAC_IR,
	106	ENETDMAC_IRMASK,
	107	ENETDMAC_MAXBURST,
	108	ENETDMAC_BUFALLOC,
	109	ENETDMAC_RSTART,
	110	ENETDMAC_FC,
	111	ENETDMAC_LEN,
	112	};
	113
	114	static inline unsigned long bcm63xx_enetdmacreg(enum bcm63xx_regs_enetdmac reg)
	115	{
3dc6475c FF	116	extern const unsigned long *bcm63xx_regs_enetdmac;
	117
	118	return bcm63xx_regs_enetdmac[reg];
3dc6475c FF	119	}
	120
	121
e7300d04	122	#endif /* ! BCM63XX_DEV_ENET_H_ */