projects / mirror_ubuntu-eoan-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 2874c5fd | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 33afab80 MR |
2 | /* |
| 3 | * CPU feature overrides for DECstation systems. Two variations | |
| 4 | * are generally applicable. | |
| 5 | * | |
| 6 | * Copyright (C) 2013 Maciej W. Rozycki | |
| 33afab80 MR |
7 | */ |
| 8 | #ifndef __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H | |
| 9 | #define __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H | |
| 10 | ||
| 11 | /* Generic ones first. */ | |
| 12 | #define cpu_has_tlb 1 | |
| bc4f12e6 MR |
13 | #define cpu_has_tlbinv 0 |
| 14 | #define cpu_has_segments 0 | |
| 15 | #define cpu_has_eva 0 | |
| 16 | #define cpu_has_htw 0 | |
| 17 | #define cpu_has_rixiex 0 | |
| 18 | #define cpu_has_maar 0 | |
| 19 | #define cpu_has_rw_llb 0 | |
| 33afab80 | 20 | #define cpu_has_tx39_cache 0 |
| 33afab80 MR |
21 | #define cpu_has_divec 0 |
| 22 | #define cpu_has_prefetch 0 | |
| 23 | #define cpu_has_mcheck 0 | |
| 24 | #define cpu_has_ejtag 0 | |
| 25 | #define cpu_has_mips16 0 | |
| 65ae8d26 | 26 | #define cpu_has_mips16e2 0 |
| 33afab80 MR |
27 | #define cpu_has_mdmx 0 |
| 28 | #define cpu_has_mips3d 0 | |
| 29 | #define cpu_has_smartmips 0 | |
| 30 | #define cpu_has_rixi 0 | |
| bc4f12e6 | 31 | #define cpu_has_xpa 0 |
| 33afab80 MR |
32 | #define cpu_has_vtag_icache 0 |
| 33 | #define cpu_has_ic_fills_f_dc 0 | |
| 34 | #define cpu_has_pindexed_dcache 0 | |
| 35 | #define cpu_has_local_ebase 0 | |
| 36 | #define cpu_icache_snoops_remote_store 1 | |
| 37 | #define cpu_has_mips_4 0 | |
| 38 | #define cpu_has_mips_5 0 | |
| 39 | #define cpu_has_mips32r1 0 | |
| 40 | #define cpu_has_mips32r2 0 | |
| 41 | #define cpu_has_mips64r1 0 | |
| 42 | #define cpu_has_mips64r2 0 | |
| 43 | #define cpu_has_dsp 0 | |
| bc4f12e6 | 44 | #define cpu_has_dsp2 0 |
| 33afab80 MR |
45 | #define cpu_has_mipsmt 0 |
| 46 | #define cpu_has_userlocal 0 | |
| bc4f12e6 MR |
47 | #define cpu_hwrena_impl_bits 0 |
| 48 | #define cpu_has_perf_cntr_intr_bit 0 | |
| 49 | #define cpu_has_vz 0 | |
| 50 | #define cpu_has_fre 0 | |
| 51 | #define cpu_has_cdmm 0 | |
| 33afab80 MR |
52 | |
| 53 | /* R3k-specific ones. */ | |
| 54 | #ifdef CONFIG_CPU_R3000 | |
| bc4f12e6 | 55 | #define cpu_has_3kex 1 |
| 33afab80 MR |
56 | #define cpu_has_4kex 0 |
| 57 | #define cpu_has_3k_cache 1 | |
| 58 | #define cpu_has_4k_cache 0 | |
| 59 | #define cpu_has_32fpr 0 | |
| 60 | #define cpu_has_counter 0 | |
| 61 | #define cpu_has_watch 0 | |
| 62 | #define cpu_has_vce 0 | |
| 63 | #define cpu_has_cache_cdex_p 0 | |
| 64 | #define cpu_has_cache_cdex_s 0 | |
| 65 | #define cpu_has_llsc 0 | |
| 66 | #define cpu_has_dc_aliases 0 | |
| 67 | #define cpu_has_mips_2 0 | |
| 68 | #define cpu_has_mips_3 0 | |
| 69 | #define cpu_has_nofpuex 1 | |
| 70 | #define cpu_has_inclusive_pcaches 0 | |
| 71 | #define cpu_dcache_line_size() 4 | |
| 72 | #define cpu_icache_line_size() 4 | |
| 73 | #define cpu_scache_line_size() 0 | |
| 74 | #endif /* CONFIG_CPU_R3000 */ | |
| 75 | ||
| 76 | /* R4k-specific ones. */ | |
| 77 | #ifdef CONFIG_CPU_R4X00 | |
| bc4f12e6 | 78 | #define cpu_has_3kex 0 |
| 33afab80 MR |
79 | #define cpu_has_4kex 1 |
| 80 | #define cpu_has_3k_cache 0 | |
| 81 | #define cpu_has_4k_cache 1 | |
| 82 | #define cpu_has_32fpr 1 | |
| 83 | #define cpu_has_counter 1 | |
| 84 | #define cpu_has_watch 1 | |
| 85 | #define cpu_has_vce 1 | |
| 86 | #define cpu_has_cache_cdex_p 1 | |
| 87 | #define cpu_has_cache_cdex_s 1 | |
| 88 | #define cpu_has_llsc 1 | |
| 89 | #define cpu_has_dc_aliases (PAGE_SIZE < 0x4000) | |
| 90 | #define cpu_has_mips_2 1 | |
| 91 | #define cpu_has_mips_3 1 | |
| 92 | #define cpu_has_nofpuex 0 | |
| 93 | #define cpu_has_inclusive_pcaches 1 | |
| 94 | #define cpu_dcache_line_size() 16 | |
| 95 | #define cpu_icache_line_size() 16 | |
| 96 | #define cpu_scache_line_size() 32 | |
| 97 | #endif /* CONFIG_CPU_R4X00 */ | |
| 98 | ||
| 99 | #endif /* __ASM_MACH_DEC_CPU_FEATURE_OVERRIDES_H */ |