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Commit | Line | Data |
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22c21003 | 1 | /* |
25985edc | 2 | * The header file of cs5536 south bridge. |
22c21003 WZ |
3 | * |
4 | * Copyright (C) 2007 Lemote, Inc. | |
5 | * Author : jlliu <liujl@lemote.com> | |
6 | */ | |
7 | ||
70342287 RB |
8 | #ifndef _CS5536_H |
9 | #define _CS5536_H | |
22c21003 WZ |
10 | |
11 | #include <linux/types.h> | |
12 | ||
13 | extern void _rdmsr(u32 msr, u32 *hi, u32 *lo); | |
14 | extern void _wrmsr(u32 msr, u32 hi, u32 lo); | |
15 | ||
16 | /* | |
17 | * MSR module base | |
18 | */ | |
70342287 RB |
19 | #define CS5536_SB_MSR_BASE (0x00000000) |
20 | #define CS5536_GLIU_MSR_BASE (0x10000000) | |
21 | #define CS5536_ILLEGAL_MSR_BASE (0x20000000) | |
22 | #define CS5536_USB_MSR_BASE (0x40000000) | |
23 | #define CS5536_IDE_MSR_BASE (0x60000000) | |
24 | #define CS5536_DIVIL_MSR_BASE (0x80000000) | |
25 | #define CS5536_ACC_MSR_BASE (0xa0000000) | |
26 | #define CS5536_UNUSED_MSR_BASE (0xc0000000) | |
27 | #define CS5536_GLCP_MSR_BASE (0xe0000000) | |
22c21003 | 28 | |
70342287 RB |
29 | #define SB_MSR_REG(offset) (CS5536_SB_MSR_BASE | (offset)) |
30 | #define GLIU_MSR_REG(offset) (CS5536_GLIU_MSR_BASE | (offset)) | |
31 | #define ILLEGAL_MSR_REG(offset) (CS5536_ILLEGAL_MSR_BASE | (offset)) | |
32 | #define USB_MSR_REG(offset) (CS5536_USB_MSR_BASE | (offset)) | |
33 | #define IDE_MSR_REG(offset) (CS5536_IDE_MSR_BASE | (offset)) | |
34 | #define DIVIL_MSR_REG(offset) (CS5536_DIVIL_MSR_BASE | (offset)) | |
35 | #define ACC_MSR_REG(offset) (CS5536_ACC_MSR_BASE | (offset)) | |
36 | #define UNUSED_MSR_REG(offset) (CS5536_UNUSED_MSR_BASE | (offset)) | |
37 | #define GLCP_MSR_REG(offset) (CS5536_GLCP_MSR_BASE | (offset)) | |
22c21003 WZ |
38 | |
39 | /* | |
40 | * BAR SPACE OF VIRTUAL PCI : | |
41 | * range for pci probe use, length is the actual size. | |
42 | */ | |
43 | /* IO space for all DIVIL modules */ | |
70342287 RB |
44 | #define CS5536_IRQ_RANGE 0xffffffe0 /* USERD FOR PCI PROBE */ |
45 | #define CS5536_IRQ_LENGTH 0x20 /* THE REGS ACTUAL LENGTH */ | |
46 | #define CS5536_SMB_RANGE 0xfffffff8 | |
47 | #define CS5536_SMB_LENGTH 0x08 | |
48 | #define CS5536_GPIO_RANGE 0xffffff00 | |
49 | #define CS5536_GPIO_LENGTH 0x100 | |
50 | #define CS5536_MFGPT_RANGE 0xffffffc0 | |
51 | #define CS5536_MFGPT_LENGTH 0x40 | |
52 | #define CS5536_ACPI_RANGE 0xffffffe0 | |
53 | #define CS5536_ACPI_LENGTH 0x20 | |
54 | #define CS5536_PMS_RANGE 0xffffff80 | |
55 | #define CS5536_PMS_LENGTH 0x80 | |
22c21003 | 56 | /* IO space for IDE */ |
70342287 RB |
57 | #define CS5536_IDE_RANGE 0xfffffff0 |
58 | #define CS5536_IDE_LENGTH 0x10 | |
22c21003 | 59 | /* IO space for ACC */ |
70342287 RB |
60 | #define CS5536_ACC_RANGE 0xffffff80 |
61 | #define CS5536_ACC_LENGTH 0x80 | |
22c21003 | 62 | /* MEM space for ALL USB modules */ |
70342287 RB |
63 | #define CS5536_OHCI_RANGE 0xfffff000 |
64 | #define CS5536_OHCI_LENGTH 0x1000 | |
65 | #define CS5536_EHCI_RANGE 0xfffff000 | |
66 | #define CS5536_EHCI_LENGTH 0x1000 | |
22c21003 WZ |
67 | |
68 | /* | |
69 | * PCI MSR ACCESS | |
70 | */ | |
70342287 RB |
71 | #define PCI_MSR_CTRL 0xF0 |
72 | #define PCI_MSR_ADDR 0xF4 | |
73 | #define PCI_MSR_DATA_LO 0xF8 | |
74 | #define PCI_MSR_DATA_HI 0xFC | |
22c21003 WZ |
75 | |
76 | /**************** MSR *****************************/ | |
77 | ||
78 | /* | |
79 | * GLIU STANDARD MSR | |
80 | */ | |
70342287 RB |
81 | #define GLIU_CAP 0x00 |
82 | #define GLIU_CONFIG 0x01 | |
83 | #define GLIU_SMI 0x02 | |
84 | #define GLIU_ERROR 0x03 | |
85 | #define GLIU_PM 0x04 | |
86 | #define GLIU_DIAG 0x05 | |
22c21003 WZ |
87 | |
88 | /* | |
89 | * GLIU SPEC. MSR | |
90 | */ | |
70342287 RB |
91 | #define GLIU_P2D_BM0 0x20 |
92 | #define GLIU_P2D_BM1 0x21 | |
93 | #define GLIU_P2D_BM2 0x22 | |
94 | #define GLIU_P2D_BMK0 0x23 | |
95 | #define GLIU_P2D_BMK1 0x24 | |
96 | #define GLIU_P2D_BM3 0x25 | |
97 | #define GLIU_P2D_BM4 0x26 | |
98 | #define GLIU_COH 0x80 | |
99 | #define GLIU_PAE 0x81 | |
100 | #define GLIU_ARB 0x82 | |
101 | #define GLIU_ASMI 0x83 | |
102 | #define GLIU_AERR 0x84 | |
103 | #define GLIU_DEBUG 0x85 | |
104 | #define GLIU_PHY_CAP 0x86 | |
105 | #define GLIU_NOUT_RESP 0x87 | |
106 | #define GLIU_NOUT_WDATA 0x88 | |
107 | #define GLIU_WHOAMI 0x8B | |
108 | #define GLIU_SLV_DIS 0x8C | |
109 | #define GLIU_IOD_BM0 0xE0 | |
110 | #define GLIU_IOD_BM1 0xE1 | |
111 | #define GLIU_IOD_BM2 0xE2 | |
112 | #define GLIU_IOD_BM3 0xE3 | |
113 | #define GLIU_IOD_BM4 0xE4 | |
114 | #define GLIU_IOD_BM5 0xE5 | |
115 | #define GLIU_IOD_BM6 0xE6 | |
116 | #define GLIU_IOD_BM7 0xE7 | |
117 | #define GLIU_IOD_BM8 0xE8 | |
118 | #define GLIU_IOD_BM9 0xE9 | |
119 | #define GLIU_IOD_SC0 0xEA | |
120 | #define GLIU_IOD_SC1 0xEB | |
121 | #define GLIU_IOD_SC2 0xEC | |
122 | #define GLIU_IOD_SC3 0xED | |
123 | #define GLIU_IOD_SC4 0xEE | |
124 | #define GLIU_IOD_SC5 0xEF | |
125 | #define GLIU_IOD_SC6 0xF0 | |
126 | #define GLIU_IOD_SC7 0xF1 | |
22c21003 WZ |
127 | |
128 | /* | |
129 | * SB STANDARD | |
130 | */ | |
70342287 RB |
131 | #define SB_CAP 0x00 |
132 | #define SB_CONFIG 0x01 | |
133 | #define SB_SMI 0x02 | |
134 | #define SB_ERROR 0x03 | |
135 | #define SB_MAR_ERR_EN 0x00000001 | |
136 | #define SB_TAR_ERR_EN 0x00000002 | |
137 | #define SB_RSVD_BIT1 0x00000004 | |
138 | #define SB_EXCEP_ERR_EN 0x00000008 | |
139 | #define SB_SYSE_ERR_EN 0x00000010 | |
140 | #define SB_PARE_ERR_EN 0x00000020 | |
141 | #define SB_TAS_ERR_EN 0x00000040 | |
142 | #define SB_MAR_ERR_FLAG 0x00010000 | |
143 | #define SB_TAR_ERR_FLAG 0x00020000 | |
144 | #define SB_RSVD_BIT2 0x00040000 | |
145 | #define SB_EXCEP_ERR_FLAG 0x00080000 | |
146 | #define SB_SYSE_ERR_FLAG 0x00100000 | |
147 | #define SB_PARE_ERR_FLAG 0x00200000 | |
148 | #define SB_TAS_ERR_FLAG 0x00400000 | |
149 | #define SB_PM 0x04 | |
150 | #define SB_DIAG 0x05 | |
22c21003 WZ |
151 | |
152 | /* | |
153 | * SB SPEC. | |
154 | */ | |
70342287 RB |
155 | #define SB_CTRL 0x10 |
156 | #define SB_R0 0x20 | |
157 | #define SB_R1 0x21 | |
158 | #define SB_R2 0x22 | |
159 | #define SB_R3 0x23 | |
160 | #define SB_R4 0x24 | |
161 | #define SB_R5 0x25 | |
162 | #define SB_R6 0x26 | |
163 | #define SB_R7 0x27 | |
164 | #define SB_R8 0x28 | |
165 | #define SB_R9 0x29 | |
166 | #define SB_R10 0x2A | |
167 | #define SB_R11 0x2B | |
168 | #define SB_R12 0x2C | |
169 | #define SB_R13 0x2D | |
170 | #define SB_R14 0x2E | |
171 | #define SB_R15 0x2F | |
22c21003 WZ |
172 | |
173 | /* | |
174 | * GLCP STANDARD | |
175 | */ | |
70342287 RB |
176 | #define GLCP_CAP 0x00 |
177 | #define GLCP_CONFIG 0x01 | |
178 | #define GLCP_SMI 0x02 | |
179 | #define GLCP_ERROR 0x03 | |
180 | #define GLCP_PM 0x04 | |
181 | #define GLCP_DIAG 0x05 | |
22c21003 WZ |
182 | |
183 | /* | |
184 | * GLCP SPEC. | |
185 | */ | |
70342287 RB |
186 | #define GLCP_CLK_DIS_DELAY 0x08 |
187 | #define GLCP_PM_CLK_DISABLE 0x09 | |
188 | #define GLCP_GLB_PM 0x0B | |
189 | #define GLCP_DBG_OUT 0x0C | |
190 | #define GLCP_RSVD1 0x0D | |
191 | #define GLCP_SOFT_COM 0x0E | |
192 | #define SOFT_BAR_SMB_FLAG 0x00000001 | |
193 | #define SOFT_BAR_GPIO_FLAG 0x00000002 | |
194 | #define SOFT_BAR_MFGPT_FLAG 0x00000004 | |
195 | #define SOFT_BAR_IRQ_FLAG 0x00000008 | |
196 | #define SOFT_BAR_PMS_FLAG 0x00000010 | |
197 | #define SOFT_BAR_ACPI_FLAG 0x00000020 | |
198 | #define SOFT_BAR_IDE_FLAG 0x00000400 | |
199 | #define SOFT_BAR_ACC_FLAG 0x00000800 | |
200 | #define SOFT_BAR_OHCI_FLAG 0x00001000 | |
201 | #define SOFT_BAR_EHCI_FLAG 0x00002000 | |
202 | #define GLCP_RSVD2 0x0F | |
203 | #define GLCP_CLK_OFF 0x10 | |
204 | #define GLCP_CLK_ACTIVE 0x11 | |
205 | #define GLCP_CLK_DISABLE 0x12 | |
206 | #define GLCP_CLK4ACK 0x13 | |
207 | #define GLCP_SYS_RST 0x14 | |
208 | #define GLCP_RSVD3 0x15 | |
209 | #define GLCP_DBG_CLK_CTRL 0x16 | |
210 | #define GLCP_CHIP_REV_ID 0x17 | |
22c21003 WZ |
211 | |
212 | /* PIC */ | |
70342287 RB |
213 | #define PIC_YSEL_LOW 0x20 |
214 | #define PIC_YSEL_LOW_USB_SHIFT 8 | |
215 | #define PIC_YSEL_LOW_ACC_SHIFT 16 | |
216 | #define PIC_YSEL_LOW_FLASH_SHIFT 24 | |
217 | #define PIC_YSEL_HIGH 0x21 | |
218 | #define PIC_ZSEL_LOW 0x22 | |
219 | #define PIC_ZSEL_HIGH 0x23 | |
220 | #define PIC_IRQM_PRIM 0x24 | |
221 | #define PIC_IRQM_LPC 0x25 | |
222 | #define PIC_XIRR_STS_LOW 0x26 | |
223 | #define PIC_XIRR_STS_HIGH 0x27 | |
224 | #define PCI_SHDW 0x34 | |
22c21003 WZ |
225 | |
226 | /* | |
227 | * DIVIL STANDARD | |
228 | */ | |
70342287 RB |
229 | #define DIVIL_CAP 0x00 |
230 | #define DIVIL_CONFIG 0x01 | |
231 | #define DIVIL_SMI 0x02 | |
232 | #define DIVIL_ERROR 0x03 | |
233 | #define DIVIL_PM 0x04 | |
234 | #define DIVIL_DIAG 0x05 | |
22c21003 WZ |
235 | |
236 | /* | |
237 | * DIVIL SPEC. | |
238 | */ | |
70342287 RB |
239 | #define DIVIL_LBAR_IRQ 0x08 |
240 | #define DIVIL_LBAR_KEL 0x09 | |
241 | #define DIVIL_LBAR_SMB 0x0B | |
242 | #define DIVIL_LBAR_GPIO 0x0C | |
243 | #define DIVIL_LBAR_MFGPT 0x0D | |
244 | #define DIVIL_LBAR_ACPI 0x0E | |
245 | #define DIVIL_LBAR_PMS 0x0F | |
246 | #define DIVIL_LEG_IO 0x14 | |
247 | #define DIVIL_BALL_OPTS 0x15 | |
248 | #define DIVIL_SOFT_IRQ 0x16 | |
249 | #define DIVIL_SOFT_RESET 0x17 | |
22c21003 WZ |
250 | |
251 | /* MFGPT */ | |
252 | #define MFGPT_IRQ 0x28 | |
253 | ||
254 | /* | |
255 | * IDE STANDARD | |
256 | */ | |
70342287 RB |
257 | #define IDE_CAP 0x00 |
258 | #define IDE_CONFIG 0x01 | |
259 | #define IDE_SMI 0x02 | |
260 | #define IDE_ERROR 0x03 | |
261 | #define IDE_PM 0x04 | |
262 | #define IDE_DIAG 0x05 | |
22c21003 WZ |
263 | |
264 | /* | |
265 | * IDE SPEC. | |
266 | */ | |
70342287 RB |
267 | #define IDE_IO_BAR 0x08 |
268 | #define IDE_CFG 0x10 | |
269 | #define IDE_DTC 0x12 | |
270 | #define IDE_CAST 0x13 | |
271 | #define IDE_ETC 0x14 | |
272 | #define IDE_INTERNAL_PM 0x15 | |
22c21003 WZ |
273 | |
274 | /* | |
275 | * ACC STANDARD | |
276 | */ | |
70342287 RB |
277 | #define ACC_CAP 0x00 |
278 | #define ACC_CONFIG 0x01 | |
279 | #define ACC_SMI 0x02 | |
280 | #define ACC_ERROR 0x03 | |
281 | #define ACC_PM 0x04 | |
282 | #define ACC_DIAG 0x05 | |
22c21003 WZ |
283 | |
284 | /* | |
285 | * USB STANDARD | |
286 | */ | |
70342287 RB |
287 | #define USB_CAP 0x00 |
288 | #define USB_CONFIG 0x01 | |
289 | #define USB_SMI 0x02 | |
290 | #define USB_ERROR 0x03 | |
291 | #define USB_PM 0x04 | |
292 | #define USB_DIAG 0x05 | |
22c21003 WZ |
293 | |
294 | /* | |
295 | * USB SPEC. | |
296 | */ | |
70342287 RB |
297 | #define USB_OHCI 0x08 |
298 | #define USB_EHCI 0x09 | |
22c21003 WZ |
299 | |
300 | /****************** NATIVE ***************************/ | |
301 | /* GPIO : I/O SPACE; REG : 32BITS */ | |
70342287 RB |
302 | #define GPIOL_OUT_VAL 0x00 |
303 | #define GPIOL_OUT_EN 0x04 | |
22c21003 WZ |
304 | |
305 | #endif /* _CS5536_H */ |