[mirror_ubuntu-eoan-kernel.git] / arch / mips / include / asm / mach-loongson / loongson.h

/*
 * Copyright (C) 2009 Lemote, Inc.
 * Author: Wu Zhangjin <wuzj@lemote.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */

#ifndef __ASM_MACH_LOONGSON_LOONGSON_H
#define __ASM_MACH_LOONGSON_LOONGSON_H

#include <linux/io.h>
#include <linux/init.h>

/* loongson internal northbridge initialization */
extern void bonito_irq_init(void);

/* machine-specific reboot/halt operation */
extern void mach_prepare_reboot(void);
extern void mach_prepare_shutdown(void);

/* environment arguments from bootloader */
extern unsigned long bus_clock, cpu_clock_freq;
extern unsigned long memsize, highmemsize;

/* loongson-specific command line, env and memory initialization */
extern void __init prom_init_memory(void);
extern void __init prom_init_cmdline(void);
extern void __init prom_init_machtype(void);
extern void __init prom_init_env(void);
extern unsigned long _loongson_uart_base;
extern unsigned long uart8250_base[];
extern void prom_init_uart_base(void);

/* irq operation functions */
extern void bonito_irqdispatch(void);
extern void __init bonito_irq_init(void);
extern void __init set_irq_trigger_mode(void);
extern void __init mach_init_irq(void);
extern void mach_irq_dispatch(unsigned int pending);

/* We need this in some places... */
#define delay()	({		\
	int x;				\
	for (x = 0; x < 100000; x++)	\
		__asm__ __volatile__(""); \
})

#define LOONGSON_REG(x) \
	(*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))

#define LOONGSON_IRQ_BASE	32
#define LOONGSON2_PERFCNT_IRQ	(MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */

#define LOONGSON_FLASH_BASE	0x1c000000
#define LOONGSON_FLASH_SIZE	0x02000000	/* 32M */
#define LOONGSON_FLASH_TOP	(LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)

#define LOONGSON_LIO0_BASE	0x1e000000
#define LOONGSON_LIO0_SIZE	0x01C00000	/* 28M */
#define LOONGSON_LIO0_TOP	(LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1)

#define LOONGSON_BOOT_BASE	0x1fc00000
#define LOONGSON_BOOT_SIZE	0x00100000	/* 1M */
#define LOONGSON_BOOT_TOP 	(LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
#define LOONGSON_REG_BASE 	0x1fe00000
#define LOONGSON_REG_SIZE 	0x00100000	/* 256Bytes + 256Bytes + ??? */
#define LOONGSON_REG_TOP	(LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)

#define LOONGSON_LIO1_BASE 	0x1ff00000
#define LOONGSON_LIO1_SIZE 	0x00100000	/* 1M */
#define LOONGSON_LIO1_TOP	(LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1)

#define LOONGSON_PCILO0_BASE	0x10000000
#define LOONGSON_PCILO1_BASE	0x14000000
#define LOONGSON_PCILO2_BASE	0x18000000
#define LOONGSON_PCILO_BASE	LOONGSON_PCILO0_BASE
#define LOONGSON_PCILO_SIZE	0x0c000000	/* 64M * 3 */
#define LOONGSON_PCILO_TOP	(LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1)

#define LOONGSON_PCICFG_BASE	0x1fe80000
#define LOONGSON_PCICFG_SIZE	0x00000800	/* 2K */
#define LOONGSON_PCICFG_TOP	(LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
#define LOONGSON_PCIIO_BASE	0x1fd00000
#define LOONGSON_PCIIO_SIZE	0x00100000	/* 1M */
#define LOONGSON_PCIIO_TOP	(LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1)

/* Loongson Register Bases */

#define LOONGSON_PCICONFIGBASE	0x00
#define LOONGSON_REGBASE	0x100

/* PCI Configuration Registers */

#define LOONGSON_PCI_REG(x)	LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x))
#define LOONGSON_PCIDID		LOONGSON_PCI_REG(0x00)
#define LOONGSON_PCICMD		LOONGSON_PCI_REG(0x04)
#define LOONGSON_PCICLASS 	LOONGSON_PCI_REG(0x08)
#define LOONGSON_PCILTIMER	LOONGSON_PCI_REG(0x0c)
#define LOONGSON_PCIBASE0 	LOONGSON_PCI_REG(0x10)
#define LOONGSON_PCIBASE1 	LOONGSON_PCI_REG(0x14)
#define LOONGSON_PCIBASE2 	LOONGSON_PCI_REG(0x18)
#define LOONGSON_PCIBASE3 	LOONGSON_PCI_REG(0x1c)
#define LOONGSON_PCIBASE4 	LOONGSON_PCI_REG(0x20)
#define LOONGSON_PCIEXPRBASE	LOONGSON_PCI_REG(0x30)
#define LOONGSON_PCIINT		LOONGSON_PCI_REG(0x3c)

#define LOONGSON_PCI_ISR4C	LOONGSON_PCI_REG(0x4c)

#define LOONGSON_PCICMD_PERR_CLR	0x80000000
#define LOONGSON_PCICMD_SERR_CLR	0x40000000
#define LOONGSON_PCICMD_MABORT_CLR	0x20000000
#define LOONGSON_PCICMD_MTABORT_CLR	0x10000000
#define LOONGSON_PCICMD_TABORT_CLR	0x08000000
#define LOONGSON_PCICMD_MPERR_CLR 	0x01000000
#define LOONGSON_PCICMD_PERRRESPEN	0x00000040
#define LOONGSON_PCICMD_ASTEPEN		0x00000080
#define LOONGSON_PCICMD_SERREN		0x00000100
#define LOONGSON_PCILTIMER_BUSLATENCY	0x0000ff00
#define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT	8

/* Loongson h/w Configuration */

#define LOONGSON_GENCFG_OFFSET		0x4
#define LOONGSON_GENCFG	LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET)

#define LOONGSON_GENCFG_DEBUGMODE	0x00000001
#define LOONGSON_GENCFG_SNOOPEN		0x00000002
#define LOONGSON_GENCFG_CPUSELFRESET	0x00000004

#define LOONGSON_GENCFG_FORCE_IRQA	0x00000008
#define LOONGSON_GENCFG_IRQA_ISOUT	0x00000010
#define LOONGSON_GENCFG_IRQA_FROM_INT1	0x00000020
#define LOONGSON_GENCFG_BYTESWAP	0x00000040

#define LOONGSON_GENCFG_UNCACHED	0x00000080
#define LOONGSON_GENCFG_PREFETCHEN	0x00000100
#define LOONGSON_GENCFG_WBEHINDEN	0x00000200
#define LOONGSON_GENCFG_CACHEALG	0x00000c00
#define LOONGSON_GENCFG_CACHEALG_SHIFT	10
#define LOONGSON_GENCFG_PCIQUEUE	0x00001000
#define LOONGSON_GENCFG_CACHESTOP	0x00002000
#define LOONGSON_GENCFG_MSTRBYTESWAP	0x00004000
#define LOONGSON_GENCFG_BUSERREN	0x00008000
#define LOONGSON_GENCFG_NORETRYTIMEOUT	0x00010000
#define LOONGSON_GENCFG_SHORTCOPYTIMEOUT	0x00020000

/* PCI address map control */

#define LOONGSON_PCIMAP			LOONGSON_REG(LOONGSON_REGBASE + 0x10)
#define LOONGSON_PCIMEMBASECFG		LOONGSON_REG(LOONGSON_REGBASE + 0x14)
#define LOONGSON_PCIMAP_CFG		LOONGSON_REG(LOONGSON_REGBASE + 0x18)

/* GPIO Regs - r/w */

#define LOONGSON_GPIODATA 		LOONGSON_REG(LOONGSON_REGBASE + 0x1c)
#define LOONGSON_GPIOIE			LOONGSON_REG(LOONGSON_REGBASE + 0x20)

/* ICU Configuration Regs - r/w */

#define LOONGSON_INTEDGE		LOONGSON_REG(LOONGSON_REGBASE + 0x24)
#define LOONGSON_INTSTEER 		LOONGSON_REG(LOONGSON_REGBASE + 0x28)
#define LOONGSON_INTPOL			LOONGSON_REG(LOONGSON_REGBASE + 0x2c)

/* ICU Enable Regs - IntEn & IntISR are r/o. */

#define LOONGSON_INTENSET 		LOONGSON_REG(LOONGSON_REGBASE + 0x30)
#define LOONGSON_INTENCLR 		LOONGSON_REG(LOONGSON_REGBASE + 0x34)
#define LOONGSON_INTEN			LOONGSON_REG(LOONGSON_REGBASE + 0x38)
#define LOONGSON_INTISR			LOONGSON_REG(LOONGSON_REGBASE + 0x3c)

/* ICU */
#define LOONGSON_ICU_MBOXES		0x0000000f
#define LOONGSON_ICU_MBOXES_SHIFT 	0
#define LOONGSON_ICU_DMARDY		0x00000010
#define LOONGSON_ICU_DMAEMPTY		0x00000020
#define LOONGSON_ICU_COPYRDY		0x00000040
#define LOONGSON_ICU_COPYEMPTY		0x00000080
#define LOONGSON_ICU_COPYERR		0x00000100
#define LOONGSON_ICU_PCIIRQ		0x00000200
#define LOONGSON_ICU_MASTERERR		0x00000400
#define LOONGSON_ICU_SYSTEMERR		0x00000800
#define LOONGSON_ICU_DRAMPERR		0x00001000
#define LOONGSON_ICU_RETRYERR		0x00002000
#define LOONGSON_ICU_GPIOS		0x01ff0000
#define LOONGSON_ICU_GPIOS_SHIFT		16
#define LOONGSON_ICU_GPINS		0x7e000000
#define LOONGSON_ICU_GPINS_SHIFT		25
#define LOONGSON_ICU_MBOX(N)		(1<<(LOONGSON_ICU_MBOXES_SHIFT+(N)))
#define LOONGSON_ICU_GPIO(N)		(1<<(LOONGSON_ICU_GPIOS_SHIFT+(N)))
#define LOONGSON_ICU_GPIN(N)		(1<<(LOONGSON_ICU_GPINS_SHIFT+(N)))

/* PCI prefetch window base & mask */

#define LOONGSON_MEM_WIN_BASE_L 	LOONGSON_REG(LOONGSON_REGBASE + 0x40)
#define LOONGSON_MEM_WIN_BASE_H 	LOONGSON_REG(LOONGSON_REGBASE + 0x44)
#define LOONGSON_MEM_WIN_MASK_L 	LOONGSON_REG(LOONGSON_REGBASE + 0x48)
#define LOONGSON_MEM_WIN_MASK_H 	LOONGSON_REG(LOONGSON_REGBASE + 0x4c)

/* PCI_Hit*_Sel_* */

#define LOONGSON_PCI_HIT0_SEL_L		LOONGSON_REG(LOONGSON_REGBASE + 0x50)
#define LOONGSON_PCI_HIT0_SEL_H		LOONGSON_REG(LOONGSON_REGBASE + 0x54)
#define LOONGSON_PCI_HIT1_SEL_L		LOONGSON_REG(LOONGSON_REGBASE + 0x58)
#define LOONGSON_PCI_HIT1_SEL_H		LOONGSON_REG(LOONGSON_REGBASE + 0x5c)
#define LOONGSON_PCI_HIT2_SEL_L		LOONGSON_REG(LOONGSON_REGBASE + 0x60)
#define LOONGSON_PCI_HIT2_SEL_H		LOONGSON_REG(LOONGSON_REGBASE + 0x64)

/* PXArb Config & Status */

#define LOONGSON_PXARB_CFG		LOONGSON_REG(LOONGSON_REGBASE + 0x68)
#define LOONGSON_PXARB_STATUS		LOONGSON_REG(LOONGSON_REGBASE + 0x6c)

/* pcimap */

#define LOONGSON_PCIMAP_PCIMAP_LO0	0x0000003f
#define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT	0
#define LOONGSON_PCIMAP_PCIMAP_LO1	0x00000fc0
#define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT	6
#define LOONGSON_PCIMAP_PCIMAP_LO2	0x0003f000
#define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT	12
#define LOONGSON_PCIMAP_PCIMAP_2	0x00040000
#define LOONGSON_PCIMAP_WIN(WIN, ADDR)	\
	((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6))

/* Chip Config */
#ifdef CONFIG_CPU_SUPPORTS_CPUFREQ
#define LOONGSON_CHIPCFG0		LOONGSON_REG(LOONGSON_REGBASE + 0x80)
#endif

/*
 * address windows configuration module
 *
 * loongson2e do not have this module
 */
#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG

/* address window config module base address */
#define LOONGSON_ADDRWINCFG_BASE		0x3ff00000ul
#define LOONGSON_ADDRWINCFG_SIZE		0x180

extern unsigned long _loongson_addrwincfg_base;
#define LOONGSON_ADDRWINCFG(offset) \
	(*(volatile u64 *)(_loongson_addrwincfg_base + (offset)))

#define CPU_WIN0_BASE	LOONGSON_ADDRWINCFG(0x00)
#define CPU_WIN1_BASE	LOONGSON_ADDRWINCFG(0x08)
#define CPU_WIN2_BASE	LOONGSON_ADDRWINCFG(0x10)
#define CPU_WIN3_BASE	LOONGSON_ADDRWINCFG(0x18)

#define CPU_WIN0_MASK	LOONGSON_ADDRWINCFG(0x20)
#define CPU_WIN1_MASK	LOONGSON_ADDRWINCFG(0x28)
#define CPU_WIN2_MASK	LOONGSON_ADDRWINCFG(0x30)
#define CPU_WIN3_MASK	LOONGSON_ADDRWINCFG(0x38)

#define CPU_WIN0_MMAP	LOONGSON_ADDRWINCFG(0x40)
#define CPU_WIN1_MMAP	LOONGSON_ADDRWINCFG(0x48)
#define CPU_WIN2_MMAP	LOONGSON_ADDRWINCFG(0x50)
#define CPU_WIN3_MMAP	LOONGSON_ADDRWINCFG(0x58)

#define PCIDMA_WIN0_BASE	LOONGSON_ADDRWINCFG(0x60)
#define PCIDMA_WIN1_BASE	LOONGSON_ADDRWINCFG(0x68)
#define PCIDMA_WIN2_BASE	LOONGSON_ADDRWINCFG(0x70)
#define PCIDMA_WIN3_BASE	LOONGSON_ADDRWINCFG(0x78)

#define PCIDMA_WIN0_MASK	LOONGSON_ADDRWINCFG(0x80)
#define PCIDMA_WIN1_MASK	LOONGSON_ADDRWINCFG(0x88)
#define PCIDMA_WIN2_MASK	LOONGSON_ADDRWINCFG(0x90)
#define PCIDMA_WIN3_MASK	LOONGSON_ADDRWINCFG(0x98)

#define PCIDMA_WIN0_MMAP	LOONGSON_ADDRWINCFG(0xa0)
#define PCIDMA_WIN1_MMAP	LOONGSON_ADDRWINCFG(0xa8)
#define PCIDMA_WIN2_MMAP	LOONGSON_ADDRWINCFG(0xb0)
#define PCIDMA_WIN3_MMAP	LOONGSON_ADDRWINCFG(0xb8)

#define ADDRWIN_WIN0	0
#define ADDRWIN_WIN1	1
#define ADDRWIN_WIN2	2
#define ADDRWIN_WIN3	3

#define ADDRWIN_MAP_DST_DDR	0
#define ADDRWIN_MAP_DST_PCI	1
#define ADDRWIN_MAP_DST_LIO	1

/*
 * s: CPU, PCIDMA
 * d: DDR, PCI, LIO
 * win: 0, 1, 2, 3
 * src: map source
 * dst: map destination
 * size: ~mask + 1
 */
#define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\
	s##_WIN##w##_BASE = (src); \
	s##_WIN##w##_MMAP = (src) | ADDRWIN_MAP_DST_##d; \
	s##_WIN##w##_MASK = ~(size-1); \
} while (0)

#define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \
	LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size)
#define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \
	LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size)
#define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \
	LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size)

#endif	/* ! CONFIG_CPU_SUPPORTS_ADDRWINCFG */

#endif /* __ASM_MACH_LOONGSON_LOONGSON_H */
Commit	Line	Data
5e983ff6	1	/*
6f7a251a	2	* Copyright (C) 2009 Lemote, Inc.
5e983ff6 WZ	3	* Author: Wu Zhangjin <wuzj@lemote.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License as published by the
	7	* Free Software Foundation; either version 2 of the License, or (at your
	8	* option) any later version.
	9	*
	10	*/
	11
	12	#ifndef __ASM_MACH_LOONGSON_LOONGSON_H
	13	#define __ASM_MACH_LOONGSON_LOONGSON_H
	14
	15	#include <linux/io.h>
	16	#include <linux/init.h>
	17
5e983ff6 WZ	18	/* loongson internal northbridge initialization */
	19	extern void bonito_irq_init(void);
	20
85749d24 WZ	21	/* machine-specific reboot/halt operation */
	22	extern void mach_prepare_reboot(void);
	23	extern void mach_prepare_shutdown(void);
	24
5e983ff6 WZ	25	/* environment arguments from bootloader */
	26	extern unsigned long bus_clock, cpu_clock_freq;
	27	extern unsigned long memsize, highmemsize;
	28
	29	/* loongson-specific command line, env and memory initialization */
	30	extern void __init prom_init_memory(void);
	31	extern void __init prom_init_cmdline(void);
04cfb90a	32	extern void __init prom_init_machtype(void);
5e983ff6	33	extern void __init prom_init_env(void);
a3ed4951 WZ	34	extern unsigned long _loongson_uart_base;
	35	extern unsigned long uart8250_base[];
	36	extern void prom_init_uart_base(void);
5e983ff6	37
85749d24 WZ	38	/* irq operation functions */
	39	extern void bonito_irqdispatch(void);
	40	extern void __init bonito_irq_init(void);
	41	extern void __init set_irq_trigger_mode(void);
	42	extern void __init mach_init_irq(void);
	43	extern void mach_irq_dispatch(unsigned int pending);
	44
2ee98e0f WZ	45	/* We need this in some places... */
	46	#define delay() ({ \
	47	int x; \
	48	for (x = 0; x < 100000; x++) \
	49	__asm__ __volatile__(""); \
	50	})
	51
e2fee572 WZ	52	#define LOONGSON_REG(x) \
	53	((volatile u32 )((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
	54
	55	#define LOONGSON_IRQ_BASE 32
	56	#define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
	57
	58	#define LOONGSON_FLASH_BASE 0x1c000000
	59	#define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
	60	#define LOONGSON_FLASH_TOP (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)
	61
	62	#define LOONGSON_LIO0_BASE 0x1e000000
	63	#define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
	64	#define LOONGSON_LIO0_TOP (LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1)
	65
	66	#define LOONGSON_BOOT_BASE 0x1fc00000
	67	#define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
	68	#define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
	69	#define LOONGSON_REG_BASE 0x1fe00000
	70	#define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
	71	#define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
	72
	73	#define LOONGSON_LIO1_BASE 0x1ff00000
	74	#define LOONGSON_LIO1_SIZE 0x00100000 /* 1M */
	75	#define LOONGSON_LIO1_TOP (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1)
	76
	77	#define LOONGSON_PCILO0_BASE 0x10000000
	78	#define LOONGSON_PCILO1_BASE 0x14000000
	79	#define LOONGSON_PCILO2_BASE 0x18000000
	80	#define LOONGSON_PCILO_BASE LOONGSON_PCILO0_BASE
	81	#define LOONGSON_PCILO_SIZE 0x0c000000 /* 64M * 3 */
	82	#define LOONGSON_PCILO_TOP (LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1)
	83
	84	#define LOONGSON_PCICFG_BASE 0x1fe80000
	85	#define LOONGSON_PCICFG_SIZE 0x00000800 /* 2K */
	86	#define LOONGSON_PCICFG_TOP (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
	87	#define LOONGSON_PCIIO_BASE 0x1fd00000
	88	#define LOONGSON_PCIIO_SIZE 0x00100000 /* 1M */
	89	#define LOONGSON_PCIIO_TOP (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1)
	90
	91	/* Loongson Register Bases */
	92
	93	#define LOONGSON_PCICONFIGBASE 0x00
	94	#define LOONGSON_REGBASE 0x100
	95
f7face03	96	/* PCI Configuration Registers */
e2fee572 WZ	97
	98	#define LOONGSON_PCI_REG(x) LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x))
	99	#define LOONGSON_PCIDID LOONGSON_PCI_REG(0x00)
	100	#define LOONGSON_PCICMD LOONGSON_PCI_REG(0x04)
	101	#define LOONGSON_PCICLASS LOONGSON_PCI_REG(0x08)
	102	#define LOONGSON_PCILTIMER LOONGSON_PCI_REG(0x0c)
	103	#define LOONGSON_PCIBASE0 LOONGSON_PCI_REG(0x10)
	104	#define LOONGSON_PCIBASE1 LOONGSON_PCI_REG(0x14)
	105	#define LOONGSON_PCIBASE2 LOONGSON_PCI_REG(0x18)
	106	#define LOONGSON_PCIBASE3 LOONGSON_PCI_REG(0x1c)
	107	#define LOONGSON_PCIBASE4 LOONGSON_PCI_REG(0x20)
	108	#define LOONGSON_PCIEXPRBASE LOONGSON_PCI_REG(0x30)
	109	#define LOONGSON_PCIINT LOONGSON_PCI_REG(0x3c)
	110
	111	#define LOONGSON_PCI_ISR4C LOONGSON_PCI_REG(0x4c)
	112
	113	#define LOONGSON_PCICMD_PERR_CLR 0x80000000
	114	#define LOONGSON_PCICMD_SERR_CLR 0x40000000
	115	#define LOONGSON_PCICMD_MABORT_CLR 0x20000000
	116	#define LOONGSON_PCICMD_MTABORT_CLR 0x10000000
	117	#define LOONGSON_PCICMD_TABORT_CLR 0x08000000
	118	#define LOONGSON_PCICMD_MPERR_CLR 0x01000000
	119	#define LOONGSON_PCICMD_PERRRESPEN 0x00000040
	120	#define LOONGSON_PCICMD_ASTEPEN 0x00000080
	121	#define LOONGSON_PCICMD_SERREN 0x00000100
	122	#define LOONGSON_PCILTIMER_BUSLATENCY 0x0000ff00
	123	#define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT 8
	124
	125	/* Loongson h/w Configuration */
	126
	127	#define LOONGSON_GENCFG_OFFSET 0x4
	128	#define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET)
	129
	130	#define LOONGSON_GENCFG_DEBUGMODE 0x00000001
	131	#define LOONGSON_GENCFG_SNOOPEN 0x00000002
	132	#define LOONGSON_GENCFG_CPUSELFRESET 0x00000004
	133
	134	#define LOONGSON_GENCFG_FORCE_IRQA 0x00000008
	135	#define LOONGSON_GENCFG_IRQA_ISOUT 0x00000010
	136	#define LOONGSON_GENCFG_IRQA_FROM_INT1 0x00000020
	137	#define LOONGSON_GENCFG_BYTESWAP 0x00000040
	138
	139	#define LOONGSON_GENCFG_UNCACHED 0x00000080
	140	#define LOONGSON_GENCFG_PREFETCHEN 0x00000100
	141	#define LOONGSON_GENCFG_WBEHINDEN 0x00000200
	142	#define LOONGSON_GENCFG_CACHEALG 0x00000c00
	143	#define LOONGSON_GENCFG_CACHEALG_SHIFT 10
	144	#define LOONGSON_GENCFG_PCIQUEUE 0x00001000
	145	#define LOONGSON_GENCFG_CACHESTOP 0x00002000
	146	#define LOONGSON_GENCFG_MSTRBYTESWAP 0x00004000
	147	#define LOONGSON_GENCFG_BUSERREN 0x00008000
	148	#define LOONGSON_GENCFG_NORETRYTIMEOUT 0x00010000
	149	#define LOONGSON_GENCFG_SHORTCOPYTIMEOUT 0x00020000
	150
	151	/* PCI address map control */
	152
	153	#define LOONGSON_PCIMAP LOONGSON_REG(LOONGSON_REGBASE + 0x10)
	154	#define LOONGSON_PCIMEMBASECFG LOONGSON_REG(LOONGSON_REGBASE + 0x14)
	155	#define LOONGSON_PCIMAP_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x18)
	156
	157	/* GPIO Regs - r/w */
	158
	159	#define LOONGSON_GPIODATA LOONGSON_REG(LOONGSON_REGBASE + 0x1c)
	160	#define LOONGSON_GPIOIE LOONGSON_REG(LOONGSON_REGBASE + 0x20)
161
162	/* ICU Configuration Regs - r/w */
163
164	#define LOONGSON_INTEDGE LOONGSON_REG(LOONGSON_REGBASE + 0x24)
165	#define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28)
166	#define LOONGSON_INTPOL LOONGSON_REG(LOONGSON_REGBASE + 0x2c)
167
168	/* ICU Enable Regs - IntEn & IntISR are r/o. */
169
170	#define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30)
171	#define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34)
172	#define LOONGSON_INTEN LOONGSON_REG(LOONGSON_REGBASE + 0x38)
173	#define LOONGSON_INTISR LOONGSON_REG(LOONGSON_REGBASE + 0x3c)
174
175	/* ICU */
176	#define LOONGSON_ICU_MBOXES 0x0000000f
177	#define LOONGSON_ICU_MBOXES_SHIFT 0
178	#define LOONGSON_ICU_DMARDY 0x00000010
179	#define LOONGSON_ICU_DMAEMPTY 0x00000020
180	#define LOONGSON_ICU_COPYRDY 0x00000040
181	#define LOONGSON_ICU_COPYEMPTY 0x00000080
182	#define LOONGSON_ICU_COPYERR 0x00000100
183	#define LOONGSON_ICU_PCIIRQ 0x00000200
184	#define LOONGSON_ICU_MASTERERR 0x00000400
185	#define LOONGSON_ICU_SYSTEMERR 0x00000800
186	#define LOONGSON_ICU_DRAMPERR 0x00001000
187	#define LOONGSON_ICU_RETRYERR 0x00002000
188	#define LOONGSON_ICU_GPIOS 0x01ff0000
189	#define LOONGSON_ICU_GPIOS_SHIFT 16
190	#define LOONGSON_ICU_GPINS 0x7e000000
191	#define LOONGSON_ICU_GPINS_SHIFT 25
192	#define LOONGSON_ICU_MBOX(N) (1<<(LOONGSON_ICU_MBOXES_SHIFT+(N)))
193	#define LOONGSON_ICU_GPIO(N) (1<<(LOONGSON_ICU_GPIOS_SHIFT+(N)))
194	#define LOONGSON_ICU_GPIN(N) (1<<(LOONGSON_ICU_GPINS_SHIFT+(N)))
195
196	/* PCI prefetch window base & mask */
197
198	#define LOONGSON_MEM_WIN_BASE_L LOONGSON_REG(LOONGSON_REGBASE + 0x40)
199	#define LOONGSON_MEM_WIN_BASE_H LOONGSON_REG(LOONGSON_REGBASE + 0x44)
200	#define LOONGSON_MEM_WIN_MASK_L LOONGSON_REG(LOONGSON_REGBASE + 0x48)
201	#define LOONGSON_MEM_WIN_MASK_H LOONGSON_REG(LOONGSON_REGBASE + 0x4c)
f7face03 WZ	202
	203	/* PCI_Hit_Sel_ */
	204
e2fee572 WZ	205	#define LOONGSON_PCI_HIT0_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x50)
	206	#define LOONGSON_PCI_HIT0_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x54)
	207	#define LOONGSON_PCI_HIT1_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x58)
	208	#define LOONGSON_PCI_HIT1_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x5c)
	209	#define LOONGSON_PCI_HIT2_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x60)
	210	#define LOONGSON_PCI_HIT2_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x64)
f7face03 WZ	211
	212	/* PXArb Config & Status */
	213
e2fee572 WZ	214	#define LOONGSON_PXARB_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x68)
	215	#define LOONGSON_PXARB_STATUS LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
	216
	217	/* pcimap */
f7face03	218
e2fee572 WZ	219	#define LOONGSON_PCIMAP_PCIMAP_LO0 0x0000003f
	220	#define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT 0
	221	#define LOONGSON_PCIMAP_PCIMAP_LO1 0x00000fc0
	222	#define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT 6
	223	#define LOONGSON_PCIMAP_PCIMAP_LO2 0x0003f000
	224	#define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT 12
	225	#define LOONGSON_PCIMAP_PCIMAP_2 0x00040000
	226	#define LOONGSON_PCIMAP_WIN(WIN, ADDR) \
	227	((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
67b35e5d	228
6f7a251a	229	/* Chip Config */
55045ff5	230	#ifdef CONFIG_CPU_SUPPORTS_CPUFREQ
6f7a251a WZ	231	#define LOONGSON_CHIPCFG0 LOONGSON_REG(LOONGSON_REGBASE + 0x80)
	232	#endif
	233
	234	/*
	235	* address windows configuration module
	236	*
	237	* loongson2e do not have this module
	238	*/
55045ff5	239	#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
6f7a251a WZ	240
	241	/* address window config module base address */
	242	#define LOONGSON_ADDRWINCFG_BASE 0x3ff00000ul
	243	#define LOONGSON_ADDRWINCFG_SIZE 0x180
	244
	245	extern unsigned long _loongson_addrwincfg_base;
	246	#define LOONGSON_ADDRWINCFG(offset) \
	247	((volatile u64 )(_loongson_addrwincfg_base + (offset)))
	248
	249	#define CPU_WIN0_BASE LOONGSON_ADDRWINCFG(0x00)
	250	#define CPU_WIN1_BASE LOONGSON_ADDRWINCFG(0x08)
	251	#define CPU_WIN2_BASE LOONGSON_ADDRWINCFG(0x10)
	252	#define CPU_WIN3_BASE LOONGSON_ADDRWINCFG(0x18)
	253
	254	#define CPU_WIN0_MASK LOONGSON_ADDRWINCFG(0x20)
	255	#define CPU_WIN1_MASK LOONGSON_ADDRWINCFG(0x28)
	256	#define CPU_WIN2_MASK LOONGSON_ADDRWINCFG(0x30)
	257	#define CPU_WIN3_MASK LOONGSON_ADDRWINCFG(0x38)
	258
	259	#define CPU_WIN0_MMAP LOONGSON_ADDRWINCFG(0x40)
	260	#define CPU_WIN1_MMAP LOONGSON_ADDRWINCFG(0x48)
	261	#define CPU_WIN2_MMAP LOONGSON_ADDRWINCFG(0x50)
	262	#define CPU_WIN3_MMAP LOONGSON_ADDRWINCFG(0x58)
	263
	264	#define PCIDMA_WIN0_BASE LOONGSON_ADDRWINCFG(0x60)
	265	#define PCIDMA_WIN1_BASE LOONGSON_ADDRWINCFG(0x68)
	266	#define PCIDMA_WIN2_BASE LOONGSON_ADDRWINCFG(0x70)
	267	#define PCIDMA_WIN3_BASE LOONGSON_ADDRWINCFG(0x78)
	268
	269	#define PCIDMA_WIN0_MASK LOONGSON_ADDRWINCFG(0x80)
	270	#define PCIDMA_WIN1_MASK LOONGSON_ADDRWINCFG(0x88)
	271	#define PCIDMA_WIN2_MASK LOONGSON_ADDRWINCFG(0x90)
	272	#define PCIDMA_WIN3_MASK LOONGSON_ADDRWINCFG(0x98)
	273
	274	#define PCIDMA_WIN0_MMAP LOONGSON_ADDRWINCFG(0xa0)
	275	#define PCIDMA_WIN1_MMAP LOONGSON_ADDRWINCFG(0xa8)
	276	#define PCIDMA_WIN2_MMAP LOONGSON_ADDRWINCFG(0xb0)
	277	#define PCIDMA_WIN3_MMAP LOONGSON_ADDRWINCFG(0xb8)
	278
	279	#define ADDRWIN_WIN0 0
	280	#define ADDRWIN_WIN1 1
	281	#define ADDRWIN_WIN2 2
	282	#define ADDRWIN_WIN3 3
	283
	284	#define ADDRWIN_MAP_DST_DDR 0
	285	#define ADDRWIN_MAP_DST_PCI 1
	286	#define ADDRWIN_MAP_DST_LIO 1
	287
	288	/*
	289	* s: CPU, PCIDMA
	290	* d: DDR, PCI, LIO
	291	* win: 0, 1, 2, 3
	292	* src: map source
	293	* dst: map destination
	294	* size: ~mask + 1
	295	*/
	296	#define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\
	297	s##_WIN##w##_BASE = (src); \
	298	s##_WIN##w##_MMAP = (src) \| ADDRWIN_MAP_DST_##d; \
	299	s##_WIN##w##_MASK = ~(size-1); \
	300	} while (0)
	301
	302	#define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \
	303	LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size)
304	#define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \
305	LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size)
306	#define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \
307	LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size)
308
55045ff5	309	#endif /* ! CONFIG_CPU_SUPPORTS_ADDRWINCFG */
6f7a251a	310
5e983ff6	311	#endif /* __ASM_MACH_LOONGSON_LOONGSON_H */