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80fb55a9 JC |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify it | |
3 | * under the terms of the GNU General Public License version 2 as published | |
4 | * by the Free Software Foundation. | |
5 | * | |
6 | * Parts of this file are based on Ralink's 2.6.21 BSP | |
7 | * | |
8 | * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> | |
9 | * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> | |
10 | * Copyright (C) 2013 John Crispin <blogic@openwrt.org> | |
11 | */ | |
12 | ||
13 | #ifndef _RT288X_REGS_H_ | |
14 | #define _RT288X_REGS_H_ | |
15 | ||
16 | #define RT2880_SYSC_BASE 0x00300000 | |
17 | ||
18 | #define SYSC_REG_CHIP_NAME0 0x00 | |
19 | #define SYSC_REG_CHIP_NAME1 0x04 | |
20 | #define SYSC_REG_CHIP_ID 0x0c | |
21 | #define SYSC_REG_SYSTEM_CONFIG 0x10 | |
22 | #define SYSC_REG_CLKCFG 0x30 | |
23 | ||
24 | #define RT2880_CHIP_NAME0 0x38325452 | |
25 | #define RT2880_CHIP_NAME1 0x20203038 | |
26 | ||
27 | #define CHIP_ID_ID_MASK 0xff | |
28 | #define CHIP_ID_ID_SHIFT 8 | |
29 | #define CHIP_ID_REV_MASK 0xff | |
30 | ||
31 | #define SYSTEM_CONFIG_CPUCLK_SHIFT 20 | |
32 | #define SYSTEM_CONFIG_CPUCLK_MASK 0x3 | |
33 | #define SYSTEM_CONFIG_CPUCLK_250 0x0 | |
34 | #define SYSTEM_CONFIG_CPUCLK_266 0x1 | |
35 | #define SYSTEM_CONFIG_CPUCLK_280 0x2 | |
36 | #define SYSTEM_CONFIG_CPUCLK_300 0x3 | |
37 | ||
38 | #define RT2880_GPIO_MODE_I2C BIT(0) | |
39 | #define RT2880_GPIO_MODE_UART0 BIT(1) | |
40 | #define RT2880_GPIO_MODE_SPI BIT(2) | |
41 | #define RT2880_GPIO_MODE_UART1 BIT(3) | |
42 | #define RT2880_GPIO_MODE_JTAG BIT(4) | |
43 | #define RT2880_GPIO_MODE_MDIO BIT(5) | |
44 | #define RT2880_GPIO_MODE_SDRAM BIT(6) | |
45 | #define RT2880_GPIO_MODE_PCI BIT(7) | |
46 | ||
47 | #define CLKCFG_SRAM_CS_N_WDT BIT(9) | |
48 | ||
38d5b81c JC |
49 | #define RT2880_SDRAM_BASE 0x08000000 |
50 | #define RT2880_MEM_SIZE_MIN 2 | |
51 | #define RT2880_MEM_SIZE_MAX 128 | |
52 | ||
80fb55a9 | 53 | #endif |