[mirror_ubuntu-eoan-kernel.git] / arch / mips / include / asm / mips-cm.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * Copyright (C) 2013 Imagination Technologies
 * Author: Paul Burton <paul.burton@mips.com>
 */

#ifndef __MIPS_ASM_MIPS_CPS_H__
# error Please include asm/mips-cps.h rather than asm/mips-cm.h
#endif

#ifndef __MIPS_ASM_MIPS_CM_H__
#define __MIPS_ASM_MIPS_CM_H__

#include <linux/bitops.h>
#include <linux/errno.h>

/* The base address of the CM GCR block */
extern void __iomem *mips_gcr_base;

/* The base address of the CM L2-only sync region */
extern void __iomem *mips_cm_l2sync_base;

/**
 * __mips_cm_phys_base - retrieve the physical base address of the CM
 *
 * This function returns the physical base address of the Coherence Manager
 * global control block, or 0 if no Coherence Manager is present. It provides
 * a default implementation which reads the CMGCRBase register where available,
 * and may be overridden by platforms which determine this address in a
 * different way by defining a function with the same prototype except for the
 * name mips_cm_phys_base (without underscores).
 */
extern phys_addr_t __mips_cm_phys_base(void);

/*
 * mips_cm_is64 - determine CM register width
 *
 * The CM register width is determined by the version of the CM, with CM3
 * introducing 64 bit GCRs and all prior CM versions having 32 bit GCRs.
 * However we may run a kernel built for MIPS32 on a system with 64 bit GCRs,
 * or vice-versa. This variable indicates the width of the memory accesses
 * that the kernel will perform to GCRs, which may differ from the actual
 * width of the GCRs.
 *
 * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.
 */
extern int mips_cm_is64;

/**
 * mips_cm_error_report - Report CM cache errors
 */
#ifdef CONFIG_MIPS_CM
extern void mips_cm_error_report(void);
#else
static inline void mips_cm_error_report(void) {}
#endif

/**
 * mips_cm_probe - probe for a Coherence Manager
 *
 * Attempt to detect the presence of a Coherence Manager. Returns 0 if a CM
 * is successfully detected, else -errno.
 */
#ifdef CONFIG_MIPS_CM
extern int mips_cm_probe(void);
#else
static inline int mips_cm_probe(void)
{
	return -ENODEV;
}
#endif

/**
 * mips_cm_present - determine whether a Coherence Manager is present
 *
 * Returns true if a CM is present in the system, else false.
 */
static inline bool mips_cm_present(void)
{
#ifdef CONFIG_MIPS_CM
	return mips_gcr_base != NULL;
#else
	return false;
#endif
}

/**
 * mips_cm_has_l2sync - determine whether an L2-only sync region is present
 *
 * Returns true if the system implements an L2-only sync region, else false.
 */
static inline bool mips_cm_has_l2sync(void)
{
#ifdef CONFIG_MIPS_CM
	return mips_cm_l2sync_base != NULL;
#else
	return false;
#endif
}

/* Offsets to register blocks from the CM base address */
#define MIPS_CM_GCB_OFS		0x0000 /* Global Control Block */
#define MIPS_CM_CLCB_OFS	0x2000 /* Core Local Control Block */
#define MIPS_CM_COCB_OFS	0x4000 /* Core Other Control Block */
#define MIPS_CM_GDB_OFS		0x6000 /* Global Debug Block */

/* Total size of the CM memory mapped registers */
#define MIPS_CM_GCR_SIZE	0x8000

/* Size of the L2-only sync region */
#define MIPS_CM_L2SYNC_SIZE	0x1000

#define GCR_ACCESSOR_RO(sz, off, name)					\
	CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_GCB_OFS + off, name)		\
	CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, redir_##name)

#define GCR_ACCESSOR_RW(sz, off, name)					\
	CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_GCB_OFS + off, name)		\
	CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_COCB_OFS + off, redir_##name)

#define GCR_CX_ACCESSOR_RO(sz, off, name)				\
	CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name)	\
	CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name)

#define GCR_CX_ACCESSOR_RW(sz, off, name)				\
	CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name)	\
	CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name)

/* GCR_CONFIG - Information about the system */
GCR_ACCESSOR_RO(64, 0x000, config)
#define CM_GCR_CONFIG_CLUSTER_COH_CAPABLE	BIT_ULL(43)
#define CM_GCR_CONFIG_CLUSTER_ID		GENMASK_ULL(39, 32)
#define CM_GCR_CONFIG_NUM_CLUSTERS		GENMASK(29, 23)
#define CM_GCR_CONFIG_NUMIOCU			GENMASK(15, 8)
#define CM_GCR_CONFIG_PCORES			GENMASK(7, 0)

/* GCR_BASE - Base address of the Global Configuration Registers (GCRs) */
GCR_ACCESSOR_RW(64, 0x008, base)
#define CM_GCR_BASE_GCRBASE			GENMASK_ULL(47, 15)
#define CM_GCR_BASE_CMDEFTGT			GENMASK(1, 0)
#define  CM_GCR_BASE_CMDEFTGT_MEM		0
#define  CM_GCR_BASE_CMDEFTGT_RESERVED		1
#define  CM_GCR_BASE_CMDEFTGT_IOCU0		2
#define  CM_GCR_BASE_CMDEFTGT_IOCU1		3

/* GCR_ACCESS - Controls core/IOCU access to GCRs */
GCR_ACCESSOR_RW(32, 0x020, access)
#define CM_GCR_ACCESS_ACCESSEN			GENMASK(7, 0)

/* GCR_REV - Indicates the Coherence Manager revision */
GCR_ACCESSOR_RO(32, 0x030, rev)
#define CM_GCR_REV_MAJOR			GENMASK(15, 8)
#define CM_GCR_REV_MINOR			GENMASK(7, 0)

#define CM_ENCODE_REV(major, minor) \
		(((major) << __ffs(CM_GCR_REV_MAJOR)) | \
		 ((minor) << __ffs(CM_GCR_REV_MINOR)))

#define CM_REV_CM2				CM_ENCODE_REV(6, 0)
#define CM_REV_CM2_5				CM_ENCODE_REV(7, 0)
#define CM_REV_CM3				CM_ENCODE_REV(8, 0)
#define CM_REV_CM3_5				CM_ENCODE_REV(9, 0)

/* GCR_ERR_CONTROL - Control error checking logic */
GCR_ACCESSOR_RW(32, 0x038, err_control)
#define CM_GCR_ERR_CONTROL_L2_ECC_EN		BIT(1)
#define CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT	BIT(0)

/* GCR_ERR_MASK - Control which errors are reported as interrupts */
GCR_ACCESSOR_RW(64, 0x040, error_mask)

/* GCR_ERR_CAUSE - Indicates the type of error that occurred */
GCR_ACCESSOR_RW(64, 0x048, error_cause)
#define CM_GCR_ERROR_CAUSE_ERRTYPE		GENMASK(31, 27)
#define CM3_GCR_ERROR_CAUSE_ERRTYPE		GENMASK_ULL(63, 58)
#define CM_GCR_ERROR_CAUSE_ERRINFO		GENMASK(26, 0)

/* GCR_ERR_ADDR - Indicates the address associated with an error */
GCR_ACCESSOR_RW(64, 0x050, error_addr)

/* GCR_ERR_MULT - Indicates when multiple errors have occurred */
GCR_ACCESSOR_RW(64, 0x058, error_mult)
#define CM_GCR_ERROR_MULT_ERR2ND		GENMASK(4, 0)

/* GCR_L2_ONLY_SYNC_BASE - Base address of the L2 cache-only sync region */
GCR_ACCESSOR_RW(64, 0x070, l2_only_sync_base)
#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE	GENMASK(31, 12)
#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN		BIT(0)

/* GCR_GIC_BASE - Base address of the Global Interrupt Controller (GIC) */
GCR_ACCESSOR_RW(64, 0x080, gic_base)
#define CM_GCR_GIC_BASE_GICBASE			GENMASK(31, 17)
#define CM_GCR_GIC_BASE_GICEN			BIT(0)

/* GCR_CPC_BASE - Base address of the Cluster Power Controller (CPC) */
GCR_ACCESSOR_RW(64, 0x088, cpc_base)
#define CM_GCR_CPC_BASE_CPCBASE			GENMASK(31, 15)
#define CM_GCR_CPC_BASE_CPCEN			BIT(0)

/* GCR_REGn_BASE - Base addresses of CM address regions */
GCR_ACCESSOR_RW(64, 0x090, reg0_base)
GCR_ACCESSOR_RW(64, 0x0a0, reg1_base)
GCR_ACCESSOR_RW(64, 0x0b0, reg2_base)
GCR_ACCESSOR_RW(64, 0x0c0, reg3_base)
#define CM_GCR_REGn_BASE_BASEADDR		GENMASK(31, 16)

/* GCR_REGn_MASK - Size & destination of CM address regions */
GCR_ACCESSOR_RW(64, 0x098, reg0_mask)
GCR_ACCESSOR_RW(64, 0x0a8, reg1_mask)
GCR_ACCESSOR_RW(64, 0x0b8, reg2_mask)
GCR_ACCESSOR_RW(64, 0x0c8, reg3_mask)
#define CM_GCR_REGn_MASK_ADDRMASK		GENMASK(31, 16)
#define CM_GCR_REGn_MASK_CCAOVR			GENMASK(7, 5)
#define CM_GCR_REGn_MASK_CCAOVREN		BIT(4)
#define CM_GCR_REGn_MASK_DROPL2			BIT(2)
#define CM_GCR_REGn_MASK_CMTGT			GENMASK(1, 0)
#define  CM_GCR_REGn_MASK_CMTGT_DISABLED	0x0
#define  CM_GCR_REGn_MASK_CMTGT_MEM		0x1
#define  CM_GCR_REGn_MASK_CMTGT_IOCU0		0x2
#define  CM_GCR_REGn_MASK_CMTGT_IOCU1		0x3

/* GCR_GIC_STATUS - Indicates presence of a Global Interrupt Controller (GIC) */
GCR_ACCESSOR_RO(32, 0x0d0, gic_status)
#define CM_GCR_GIC_STATUS_EX			BIT(0)

/* GCR_CPC_STATUS - Indicates presence of a Cluster Power Controller (CPC) */
GCR_ACCESSOR_RO(32, 0x0f0, cpc_status)
#define CM_GCR_CPC_STATUS_EX			BIT(0)

/* GCR_L2_CONFIG - Indicates L2 cache configuration when Config5.L2C=1 */
GCR_ACCESSOR_RW(32, 0x130, l2_config)
#define CM_GCR_L2_CONFIG_BYPASS			BIT(20)
#define CM_GCR_L2_CONFIG_SET_SIZE		GENMASK(15, 12)
#define CM_GCR_L2_CONFIG_LINE_SIZE		GENMASK(11, 8)
#define CM_GCR_L2_CONFIG_ASSOC			GENMASK(7, 0)

/* GCR_SYS_CONFIG2 - Further information about the system */
GCR_ACCESSOR_RO(32, 0x150, sys_config2)
#define CM_GCR_SYS_CONFIG2_MAXVPW		GENMASK(3, 0)

/* GCR_L2_PFT_CONTROL - Controls hardware L2 prefetching */
GCR_ACCESSOR_RW(32, 0x300, l2_pft_control)
#define CM_GCR_L2_PFT_CONTROL_PAGEMASK		GENMASK(31, 12)
#define CM_GCR_L2_PFT_CONTROL_PFTEN		BIT(8)
#define CM_GCR_L2_PFT_CONTROL_NPFT		GENMASK(7, 0)

/* GCR_L2_PFT_CONTROL_B - Controls hardware L2 prefetching */
GCR_ACCESSOR_RW(32, 0x308, l2_pft_control_b)
#define CM_GCR_L2_PFT_CONTROL_B_CEN		BIT(8)
#define CM_GCR_L2_PFT_CONTROL_B_PORTID		GENMASK(7, 0)

/* GCR_L2SM_COP - L2 cache op state machine control */
GCR_ACCESSOR_RW(32, 0x620, l2sm_cop)
#define CM_GCR_L2SM_COP_PRESENT			BIT(31)
#define CM_GCR_L2SM_COP_RESULT			GENMASK(8, 6)
#define  CM_GCR_L2SM_COP_RESULT_DONTCARE	0
#define  CM_GCR_L2SM_COP_RESULT_DONE_OK		1
#define  CM_GCR_L2SM_COP_RESULT_DONE_ERROR	2
#define  CM_GCR_L2SM_COP_RESULT_ABORT_OK	3
#define  CM_GCR_L2SM_COP_RESULT_ABORT_ERROR	4
#define CM_GCR_L2SM_COP_RUNNING			BIT(5)
#define CM_GCR_L2SM_COP_TYPE			GENMASK(4, 2)
#define  CM_GCR_L2SM_COP_TYPE_IDX_WBINV		0
#define  CM_GCR_L2SM_COP_TYPE_IDX_STORETAG	1
#define  CM_GCR_L2SM_COP_TYPE_IDX_STORETAGDATA	2
#define  CM_GCR_L2SM_COP_TYPE_HIT_INV		4
#define  CM_GCR_L2SM_COP_TYPE_HIT_WBINV		5
#define  CM_GCR_L2SM_COP_TYPE_HIT_WB		6
#define  CM_GCR_L2SM_COP_TYPE_FETCHLOCK		7
#define CM_GCR_L2SM_COP_CMD			GENMASK(1, 0)
#define  CM_GCR_L2SM_COP_CMD_START		1	/* only when idle */
#define  CM_GCR_L2SM_COP_CMD_ABORT		3	/* only when running */

/* GCR_L2SM_TAG_ADDR_COP - L2 cache op state machine address control */
GCR_ACCESSOR_RW(64, 0x628, l2sm_tag_addr_cop)
#define CM_GCR_L2SM_TAG_ADDR_COP_NUM_LINES	GENMASK_ULL(63, 48)
#define CM_GCR_L2SM_TAG_ADDR_COP_START_TAG	GENMASK_ULL(47, 6)

/* GCR_BEV_BASE - Controls the location of the BEV for powered up cores */
GCR_ACCESSOR_RW(64, 0x680, bev_base)

/* GCR_Cx_RESET_RELEASE - Controls core reset for CM 1.x */
GCR_CX_ACCESSOR_RW(32, 0x000, reset_release)

/* GCR_Cx_COHERENCE - Controls core coherence */
GCR_CX_ACCESSOR_RW(32, 0x008, coherence)
#define CM_GCR_Cx_COHERENCE_COHDOMAINEN		GENMASK(7, 0)
#define CM3_GCR_Cx_COHERENCE_COHEN		BIT(0)

/* GCR_Cx_CONFIG - Information about a core's configuration */
GCR_CX_ACCESSOR_RO(32, 0x010, config)
#define CM_GCR_Cx_CONFIG_IOCUTYPE		GENMASK(11, 10)
#define CM_GCR_Cx_CONFIG_PVPE			GENMASK(9, 0)

/* GCR_Cx_OTHER - Configure the core-other/redirect GCR block */
GCR_CX_ACCESSOR_RW(32, 0x018, other)
#define CM_GCR_Cx_OTHER_CORENUM			GENMASK(31, 16)	/* CM < 3 */
#define CM_GCR_Cx_OTHER_CLUSTER_EN		BIT(31)		/* CM >= 3.5 */
#define CM_GCR_Cx_OTHER_GIC_EN			BIT(30)		/* CM >= 3.5 */
#define CM_GCR_Cx_OTHER_BLOCK			GENMASK(25, 24)	/* CM >= 3.5 */
#define  CM_GCR_Cx_OTHER_BLOCK_LOCAL		0
#define  CM_GCR_Cx_OTHER_BLOCK_GLOBAL		1
#define  CM_GCR_Cx_OTHER_BLOCK_USER		2
#define  CM_GCR_Cx_OTHER_BLOCK_GLOBAL_HIGH	3
#define CM_GCR_Cx_OTHER_CLUSTER			GENMASK(21, 16)	/* CM >= 3.5 */
#define CM3_GCR_Cx_OTHER_CORE			GENMASK(13, 8)	/* CM >= 3 */
#define  CM_GCR_Cx_OTHER_CORE_CM		32
#define CM3_GCR_Cx_OTHER_VP			GENMASK(2, 0)	/* CM >= 3 */

/* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */
GCR_CX_ACCESSOR_RW(32, 0x020, reset_base)
#define CM_GCR_Cx_RESET_BASE_BEVEXCBASE		GENMASK(31, 12)

/* GCR_Cx_ID - Identify the current core */
GCR_CX_ACCESSOR_RO(32, 0x028, id)
#define CM_GCR_Cx_ID_CLUSTER			GENMASK(15, 8)
#define CM_GCR_Cx_ID_CORE			GENMASK(7, 0)

/* GCR_Cx_RESET_EXT_BASE - Configure behaviour when cores reset or power up */
GCR_CX_ACCESSOR_RW(32, 0x030, reset_ext_base)
#define CM_GCR_Cx_RESET_EXT_BASE_EVARESET	BIT(31)
#define CM_GCR_Cx_RESET_EXT_BASE_UEB		BIT(30)
#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK	GENMASK(27, 20)
#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA	GENMASK(7, 1)
#define CM_GCR_Cx_RESET_EXT_BASE_PRESENT	BIT(0)

/**
 * mips_cm_l2sync - perform an L2-only sync operation
 *
 * If an L2-only sync region is present in the system then this function
 * performs and L2-only sync and returns zero. Otherwise it returns -ENODEV.
 */
static inline int mips_cm_l2sync(void)
{
	if (!mips_cm_has_l2sync())
		return -ENODEV;

	writel(0, mips_cm_l2sync_base);
	return 0;
}

/**
 * mips_cm_revision() - return CM revision
 *
 * Return: The revision of the CM, from GCR_REV, or 0 if no CM is present. The
 * return value should be checked against the CM_REV_* macros.
 */
static inline int mips_cm_revision(void)
{
	if (!mips_cm_present())
		return 0;

	return read_gcr_rev();
}

/**
 * mips_cm_max_vp_width() - return the width in bits of VP indices
 *
 * Return: the width, in bits, of VP indices in fields that combine core & VP
 * indices.
 */
static inline unsigned int mips_cm_max_vp_width(void)
{
	extern int smp_num_siblings;
	uint32_t cfg;

	if (mips_cm_revision() >= CM_REV_CM3)
		return read_gcr_sys_config2() & CM_GCR_SYS_CONFIG2_MAXVPW;

	if (mips_cm_present()) {
		/*
		 * We presume that all cores in the system will have the same
		 * number of VP(E)s, and if that ever changes then this will
		 * need revisiting.
		 */
		cfg = read_gcr_cl_config() & CM_GCR_Cx_CONFIG_PVPE;
		return (cfg >> __ffs(CM_GCR_Cx_CONFIG_PVPE)) + 1;
	}

	if (IS_ENABLED(CONFIG_SMP))
		return smp_num_siblings;

	return 1;
}

/**
 * mips_cm_vp_id() - calculate the hardware VP ID for a CPU
 * @cpu: the CPU whose VP ID to calculate
 *
 * Hardware such as the GIC uses identifiers for VPs which may not match the
 * CPU numbers used by Linux. This function calculates the hardware VP
 * identifier corresponding to a given CPU.
 *
 * Return: the VP ID for the CPU.
 */
static inline unsigned int mips_cm_vp_id(unsigned int cpu)
{
	unsigned int core = cpu_core(&cpu_data[cpu]);
	unsigned int vp = cpu_vpe_id(&cpu_data[cpu]);

	return (core * mips_cm_max_vp_width()) + vp;
}

#ifdef CONFIG_MIPS_CM

/**
 * mips_cm_lock_other - lock access to redirect/other region
 * @cluster: the other cluster to be accessed
 * @core: the other core to be accessed
 * @vp: the VP within the other core to be accessed
 * @block: the register block to be accessed
 *
 * Configure the redirect/other region for the local core/VP (depending upon
 * the CM revision) to target the specified @cluster, @core, @vp & register
 * @block. Must be called before using the redirect/other region, and followed
 * by a call to mips_cm_unlock_other() when access to the redirect/other region
 * is complete.
 *
 * This function acquires a spinlock such that code between it &
 * mips_cm_unlock_other() calls cannot be pre-empted by anything which may
 * reconfigure the redirect/other region, and cannot be interfered with by
 * another VP in the core. As such calls to this function should not be nested.
 */
extern void mips_cm_lock_other(unsigned int cluster, unsigned int core,
			       unsigned int vp, unsigned int block);

/**
 * mips_cm_unlock_other - unlock access to redirect/other region
 *
 * Must be called after mips_cm_lock_other() once all required access to the
 * redirect/other region has been completed.
 */
extern void mips_cm_unlock_other(void);

#else /* !CONFIG_MIPS_CM */

static inline void mips_cm_lock_other(unsigned int cluster, unsigned int core,
				      unsigned int vp, unsigned int block) { }
static inline void mips_cm_unlock_other(void) { }

#endif /* !CONFIG_MIPS_CM */

/**
 * mips_cm_lock_other_cpu - lock access to redirect/other region
 * @cpu: the other CPU whose register we want to access
 *
 * Configure the redirect/other region for the local core/VP (depending upon
 * the CM revision) to target the specified @cpu & register @block. This is
 * equivalent to calling mips_cm_lock_other() but accepts a Linux CPU number
 * for convenience.
 */
static inline void mips_cm_lock_other_cpu(unsigned int cpu, unsigned int block)
{
	struct cpuinfo_mips *d = &cpu_data[cpu];

	mips_cm_lock_other(cpu_cluster(d), cpu_core(d), cpu_vpe_id(d), block);
}

#endif /* __MIPS_ASM_MIPS_CM_H__ */
Commit	Line	Data
2874c5fd	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
9f98f3dd PB	2	/*
9f98f3dd PB	3	* Copyright (C) 2013 Imagination Technologies
48c834be	4	* Author: Paul Burton <paul.burton@mips.com>
9f98f3dd PB	5	*/
9f98f3dd PB	6
e83f7e02 PB	7	#ifndef __MIPS_ASM_MIPS_CPS_H__
	8	# error Please include asm/mips-cps.h rather than asm/mips-cm.h
	9	#endif
	10
9f98f3dd PB	11	#ifndef __MIPS_ASM_MIPS_CM_H__
	12	#define __MIPS_ASM_MIPS_CM_H__
	13
47b26a46	14	#include <linux/bitops.h>
56d4c99b	15	#include <linux/errno.h>
9f98f3dd PB	16
9f98f3dd PB	17	/* The base address of the CM GCR block */
abe852ea	18	extern void __iomem *mips_gcr_base;
9f98f3dd PB	19
	20	/* The base address of the CM L2-only sync region */
	21	extern void __iomem *mips_cm_l2sync_base;
	22
	23	/**
	24	* __mips_cm_phys_base - retrieve the physical base address of the CM
	25	*
	26	* This function returns the physical base address of the Coherence Manager
	27	* global control block, or 0 if no Coherence Manager is present. It provides
	28	* a default implementation which reads the CMGCRBase register where available,
92a76f6d	29	* and may be overridden by platforms which determine this address in a
9f98f3dd PB	30	* different way by defining a function with the same prototype except for the
	31	* name mips_cm_phys_base (without underscores).
	32	*/
15d45cce	33	extern phys_addr_t __mips_cm_phys_base(void);
9f98f3dd	34
c0b584a2 MC	35	/*
	36	* mips_cm_is64 - determine CM register width
	37	*
7784494a PB	38	* The CM register width is determined by the version of the CM, with CM3
	39	* introducing 64 bit GCRs and all prior CM versions having 32 bit GCRs.
	40	* However we may run a kernel built for MIPS32 on a system with 64 bit GCRs,
	41	* or vice-versa. This variable indicates the width of the memory accesses
	42	* that the kernel will perform to GCRs, which may differ from the actual
	43	* width of the GCRs.
c0b584a2 MC	44	*
	45	* It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.
	46	*/
	47	extern int mips_cm_is64;
	48
3885c2b4 MC	49	/**
	50	* mips_cm_error_report - Report CM cache errors
	51	*/
	52	#ifdef CONFIG_MIPS_CM
	53	extern void mips_cm_error_report(void);
	54	#else
	55	static inline void mips_cm_error_report(void) {}
	56	#endif
	57
9f98f3dd PB	58	/**
	59	* mips_cm_probe - probe for a Coherence Manager
	60	*
	61	* Attempt to detect the presence of a Coherence Manager. Returns 0 if a CM
	62	* is successfully detected, else -errno.
	63	*/
	64	#ifdef CONFIG_MIPS_CM
	65	extern int mips_cm_probe(void);
	66	#else
	67	static inline int mips_cm_probe(void)
	68	{
	69	return -ENODEV;
	70	}
	71	#endif
	72
	73	/**
	74	* mips_cm_present - determine whether a Coherence Manager is present
	75	*
	76	* Returns true if a CM is present in the system, else false.
	77	*/
	78	static inline bool mips_cm_present(void)
	79	{
	80	#ifdef CONFIG_MIPS_CM
abe852ea	81	return mips_gcr_base != NULL;
9f98f3dd PB	82	#else
	83	return false;
	84	#endif
	85	}
	86
	87	/**
	88	* mips_cm_has_l2sync - determine whether an L2-only sync region is present
	89	*
	90	* Returns true if the system implements an L2-only sync region, else false.
	91	*/
	92	static inline bool mips_cm_has_l2sync(void)
	93	{
	94	#ifdef CONFIG_MIPS_CM
	95	return mips_cm_l2sync_base != NULL;
	96	#else
	97	return false;
	98	#endif
	99	}
	100
	101	/* Offsets to register blocks from the CM base address */
	102	#define MIPS_CM_GCB_OFS 0x0000 /* Global Control Block */
	103	#define MIPS_CM_CLCB_OFS 0x2000 /* Core Local Control Block */
	104	#define MIPS_CM_COCB_OFS 0x4000 /* Core Other Control Block */
	105	#define MIPS_CM_GDB_OFS 0x6000 /* Global Debug Block */
	106
	107	/* Total size of the CM memory mapped registers */
	108	#define MIPS_CM_GCR_SIZE 0x8000
	109
	110	/* Size of the L2-only sync region */
	111	#define MIPS_CM_L2SYNC_SIZE 0x1000
	112
b025d518	113	#define GCR_ACCESSOR_RO(sz, off, name) \
23cb600e PB	114	CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_GCB_OFS + off, name) \
23cb600e PB	115	CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, redir_##name)
9f98f3dd	116
b025d518	117	#define GCR_ACCESSOR_RW(sz, off, name) \
23cb600e PB	118	CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_GCB_OFS + off, name) \
23cb600e PB	119	CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_COCB_OFS + off, redir_##name)
9f98f3dd	120
b025d518 PB	121	#define GCR_CX_ACCESSOR_RO(sz, off, name) \
	122	CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name) \
	123	CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name)
9f98f3dd	124
b025d518 PB	125	#define GCR_CX_ACCESSOR_RW(sz, off, name) \
	126	CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name) \
	127	CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name)
9f98f3dd	128
93c5bba5	129	/* GCR_CONFIG - Information about the system */
b025d518	130	GCR_ACCESSOR_RO(64, 0x000, config)
23cb600e PB	131	#define CM_GCR_CONFIG_CLUSTER_COH_CAPABLE BIT_ULL(43)
	132	#define CM_GCR_CONFIG_CLUSTER_ID GENMASK_ULL(39, 32)
	133	#define CM_GCR_CONFIG_NUM_CLUSTERS GENMASK(29, 23)
93c5bba5 PB	134	#define CM_GCR_CONFIG_NUMIOCU GENMASK(15, 8)
	135	#define CM_GCR_CONFIG_PCORES GENMASK(7, 0)
	136
	137	/* GCR_BASE - Base address of the Global Configuration Registers (GCRs) */
b025d518	138	GCR_ACCESSOR_RW(64, 0x008, base)
93c5bba5 PB	139	#define CM_GCR_BASE_GCRBASE GENMASK_ULL(47, 15)
93c5bba5 PB	140	#define CM_GCR_BASE_CMDEFTGT GENMASK(1, 0)
6a6cba1d PB	141	#define CM_GCR_BASE_CMDEFTGT_MEM 0
6a6cba1d PB	142	#define CM_GCR_BASE_CMDEFTGT_RESERVED 1
93c5bba5 PB	143	#define CM_GCR_BASE_CMDEFTGT_IOCU0 2
	144	#define CM_GCR_BASE_CMDEFTGT_IOCU1 3
	145
	146	/* GCR_ACCESS - Controls core/IOCU access to GCRs */
b025d518	147	GCR_ACCESSOR_RW(32, 0x020, access)
93c5bba5 PB	148	#define CM_GCR_ACCESS_ACCESSEN GENMASK(7, 0)
	149
	150	/* GCR_REV - Indicates the Coherence Manager revision */
b025d518	151	GCR_ACCESSOR_RO(32, 0x030, rev)
93c5bba5 PB	152	#define CM_GCR_REV_MAJOR GENMASK(15, 8)
	153	#define CM_GCR_REV_MINOR GENMASK(7, 0)
	154
	155	#define CM_ENCODE_REV(major, minor) \
	156	(((major) << __ffs(CM_GCR_REV_MAJOR)) \| \
	157	((minor) << __ffs(CM_GCR_REV_MINOR)))
	158
	159	#define CM_REV_CM2 CM_ENCODE_REV(6, 0)
	160	#define CM_REV_CM2_5 CM_ENCODE_REV(7, 0)
	161	#define CM_REV_CM3 CM_ENCODE_REV(8, 0)
23cb600e	162	#define CM_REV_CM3_5 CM_ENCODE_REV(9, 0)
93c5bba5 PB	163
93c5bba5 PB	164	/* GCR_ERR_CONTROL - Control error checking logic */
b025d518	165	GCR_ACCESSOR_RW(32, 0x038, err_control)
93c5bba5 PB	166	#define CM_GCR_ERR_CONTROL_L2_ECC_EN BIT(1)
	167	#define CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT BIT(0)
	168
	169	/* GCR_ERR_MASK - Control which errors are reported as interrupts */
b025d518	170	GCR_ACCESSOR_RW(64, 0x040, error_mask)
93c5bba5 PB	171
93c5bba5 PB	172	/* GCR_ERR_CAUSE - Indicates the type of error that occurred */
b025d518	173	GCR_ACCESSOR_RW(64, 0x048, error_cause)
93c5bba5 PB	174	#define CM_GCR_ERROR_CAUSE_ERRTYPE GENMASK(31, 27)
	175	#define CM3_GCR_ERROR_CAUSE_ERRTYPE GENMASK_ULL(63, 58)
	176	#define CM_GCR_ERROR_CAUSE_ERRINFO GENMASK(26, 0)
	177
	178	/* GCR_ERR_ADDR - Indicates the address associated with an error */
b025d518	179	GCR_ACCESSOR_RW(64, 0x050, error_addr)
93c5bba5 PB	180
93c5bba5 PB	181	/* GCR_ERR_MULT - Indicates when multiple errors have occurred */
b025d518	182	GCR_ACCESSOR_RW(64, 0x058, error_mult)
93c5bba5 PB	183	#define CM_GCR_ERROR_MULT_ERR2ND GENMASK(4, 0)
	184
	185	/* GCR_L2_ONLY_SYNC_BASE - Base address of the L2 cache-only sync region */
b025d518	186	GCR_ACCESSOR_RW(64, 0x070, l2_only_sync_base)
93c5bba5 PB	187	#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE GENMASK(31, 12)
	188	#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN BIT(0)
	189
	190	/* GCR_GIC_BASE - Base address of the Global Interrupt Controller (GIC) */
b025d518	191	GCR_ACCESSOR_RW(64, 0x080, gic_base)
93c5bba5 PB	192	#define CM_GCR_GIC_BASE_GICBASE GENMASK(31, 17)
	193	#define CM_GCR_GIC_BASE_GICEN BIT(0)
	194
	195	/* GCR_CPC_BASE - Base address of the Cluster Power Controller (CPC) */
b025d518	196	GCR_ACCESSOR_RW(64, 0x088, cpc_base)
93c5bba5 PB	197	#define CM_GCR_CPC_BASE_CPCBASE GENMASK(31, 15)
	198	#define CM_GCR_CPC_BASE_CPCEN BIT(0)
	199
	200	/* GCR_REGn_BASE - Base addresses of CM address regions */
b025d518	201	GCR_ACCESSOR_RW(64, 0x090, reg0_base)
b025d518	202	GCR_ACCESSOR_RW(64, 0x0a0, reg1_base)
b025d518	203	GCR_ACCESSOR_RW(64, 0x0b0, reg2_base)
b025d518	204	GCR_ACCESSOR_RW(64, 0x0c0, reg3_base)
93c5bba5 PB	205	#define CM_GCR_REGn_BASE_BASEADDR GENMASK(31, 16)
	206
	207	/* GCR_REGn_MASK - Size & destination of CM address regions */
	208	GCR_ACCESSOR_RW(64, 0x098, reg0_mask)
	209	GCR_ACCESSOR_RW(64, 0x0a8, reg1_mask)
	210	GCR_ACCESSOR_RW(64, 0x0b8, reg2_mask)
b025d518	211	GCR_ACCESSOR_RW(64, 0x0c8, reg3_mask)
93c5bba5 PB	212	#define CM_GCR_REGn_MASK_ADDRMASK GENMASK(31, 16)
	213	#define CM_GCR_REGn_MASK_CCAOVR GENMASK(7, 5)
	214	#define CM_GCR_REGn_MASK_CCAOVREN BIT(4)
	215	#define CM_GCR_REGn_MASK_DROPL2 BIT(2)
	216	#define CM_GCR_REGn_MASK_CMTGT GENMASK(1, 0)
	217	#define CM_GCR_REGn_MASK_CMTGT_DISABLED 0x0
	218	#define CM_GCR_REGn_MASK_CMTGT_MEM 0x1
	219	#define CM_GCR_REGn_MASK_CMTGT_IOCU0 0x2
	220	#define CM_GCR_REGn_MASK_CMTGT_IOCU1 0x3
	221
	222	/* GCR_GIC_STATUS - Indicates presence of a Global Interrupt Controller (GIC) */
b025d518	223	GCR_ACCESSOR_RO(32, 0x0d0, gic_status)
93c5bba5 PB	224	#define CM_GCR_GIC_STATUS_EX BIT(0)
	225
	226	/* GCR_CPC_STATUS - Indicates presence of a Cluster Power Controller (CPC) */
b025d518	227	GCR_ACCESSOR_RO(32, 0x0f0, cpc_status)
93c5bba5 PB	228	#define CM_GCR_CPC_STATUS_EX BIT(0)
	229
	230	/* GCR_L2_CONFIG - Indicates L2 cache configuration when Config5.L2C=1 */
b025d518	231	GCR_ACCESSOR_RW(32, 0x130, l2_config)
93c5bba5 PB	232	#define CM_GCR_L2_CONFIG_BYPASS BIT(20)
	233	#define CM_GCR_L2_CONFIG_SET_SIZE GENMASK(15, 12)
	234	#define CM_GCR_L2_CONFIG_LINE_SIZE GENMASK(11, 8)
	235	#define CM_GCR_L2_CONFIG_ASSOC GENMASK(7, 0)
	236
	237	/* GCR_SYS_CONFIG2 - Further information about the system */
b025d518	238	GCR_ACCESSOR_RO(32, 0x150, sys_config2)
93c5bba5 PB	239	#define CM_GCR_SYS_CONFIG2_MAXVPW GENMASK(3, 0)
	240
	241	/* GCR_L2_PFT_CONTROL - Controls hardware L2 prefetching */
b025d518	242	GCR_ACCESSOR_RW(32, 0x300, l2_pft_control)
93c5bba5 PB	243	#define CM_GCR_L2_PFT_CONTROL_PAGEMASK GENMASK(31, 12)
	244	#define CM_GCR_L2_PFT_CONTROL_PFTEN BIT(8)
	245	#define CM_GCR_L2_PFT_CONTROL_NPFT GENMASK(7, 0)
	246
	247	/* GCR_L2_PFT_CONTROL_B - Controls hardware L2 prefetching */
b025d518	248	GCR_ACCESSOR_RW(32, 0x308, l2_pft_control_b)
93c5bba5 PB	249	#define CM_GCR_L2_PFT_CONTROL_B_CEN BIT(8)
	250	#define CM_GCR_L2_PFT_CONTROL_B_PORTID GENMASK(7, 0)
	251
23cb600e PB	252	/* GCR_L2SM_COP - L2 cache op state machine control */
	253	GCR_ACCESSOR_RW(32, 0x620, l2sm_cop)
	254	#define CM_GCR_L2SM_COP_PRESENT BIT(31)
	255	#define CM_GCR_L2SM_COP_RESULT GENMASK(8, 6)
	256	#define CM_GCR_L2SM_COP_RESULT_DONTCARE 0
	257	#define CM_GCR_L2SM_COP_RESULT_DONE_OK 1
	258	#define CM_GCR_L2SM_COP_RESULT_DONE_ERROR 2
	259	#define CM_GCR_L2SM_COP_RESULT_ABORT_OK 3
	260	#define CM_GCR_L2SM_COP_RESULT_ABORT_ERROR 4
	261	#define CM_GCR_L2SM_COP_RUNNING BIT(5)
	262	#define CM_GCR_L2SM_COP_TYPE GENMASK(4, 2)
	263	#define CM_GCR_L2SM_COP_TYPE_IDX_WBINV 0
	264	#define CM_GCR_L2SM_COP_TYPE_IDX_STORETAG 1
	265	#define CM_GCR_L2SM_COP_TYPE_IDX_STORETAGDATA 2
	266	#define CM_GCR_L2SM_COP_TYPE_HIT_INV 4
	267	#define CM_GCR_L2SM_COP_TYPE_HIT_WBINV 5
	268	#define CM_GCR_L2SM_COP_TYPE_HIT_WB 6
	269	#define CM_GCR_L2SM_COP_TYPE_FETCHLOCK 7
	270	#define CM_GCR_L2SM_COP_CMD GENMASK(1, 0)
	271	#define CM_GCR_L2SM_COP_CMD_START 1 /* only when idle */
	272	#define CM_GCR_L2SM_COP_CMD_ABORT 3 /* only when running */
	273
	274	/* GCR_L2SM_TAG_ADDR_COP - L2 cache op state machine address control */
	275	GCR_ACCESSOR_RW(64, 0x628, l2sm_tag_addr_cop)
	276	#define CM_GCR_L2SM_TAG_ADDR_COP_NUM_LINES GENMASK_ULL(63, 48)
	277	#define CM_GCR_L2SM_TAG_ADDR_COP_START_TAG GENMASK_ULL(47, 6)
	278
93c5bba5	279	/* GCR_BEV_BASE - Controls the location of the BEV for powered up cores */
b025d518	280	GCR_ACCESSOR_RW(64, 0x680, bev_base)
9f98f3dd	281
93c5bba5	282	/* GCR_Cx_RESET_RELEASE - Controls core reset for CM 1.x */
b025d518	283	GCR_CX_ACCESSOR_RW(32, 0x000, reset_release)
9f98f3dd	284
93c5bba5 PB	285	/* GCR_Cx_COHERENCE - Controls core coherence */
	286	GCR_CX_ACCESSOR_RW(32, 0x008, coherence)
	287	#define CM_GCR_Cx_COHERENCE_COHDOMAINEN GENMASK(7, 0)
	288	#define CM3_GCR_Cx_COHERENCE_COHEN BIT(0)
497e803e	289
93c5bba5 PB	290	/* GCR_Cx_CONFIG - Information about a core's configuration */
	291	GCR_CX_ACCESSOR_RO(32, 0x010, config)
	292	#define CM_GCR_Cx_CONFIG_IOCUTYPE GENMASK(11, 10)
	293	#define CM_GCR_Cx_CONFIG_PVPE GENMASK(9, 0)
9f98f3dd	294
93c5bba5 PB	295	/* GCR_Cx_OTHER - Configure the core-other/redirect GCR block */
93c5bba5 PB	296	GCR_CX_ACCESSOR_RW(32, 0x018, other)
23cb600e PB	297	#define CM_GCR_Cx_OTHER_CORENUM GENMASK(31, 16) /* CM < 3 */
	298	#define CM_GCR_Cx_OTHER_CLUSTER_EN BIT(31) /* CM >= 3.5 */
	299	#define CM_GCR_Cx_OTHER_GIC_EN BIT(30) /* CM >= 3.5 */
	300	#define CM_GCR_Cx_OTHER_BLOCK GENMASK(25, 24) /* CM >= 3.5 */
	301	#define CM_GCR_Cx_OTHER_BLOCK_LOCAL 0
	302	#define CM_GCR_Cx_OTHER_BLOCK_GLOBAL 1
	303	#define CM_GCR_Cx_OTHER_BLOCK_USER 2
	304	#define CM_GCR_Cx_OTHER_BLOCK_GLOBAL_HIGH 3
	305	#define CM_GCR_Cx_OTHER_CLUSTER GENMASK(21, 16) /* CM >= 3.5 */
	306	#define CM3_GCR_Cx_OTHER_CORE GENMASK(13, 8) /* CM >= 3 */
	307	#define CM_GCR_Cx_OTHER_CORE_CM 32
	308	#define CM3_GCR_Cx_OTHER_VP GENMASK(2, 0) /* CM >= 3 */
9f98f3dd	309
93c5bba5 PB	310	/* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */
	311	GCR_CX_ACCESSOR_RW(32, 0x020, reset_base)
	312	#define CM_GCR_Cx_RESET_BASE_BEVEXCBASE GENMASK(31, 12)
197e89e0	313
93c5bba5 PB	314	/* GCR_Cx_ID - Identify the current core */
93c5bba5 PB	315	GCR_CX_ACCESSOR_RO(32, 0x028, id)
23cb600e PB	316	#define CM_GCR_Cx_ID_CLUSTER GENMASK(15, 8)
23cb600e PB	317	#define CM_GCR_Cx_ID_CORE GENMASK(7, 0)
197e89e0	318
93c5bba5 PB	319	/* GCR_Cx_RESET_EXT_BASE - Configure behaviour when cores reset or power up */
	320	GCR_CX_ACCESSOR_RW(32, 0x030, reset_ext_base)
	321	#define CM_GCR_Cx_RESET_EXT_BASE_EVARESET BIT(31)
	322	#define CM_GCR_Cx_RESET_EXT_BASE_UEB BIT(30)
	323	#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK GENMASK(27, 20)
	324	#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA GENMASK(7, 1)
	325	#define CM_GCR_Cx_RESET_EXT_BASE_PRESENT BIT(0)
9f98f3dd	326
9f98f3dd PB	327	/**
	328	* mips_cm_l2sync - perform an L2-only sync operation
	329	*
	330	* If an L2-only sync region is present in the system then this function
	331	* performs and L2-only sync and returns zero. Otherwise it returns -ENODEV.
	332	*/
	333	static inline int mips_cm_l2sync(void)
	334	{
	335	if (!mips_cm_has_l2sync())
	336	return -ENODEV;
	337
	338	writel(0, mips_cm_l2sync_base);
	339	return 0;
	340	}
	341
197e89e0 PB	342	/**
	343	* mips_cm_revision() - return CM revision
	344	*
	345	* Return: The revision of the CM, from GCR_REV, or 0 if no CM is present. The
	346	* return value should be checked against the CM_REV_* macros.
	347	*/
	348	static inline int mips_cm_revision(void)
	349	{
	350	if (!mips_cm_present())
	351	return 0;
	352
	353	return read_gcr_rev();
	354	}
	355
7573b94e PB	356	/**
	357	* mips_cm_max_vp_width() - return the width in bits of VP indices
	358	*
	359	* Return: the width, in bits, of VP indices in fields that combine core & VP
	360	* indices.
	361	*/
	362	static inline unsigned int mips_cm_max_vp_width(void)
	363	{
	364	extern int smp_num_siblings;
6605d156	365	uint32_t cfg;
7573b94e PB	366
7573b94e PB	367	if (mips_cm_revision() >= CM_REV_CM3)
93c5bba5	368	return read_gcr_sys_config2() & CM_GCR_SYS_CONFIG2_MAXVPW;
7573b94e	369
6605d156 PB	370	if (mips_cm_present()) {
	371	/*
	372	* We presume that all cores in the system will have the same
	373	* number of VP(E)s, and if that ever changes then this will
	374	* need revisiting.
	375	*/
93c5bba5 PB	376	cfg = read_gcr_cl_config() & CM_GCR_Cx_CONFIG_PVPE;
93c5bba5 PB	377	return (cfg >> __ffs(CM_GCR_Cx_CONFIG_PVPE)) + 1;
6605d156 PB	378	}
6605d156 PB	379
97f2645f	380	if (IS_ENABLED(CONFIG_SMP))
a60ae81e PB	381	return smp_num_siblings;
	382
	383	return 1;
7573b94e PB	384	}
	385
	386	/**
	387	* mips_cm_vp_id() - calculate the hardware VP ID for a CPU
	388	* @cpu: the CPU whose VP ID to calculate
	389	*
	390	* Hardware such as the GIC uses identifiers for VPs which may not match the
	391	* CPU numbers used by Linux. This function calculates the hardware VP
	392	* identifier corresponding to a given CPU.
	393	*
	394	* Return: the VP ID for the CPU.
	395	*/
	396	static inline unsigned int mips_cm_vp_id(unsigned int cpu)
	397	{
f875a832	398	unsigned int core = cpu_core(&cpu_data[cpu]);
7573b94e PB	399	unsigned int vp = cpu_vpe_id(&cpu_data[cpu]);
	400
	401	return (core * mips_cm_max_vp_width()) + vp;
	402	}
	403
23d5de8e PB	404	#ifdef CONFIG_MIPS_CM
	405
	406	/**
68923cdc PB	407	* mips_cm_lock_other - lock access to redirect/other region
68923cdc PB	408	* @cluster: the other cluster to be accessed
23d5de8e PB	409	* @core: the other core to be accessed
23d5de8e PB	410	* @vp: the VP within the other core to be accessed
68923cdc	411	* @block: the register block to be accessed
23d5de8e	412	*
68923cdc PB	413	* Configure the redirect/other region for the local core/VP (depending upon
	414	* the CM revision) to target the specified @cluster, @core, @vp & register
	415	* @block. Must be called before using the redirect/other region, and followed
	416	* by a call to mips_cm_unlock_other() when access to the redirect/other region
	417	* is complete.
	418	*
	419	* This function acquires a spinlock such that code between it &
	420	* mips_cm_unlock_other() calls cannot be pre-empted by anything which may
	421	* reconfigure the redirect/other region, and cannot be interfered with by
	422	* another VP in the core. As such calls to this function should not be nested.
23d5de8e	423	*/
68923cdc PB	424	extern void mips_cm_lock_other(unsigned int cluster, unsigned int core,
68923cdc PB	425	unsigned int vp, unsigned int block);
23d5de8e PB	426
23d5de8e PB	427	/**
68923cdc	428	* mips_cm_unlock_other - unlock access to redirect/other region
23d5de8e	429	*
68923cdc PB	430	* Must be called after mips_cm_lock_other() once all required access to the
68923cdc PB	431	* redirect/other region has been completed.
23d5de8e PB	432	*/
	433	extern void mips_cm_unlock_other(void);
	434
	435	#else /* !CONFIG_MIPS_CM */
	436
68923cdc PB	437	static inline void mips_cm_lock_other(unsigned int cluster, unsigned int core,
68923cdc PB	438	unsigned int vp, unsigned int block) { }
23d5de8e PB	439	static inline void mips_cm_unlock_other(void) { }
	440
	441	#endif /* !CONFIG_MIPS_CM */
	442
68923cdc PB	443	/**
	444	* mips_cm_lock_other_cpu - lock access to redirect/other region
	445	* @cpu: the other CPU whose register we want to access
	446	*
	447	* Configure the redirect/other region for the local core/VP (depending upon
	448	* the CM revision) to target the specified @cpu & register @block. This is
	449	* equivalent to calling mips_cm_lock_other() but accepts a Linux CPU number
	450	* for convenience.
	451	*/
	452	static inline void mips_cm_lock_other_cpu(unsigned int cpu, unsigned int block)
	453	{
	454	struct cpuinfo_mips *d = &cpu_data[cpu];
	455
	456	mips_cm_lock_other(cpu_cluster(d), cpu_core(d), cpu_vpe_id(d), block);
	457	}
	458
9f98f3dd	459	#endif /* __MIPS_ASM_MIPS_CM_H__ */