[mirror_ubuntu-artful-kernel.git] / arch / mips / include / asm / mips-cm.h

/*
 * Copyright (C) 2013 Imagination Technologies
 * Author: Paul Burton <paul.burton@imgtec.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#ifndef __MIPS_ASM_MIPS_CM_H__
#define __MIPS_ASM_MIPS_CM_H__

#include <linux/errno.h>
#include <linux/io.h>
#include <linux/types.h>

/* The base address of the CM GCR block */
extern void __iomem *mips_cm_base;

/* The base address of the CM L2-only sync region */
extern void __iomem *mips_cm_l2sync_base;

/**
 * __mips_cm_phys_base - retrieve the physical base address of the CM
 *
 * This function returns the physical base address of the Coherence Manager
 * global control block, or 0 if no Coherence Manager is present. It provides
 * a default implementation which reads the CMGCRBase register where available,
 * and may be overriden by platforms which determine this address in a
 * different way by defining a function with the same prototype except for the
 * name mips_cm_phys_base (without underscores).
 */
extern phys_addr_t __mips_cm_phys_base(void);

/*
 * mips_cm_is64 - determine CM register width
 *
 * The CM register width is processor and CM specific. A 64-bit processor
 * usually has a 64-bit CM and a 32-bit one has a 32-bit CM but a 64-bit
 * processor could come with a 32-bit CM. Moreover, accesses on 64-bit CMs
 * can be done either using regular 64-bit load/store instructions, or 32-bit
 * load/store instruction on 32-bit register pairs. We opt for using 64-bit
 * accesses on 64-bit CMs and kernels and 32-bit in any other case.
 *
 * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.
 */
extern int mips_cm_is64;

/**
 * mips_cm_probe - probe for a Coherence Manager
 *
 * Attempt to detect the presence of a Coherence Manager. Returns 0 if a CM
 * is successfully detected, else -errno.
 */
#ifdef CONFIG_MIPS_CM
extern int mips_cm_probe(void);
#else
static inline int mips_cm_probe(void)
{
	return -ENODEV;
}
#endif

/**
 * mips_cm_present - determine whether a Coherence Manager is present
 *
 * Returns true if a CM is present in the system, else false.
 */
static inline bool mips_cm_present(void)
{
#ifdef CONFIG_MIPS_CM
	return mips_cm_base != NULL;
#else
	return false;
#endif
}

/**
 * mips_cm_has_l2sync - determine whether an L2-only sync region is present
 *
 * Returns true if the system implements an L2-only sync region, else false.
 */
static inline bool mips_cm_has_l2sync(void)
{
#ifdef CONFIG_MIPS_CM
	return mips_cm_l2sync_base != NULL;
#else
	return false;
#endif
}

/* Offsets to register blocks from the CM base address */
#define MIPS_CM_GCB_OFS		0x0000 /* Global Control Block */
#define MIPS_CM_CLCB_OFS	0x2000 /* Core Local Control Block */
#define MIPS_CM_COCB_OFS	0x4000 /* Core Other Control Block */
#define MIPS_CM_GDB_OFS		0x6000 /* Global Debug Block */

/* Total size of the CM memory mapped registers */
#define MIPS_CM_GCR_SIZE	0x8000

/* Size of the L2-only sync region */
#define MIPS_CM_L2SYNC_SIZE	0x1000

/* Macros to ease the creation of register access functions */
#define BUILD_CM_R_(name, off)					\
static inline unsigned long __iomem *addr_gcr_##name(void)	\
{								\
	return (unsigned long __iomem *)(mips_cm_base + (off));	\
}								\
								\
static inline u32 read32_gcr_##name(void)			\
{								\
	return __raw_readl(addr_gcr_##name());			\
}								\
								\
static inline u64 read64_gcr_##name(void)			\
{								\
	return __raw_readq(addr_gcr_##name());			\
}								\
								\
static inline unsigned long read_gcr_##name(void)		\
{								\
	if (mips_cm_is64)					\
		return read64_gcr_##name();			\
	else							\
		return read32_gcr_##name();			\
}

#define BUILD_CM__W(name, off)					\
static inline void write32_gcr_##name(u32 value)		\
{								\
	__raw_writel(value, addr_gcr_##name());			\
}								\
								\
static inline void write64_gcr_##name(u64 value)		\
{								\
	__raw_writeq(value, addr_gcr_##name());			\
}								\
								\
static inline void write_gcr_##name(unsigned long value)	\
{								\
	if (mips_cm_is64)					\
		write64_gcr_##name(value);			\
	else							\
		write32_gcr_##name(value);			\
}

#define BUILD_CM_RW(name, off)					\
	BUILD_CM_R_(name, off)					\
	BUILD_CM__W(name, off)

#define BUILD_CM_Cx_R_(name, off)				\
	BUILD_CM_R_(cl_##name, MIPS_CM_CLCB_OFS + (off))	\
	BUILD_CM_R_(co_##name, MIPS_CM_COCB_OFS + (off))

#define BUILD_CM_Cx__W(name, off)				\
	BUILD_CM__W(cl_##name, MIPS_CM_CLCB_OFS + (off))	\
	BUILD_CM__W(co_##name, MIPS_CM_COCB_OFS + (off))

#define BUILD_CM_Cx_RW(name, off)				\
	BUILD_CM_Cx_R_(name, off)				\
	BUILD_CM_Cx__W(name, off)

/* GCB register accessor functions */
BUILD_CM_R_(config,		MIPS_CM_GCB_OFS + 0x00)
BUILD_CM_RW(base,		MIPS_CM_GCB_OFS + 0x08)
BUILD_CM_RW(access,		MIPS_CM_GCB_OFS + 0x20)
BUILD_CM_R_(rev,		MIPS_CM_GCB_OFS + 0x30)
BUILD_CM_RW(error_mask,		MIPS_CM_GCB_OFS + 0x40)
BUILD_CM_RW(error_cause,	MIPS_CM_GCB_OFS + 0x48)
BUILD_CM_RW(error_addr,		MIPS_CM_GCB_OFS + 0x50)
BUILD_CM_RW(error_mult,		MIPS_CM_GCB_OFS + 0x58)
BUILD_CM_RW(l2_only_sync_base,	MIPS_CM_GCB_OFS + 0x70)
BUILD_CM_RW(gic_base,		MIPS_CM_GCB_OFS + 0x80)
BUILD_CM_RW(cpc_base,		MIPS_CM_GCB_OFS + 0x88)
BUILD_CM_RW(reg0_base,		MIPS_CM_GCB_OFS + 0x90)
BUILD_CM_RW(reg0_mask,		MIPS_CM_GCB_OFS + 0x98)
BUILD_CM_RW(reg1_base,		MIPS_CM_GCB_OFS + 0xa0)
BUILD_CM_RW(reg1_mask,		MIPS_CM_GCB_OFS + 0xa8)
BUILD_CM_RW(reg2_base,		MIPS_CM_GCB_OFS + 0xb0)
BUILD_CM_RW(reg2_mask,		MIPS_CM_GCB_OFS + 0xb8)
BUILD_CM_RW(reg3_base,		MIPS_CM_GCB_OFS + 0xc0)
BUILD_CM_RW(reg3_mask,		MIPS_CM_GCB_OFS + 0xc8)
BUILD_CM_R_(gic_status,		MIPS_CM_GCB_OFS + 0xd0)
BUILD_CM_R_(cpc_status,		MIPS_CM_GCB_OFS + 0xf0)
BUILD_CM_RW(l2_config,		MIPS_CM_GCB_OFS + 0x130)

/* Core Local & Core Other register accessor functions */
BUILD_CM_Cx_RW(reset_release,	0x00)
BUILD_CM_Cx_RW(coherence,	0x08)
BUILD_CM_Cx_R_(config,		0x10)
BUILD_CM_Cx_RW(other,		0x18)
BUILD_CM_Cx_RW(reset_base,	0x20)
BUILD_CM_Cx_R_(id,		0x28)
BUILD_CM_Cx_RW(reset_ext_base,	0x30)
BUILD_CM_Cx_R_(tcid_0_priority,	0x40)
BUILD_CM_Cx_R_(tcid_1_priority,	0x48)
BUILD_CM_Cx_R_(tcid_2_priority,	0x50)
BUILD_CM_Cx_R_(tcid_3_priority,	0x58)
BUILD_CM_Cx_R_(tcid_4_priority,	0x60)
BUILD_CM_Cx_R_(tcid_5_priority,	0x68)
BUILD_CM_Cx_R_(tcid_6_priority,	0x70)
BUILD_CM_Cx_R_(tcid_7_priority,	0x78)
BUILD_CM_Cx_R_(tcid_8_priority,	0x80)

/* GCR_CONFIG register fields */
#define CM_GCR_CONFIG_NUMIOCU_SHF		8
#define CM_GCR_CONFIG_NUMIOCU_MSK		(_ULCAST_(0xf) << 8)
#define CM_GCR_CONFIG_PCORES_SHF		0
#define CM_GCR_CONFIG_PCORES_MSK		(_ULCAST_(0xff) << 0)

/* GCR_BASE register fields */
#define CM_GCR_BASE_GCRBASE_SHF			15
#define CM_GCR_BASE_GCRBASE_MSK			(_ULCAST_(0x1ffff) << 15)
#define CM_GCR_BASE_CMDEFTGT_SHF		0
#define CM_GCR_BASE_CMDEFTGT_MSK		(_ULCAST_(0x3) << 0)
#define  CM_GCR_BASE_CMDEFTGT_DISABLED		0
#define  CM_GCR_BASE_CMDEFTGT_MEM		1
#define  CM_GCR_BASE_CMDEFTGT_IOCU0		2
#define  CM_GCR_BASE_CMDEFTGT_IOCU1		3

/* GCR_ACCESS register fields */
#define CM_GCR_ACCESS_ACCESSEN_SHF		0
#define CM_GCR_ACCESS_ACCESSEN_MSK		(_ULCAST_(0xff) << 0)

/* GCR_REV register fields */
#define CM_GCR_REV_MAJOR_SHF			8
#define CM_GCR_REV_MAJOR_MSK			(_ULCAST_(0xff) << 8)
#define CM_GCR_REV_MINOR_SHF			0
#define CM_GCR_REV_MINOR_MSK			(_ULCAST_(0xff) << 0)

#define CM_ENCODE_REV(major, minor) \
		(((major) << CM_GCR_REV_MAJOR_SHF) | \
		 ((minor) << CM_GCR_REV_MINOR_SHF))

#define CM_REV_CM2				CM_ENCODE_REV(6, 0)
#define CM_REV_CM3				CM_ENCODE_REV(8, 0)

/* GCR_ERROR_CAUSE register fields */
#define CM_GCR_ERROR_CAUSE_ERRTYPE_SHF		27
#define CM_GCR_ERROR_CAUSE_ERRTYPE_MSK		(_ULCAST_(0x1f) << 27)
#define CM_GCR_ERROR_CAUSE_ERRINFO_SHF		0
#define CM_GCR_ERROR_CAUSE_ERRINGO_MSK		(_ULCAST_(0x7ffffff) << 0)

/* GCR_ERROR_MULT register fields */
#define CM_GCR_ERROR_MULT_ERR2ND_SHF		0
#define CM_GCR_ERROR_MULT_ERR2ND_MSK		(_ULCAST_(0x1f) << 0)

/* GCR_L2_ONLY_SYNC_BASE register fields */
#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_SHF	12
#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK	(_ULCAST_(0xfffff) << 12)
#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_SHF	0
#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK	(_ULCAST_(0x1) << 0)

/* GCR_GIC_BASE register fields */
#define CM_GCR_GIC_BASE_GICBASE_SHF		17
#define CM_GCR_GIC_BASE_GICBASE_MSK		(_ULCAST_(0x7fff) << 17)
#define CM_GCR_GIC_BASE_GICEN_SHF		0
#define CM_GCR_GIC_BASE_GICEN_MSK		(_ULCAST_(0x1) << 0)

/* GCR_CPC_BASE register fields */
#define CM_GCR_CPC_BASE_CPCBASE_SHF		17
#define CM_GCR_CPC_BASE_CPCBASE_MSK		(_ULCAST_(0x7fff) << 17)
#define CM_GCR_CPC_BASE_CPCEN_SHF		0
#define CM_GCR_CPC_BASE_CPCEN_MSK		(_ULCAST_(0x1) << 0)

/* GCR_GIC_STATUS register fields */
#define CM_GCR_GIC_STATUS_GICEX_SHF		0
#define CM_GCR_GIC_STATUS_GICEX_MSK		(_ULCAST_(0x1) << 0)

/* GCR_REGn_BASE register fields */
#define CM_GCR_REGn_BASE_BASEADDR_SHF		16
#define CM_GCR_REGn_BASE_BASEADDR_MSK		(_ULCAST_(0xffff) << 16)

/* GCR_REGn_MASK register fields */
#define CM_GCR_REGn_MASK_ADDRMASK_SHF		16
#define CM_GCR_REGn_MASK_ADDRMASK_MSK		(_ULCAST_(0xffff) << 16)
#define CM_GCR_REGn_MASK_CCAOVR_SHF		5
#define CM_GCR_REGn_MASK_CCAOVR_MSK		(_ULCAST_(0x3) << 5)
#define CM_GCR_REGn_MASK_CCAOVREN_SHF		4
#define CM_GCR_REGn_MASK_CCAOVREN_MSK		(_ULCAST_(0x1) << 4)
#define CM_GCR_REGn_MASK_DROPL2_SHF		2
#define CM_GCR_REGn_MASK_DROPL2_MSK		(_ULCAST_(0x1) << 2)
#define CM_GCR_REGn_MASK_CMTGT_SHF		0
#define CM_GCR_REGn_MASK_CMTGT_MSK		(_ULCAST_(0x3) << 0)
#define  CM_GCR_REGn_MASK_CMTGT_DISABLED	(_ULCAST_(0x0) << 0)
#define  CM_GCR_REGn_MASK_CMTGT_MEM		(_ULCAST_(0x1) << 0)
#define  CM_GCR_REGn_MASK_CMTGT_IOCU0		(_ULCAST_(0x2) << 0)
#define  CM_GCR_REGn_MASK_CMTGT_IOCU1		(_ULCAST_(0x3) << 0)

/* GCR_GIC_STATUS register fields */
#define CM_GCR_GIC_STATUS_EX_SHF		0
#define CM_GCR_GIC_STATUS_EX_MSK		(_ULCAST_(0x1) << 0)

/* GCR_CPC_STATUS register fields */
#define CM_GCR_CPC_STATUS_EX_SHF		0
#define CM_GCR_CPC_STATUS_EX_MSK		(_ULCAST_(0x1) << 0)

/* GCR_L2_CONFIG register fields */
#define CM_GCR_L2_CONFIG_BYPASS_SHF		20
#define CM_GCR_L2_CONFIG_BYPASS_MSK		(_ULCAST_(0x1) << 20)
#define CM_GCR_L2_CONFIG_SET_SIZE_SHF		12
#define CM_GCR_L2_CONFIG_SET_SIZE_MSK		(_ULCAST_(0xf) << 12)
#define CM_GCR_L2_CONFIG_LINE_SIZE_SHF		8
#define CM_GCR_L2_CONFIG_LINE_SIZE_MSK		(_ULCAST_(0xf) << 8)
#define CM_GCR_L2_CONFIG_ASSOC_SHF		0
#define CM_GCR_L2_CONFIG_ASSOC_MSK		(_ULCAST_(0xff) << 0)

/* GCR_Cx_COHERENCE register fields */
#define CM_GCR_Cx_COHERENCE_COHDOMAINEN_SHF	0
#define CM_GCR_Cx_COHERENCE_COHDOMAINEN_MSK	(_ULCAST_(0xff) << 0)

/* GCR_Cx_CONFIG register fields */
#define CM_GCR_Cx_CONFIG_IOCUTYPE_SHF		10
#define CM_GCR_Cx_CONFIG_IOCUTYPE_MSK		(_ULCAST_(0x3) << 10)
#define CM_GCR_Cx_CONFIG_PVPE_SHF		0
#define CM_GCR_Cx_CONFIG_PVPE_MSK		(_ULCAST_(0x1ff) << 0)

/* GCR_Cx_OTHER register fields */
#define CM_GCR_Cx_OTHER_CORENUM_SHF		16
#define CM_GCR_Cx_OTHER_CORENUM_MSK		(_ULCAST_(0xffff) << 16)

/* GCR_Cx_RESET_BASE register fields */
#define CM_GCR_Cx_RESET_BASE_BEVEXCBASE_SHF	12
#define CM_GCR_Cx_RESET_BASE_BEVEXCBASE_MSK	(_ULCAST_(0xfffff) << 12)

/* GCR_Cx_RESET_EXT_BASE register fields */
#define CM_GCR_Cx_RESET_EXT_BASE_EVARESET_SHF	31
#define CM_GCR_Cx_RESET_EXT_BASE_EVARESET_MSK	(_ULCAST_(0x1) << 31)
#define CM_GCR_Cx_RESET_EXT_BASE_UEB_SHF	30
#define CM_GCR_Cx_RESET_EXT_BASE_UEB_MSK	(_ULCAST_(0x1) << 30)
#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK_SHF	20
#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK_MSK	(_ULCAST_(0xff) << 20)
#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA_SHF	1
#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA_MSK	(_ULCAST_(0x7f) << 1)
#define CM_GCR_Cx_RESET_EXT_BASE_PRESENT_SHF	0
#define CM_GCR_Cx_RESET_EXT_BASE_PRESENT_MSK	(_ULCAST_(0x1) << 0)

/**
 * mips_cm_numcores - return the number of cores present in the system
 *
 * Returns the value of the PCORES field of the GCR_CONFIG register plus 1, or
 * zero if no Coherence Manager is present.
 */
static inline unsigned mips_cm_numcores(void)
{
	if (!mips_cm_present())
		return 0;

	return ((read_gcr_config() & CM_GCR_CONFIG_PCORES_MSK)
		>> CM_GCR_CONFIG_PCORES_SHF) + 1;
}

/**
 * mips_cm_numiocu - return the number of IOCUs present in the system
 *
 * Returns the value of the NUMIOCU field of the GCR_CONFIG register, or zero
 * if no Coherence Manager is present.
 */
static inline unsigned mips_cm_numiocu(void)
{
	if (!mips_cm_present())
		return 0;

	return (read_gcr_config() & CM_GCR_CONFIG_NUMIOCU_MSK)
		>> CM_GCR_CONFIG_NUMIOCU_SHF;
}

/**
 * mips_cm_l2sync - perform an L2-only sync operation
 *
 * If an L2-only sync region is present in the system then this function
 * performs and L2-only sync and returns zero. Otherwise it returns -ENODEV.
 */
static inline int mips_cm_l2sync(void)
{
	if (!mips_cm_has_l2sync())
		return -ENODEV;

	writel(0, mips_cm_l2sync_base);
	return 0;
}

/**
 * mips_cm_revision() - return CM revision
 *
 * Return: The revision of the CM, from GCR_REV, or 0 if no CM is present. The
 * return value should be checked against the CM_REV_* macros.
 */
static inline int mips_cm_revision(void)
{
	if (!mips_cm_present())
		return 0;

	return read_gcr_rev();
}

#endif /* __MIPS_ASM_MIPS_CM_H__ */
Commit	Line	Data
9f98f3dd PB	1	/*
	2	* Copyright (C) 2013 Imagination Technologies
	3	* Author: Paul Burton <paul.burton@imgtec.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License as published by the
	7	* Free Software Foundation; either version 2 of the License, or (at your
	8	* option) any later version.
	9	*/
	10
	11	#ifndef __MIPS_ASM_MIPS_CM_H__
	12	#define __MIPS_ASM_MIPS_CM_H__
	13
56d4c99b	14	#include <linux/errno.h>
9f98f3dd PB	15	#include <linux/io.h>
	16	#include <linux/types.h>
	17
	18	/* The base address of the CM GCR block */
	19	extern void __iomem *mips_cm_base;
	20
	21	/* The base address of the CM L2-only sync region */
	22	extern void __iomem *mips_cm_l2sync_base;
	23
	24	/**
	25	* __mips_cm_phys_base - retrieve the physical base address of the CM
	26	*
	27	* This function returns the physical base address of the Coherence Manager
	28	* global control block, or 0 if no Coherence Manager is present. It provides
	29	* a default implementation which reads the CMGCRBase register where available,
	30	* and may be overriden by platforms which determine this address in a
	31	* different way by defining a function with the same prototype except for the
	32	* name mips_cm_phys_base (without underscores).
	33	*/
15d45cce	34	extern phys_addr_t __mips_cm_phys_base(void);
9f98f3dd	35
c0b584a2 MC	36	/*
	37	* mips_cm_is64 - determine CM register width
	38	*
	39	* The CM register width is processor and CM specific. A 64-bit processor
	40	* usually has a 64-bit CM and a 32-bit one has a 32-bit CM but a 64-bit
	41	* processor could come with a 32-bit CM. Moreover, accesses on 64-bit CMs
	42	* can be done either using regular 64-bit load/store instructions, or 32-bit
	43	* load/store instruction on 32-bit register pairs. We opt for using 64-bit
	44	* accesses on 64-bit CMs and kernels and 32-bit in any other case.
	45	*
	46	* It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.
	47	*/
	48	extern int mips_cm_is64;
	49
9f98f3dd PB	50	/**
	51	* mips_cm_probe - probe for a Coherence Manager
	52	*
	53	* Attempt to detect the presence of a Coherence Manager. Returns 0 if a CM
	54	* is successfully detected, else -errno.
	55	*/
	56	#ifdef CONFIG_MIPS_CM
	57	extern int mips_cm_probe(void);
	58	#else
	59	static inline int mips_cm_probe(void)
	60	{
	61	return -ENODEV;
	62	}
	63	#endif
	64
	65	/**
	66	* mips_cm_present - determine whether a Coherence Manager is present
	67	*
	68	* Returns true if a CM is present in the system, else false.
	69	*/
	70	static inline bool mips_cm_present(void)
	71	{
	72	#ifdef CONFIG_MIPS_CM
	73	return mips_cm_base != NULL;
	74	#else
	75	return false;
	76	#endif
	77	}
	78
	79	/**
	80	* mips_cm_has_l2sync - determine whether an L2-only sync region is present
	81	*
	82	* Returns true if the system implements an L2-only sync region, else false.
	83	*/
	84	static inline bool mips_cm_has_l2sync(void)
	85	{
	86	#ifdef CONFIG_MIPS_CM
	87	return mips_cm_l2sync_base != NULL;
	88	#else
	89	return false;
	90	#endif
	91	}
	92
	93	/* Offsets to register blocks from the CM base address */
	94	#define MIPS_CM_GCB_OFS 0x0000 /* Global Control Block */
	95	#define MIPS_CM_CLCB_OFS 0x2000 /* Core Local Control Block */
	96	#define MIPS_CM_COCB_OFS 0x4000 /* Core Other Control Block */
	97	#define MIPS_CM_GDB_OFS 0x6000 /* Global Debug Block */
	98
	99	/* Total size of the CM memory mapped registers */
	100	#define MIPS_CM_GCR_SIZE 0x8000
	101
	102	/* Size of the L2-only sync region */
	103	#define MIPS_CM_L2SYNC_SIZE 0x1000
	104
	105	/* Macros to ease the creation of register access functions */
	106	#define BUILD_CM_R_(name, off) \
c0b584a2	107	static inline unsigned long __iomem *addr_gcr_##name(void) \
9f98f3dd	108	{ \
c0b584a2	109	return (unsigned long __iomem *)(mips_cm_base + (off)); \
9f98f3dd PB	110	} \
9f98f3dd PB	111	\
c0b584a2	112	static inline u32 read32_gcr_##name(void) \
9f98f3dd	113	{ \
cd217546	114	return __raw_readl(addr_gcr_##name()); \
c0b584a2 MC	115	} \
	116	\
	117	static inline u64 read64_gcr_##name(void) \
	118	{ \
	119	return __raw_readq(addr_gcr_##name()); \
	120	} \
	121	\
	122	static inline unsigned long read_gcr_##name(void) \
	123	{ \
	124	if (mips_cm_is64) \
	125	return read64_gcr_##name(); \
	126	else \
	127	return read32_gcr_##name(); \
9f98f3dd PB	128	}
	129
	130	#define BUILD_CM__W(name, off) \
c0b584a2	131	static inline void write32_gcr_##name(u32 value) \
9f98f3dd	132	{ \
cd217546	133	__raw_writel(value, addr_gcr_##name()); \
c0b584a2 MC	134	} \
	135	\
	136	static inline void write64_gcr_##name(u64 value) \
	137	{ \
	138	__raw_writeq(value, addr_gcr_##name()); \
	139	} \
	140	\
	141	static inline void write_gcr_##name(unsigned long value) \
	142	{ \
	143	if (mips_cm_is64) \
	144	write64_gcr_##name(value); \
	145	else \
	146	write32_gcr_##name(value); \
9f98f3dd PB	147	}
	148
	149	#define BUILD_CM_RW(name, off) \
	150	BUILD_CM_R_(name, off) \
	151	BUILD_CM__W(name, off)
	152
	153	#define BUILD_CM_Cx_R_(name, off) \
	154	BUILD_CM_R_(cl_##name, MIPS_CM_CLCB_OFS + (off)) \
	155	BUILD_CM_R_(co_##name, MIPS_CM_COCB_OFS + (off))
	156
	157	#define BUILD_CM_Cx__W(name, off) \
	158	BUILD_CM__W(cl_##name, MIPS_CM_CLCB_OFS + (off)) \
	159	BUILD_CM__W(co_##name, MIPS_CM_COCB_OFS + (off))
	160
	161	#define BUILD_CM_Cx_RW(name, off) \
	162	BUILD_CM_Cx_R_(name, off) \
	163	BUILD_CM_Cx__W(name, off)
	164
	165	/* GCB register accessor functions */
	166	BUILD_CM_R_(config, MIPS_CM_GCB_OFS + 0x00)
	167	BUILD_CM_RW(base, MIPS_CM_GCB_OFS + 0x08)
	168	BUILD_CM_RW(access, MIPS_CM_GCB_OFS + 0x20)
	169	BUILD_CM_R_(rev, MIPS_CM_GCB_OFS + 0x30)
	170	BUILD_CM_RW(error_mask, MIPS_CM_GCB_OFS + 0x40)
	171	BUILD_CM_RW(error_cause, MIPS_CM_GCB_OFS + 0x48)
	172	BUILD_CM_RW(error_addr, MIPS_CM_GCB_OFS + 0x50)
	173	BUILD_CM_RW(error_mult, MIPS_CM_GCB_OFS + 0x58)
	174	BUILD_CM_RW(l2_only_sync_base, MIPS_CM_GCB_OFS + 0x70)
	175	BUILD_CM_RW(gic_base, MIPS_CM_GCB_OFS + 0x80)
	176	BUILD_CM_RW(cpc_base, MIPS_CM_GCB_OFS + 0x88)
	177	BUILD_CM_RW(reg0_base, MIPS_CM_GCB_OFS + 0x90)
	178	BUILD_CM_RW(reg0_mask, MIPS_CM_GCB_OFS + 0x98)
	179	BUILD_CM_RW(reg1_base, MIPS_CM_GCB_OFS + 0xa0)
	180	BUILD_CM_RW(reg1_mask, MIPS_CM_GCB_OFS + 0xa8)
	181	BUILD_CM_RW(reg2_base, MIPS_CM_GCB_OFS + 0xb0)
	182	BUILD_CM_RW(reg2_mask, MIPS_CM_GCB_OFS + 0xb8)
	183	BUILD_CM_RW(reg3_base, MIPS_CM_GCB_OFS + 0xc0)
	184	BUILD_CM_RW(reg3_mask, MIPS_CM_GCB_OFS + 0xc8)
	185	BUILD_CM_R_(gic_status, MIPS_CM_GCB_OFS + 0xd0)
	186	BUILD_CM_R_(cpc_status, MIPS_CM_GCB_OFS + 0xf0)
0ba3c125	187	BUILD_CM_RW(l2_config, MIPS_CM_GCB_OFS + 0x130)
9f98f3dd PB	188
	189	/* Core Local & Core Other register accessor functions */
	190	BUILD_CM_Cx_RW(reset_release, 0x00)
	191	BUILD_CM_Cx_RW(coherence, 0x08)
	192	BUILD_CM_Cx_R_(config, 0x10)
	193	BUILD_CM_Cx_RW(other, 0x18)
	194	BUILD_CM_Cx_RW(reset_base, 0x20)
	195	BUILD_CM_Cx_R_(id, 0x28)
	196	BUILD_CM_Cx_RW(reset_ext_base, 0x30)
	197	BUILD_CM_Cx_R_(tcid_0_priority, 0x40)
	198	BUILD_CM_Cx_R_(tcid_1_priority, 0x48)
	199	BUILD_CM_Cx_R_(tcid_2_priority, 0x50)
	200	BUILD_CM_Cx_R_(tcid_3_priority, 0x58)
	201	BUILD_CM_Cx_R_(tcid_4_priority, 0x60)
	202	BUILD_CM_Cx_R_(tcid_5_priority, 0x68)
	203	BUILD_CM_Cx_R_(tcid_6_priority, 0x70)
	204	BUILD_CM_Cx_R_(tcid_7_priority, 0x78)
	205	BUILD_CM_Cx_R_(tcid_8_priority, 0x80)
	206
	207	/* GCR_CONFIG register fields */
	208	#define CM_GCR_CONFIG_NUMIOCU_SHF 8
	209	#define CM_GCR_CONFIG_NUMIOCU_MSK (_ULCAST_(0xf) << 8)
	210	#define CM_GCR_CONFIG_PCORES_SHF 0
	211	#define CM_GCR_CONFIG_PCORES_MSK (_ULCAST_(0xff) << 0)
	212
	213	/* GCR_BASE register fields */
	214	#define CM_GCR_BASE_GCRBASE_SHF 15
	215	#define CM_GCR_BASE_GCRBASE_MSK (_ULCAST_(0x1ffff) << 15)
	216	#define CM_GCR_BASE_CMDEFTGT_SHF 0
	217	#define CM_GCR_BASE_CMDEFTGT_MSK (_ULCAST_(0x3) << 0)
	218	#define CM_GCR_BASE_CMDEFTGT_DISABLED 0
	219	#define CM_GCR_BASE_CMDEFTGT_MEM 1
	220	#define CM_GCR_BASE_CMDEFTGT_IOCU0 2
	221	#define CM_GCR_BASE_CMDEFTGT_IOCU1 3
	222
	223	/* GCR_ACCESS register fields */
	224	#define CM_GCR_ACCESS_ACCESSEN_SHF 0
	225	#define CM_GCR_ACCESS_ACCESSEN_MSK (_ULCAST_(0xff) << 0)
	226
	227	/* GCR_REV register fields */
	228	#define CM_GCR_REV_MAJOR_SHF 8
	229	#define CM_GCR_REV_MAJOR_MSK (_ULCAST_(0xff) << 8)
	230	#define CM_GCR_REV_MINOR_SHF 0
	231	#define CM_GCR_REV_MINOR_MSK (_ULCAST_(0xff) << 0)
	232
197e89e0 PB	233	#define CM_ENCODE_REV(major, minor) \
	234	(((major) << CM_GCR_REV_MAJOR_SHF) \| \
	235	((minor) << CM_GCR_REV_MINOR_SHF))
	236
	237	#define CM_REV_CM2 CM_ENCODE_REV(6, 0)
	238	#define CM_REV_CM3 CM_ENCODE_REV(8, 0)
	239
9f98f3dd PB	240	/* GCR_ERROR_CAUSE register fields */
	241	#define CM_GCR_ERROR_CAUSE_ERRTYPE_SHF 27
	242	#define CM_GCR_ERROR_CAUSE_ERRTYPE_MSK (_ULCAST_(0x1f) << 27)
	243	#define CM_GCR_ERROR_CAUSE_ERRINFO_SHF 0
	244	#define CM_GCR_ERROR_CAUSE_ERRINGO_MSK (_ULCAST_(0x7ffffff) << 0)
	245
	246	/* GCR_ERROR_MULT register fields */
	247	#define CM_GCR_ERROR_MULT_ERR2ND_SHF 0
	248	#define CM_GCR_ERROR_MULT_ERR2ND_MSK (_ULCAST_(0x1f) << 0)
	249
	250	/* GCR_L2_ONLY_SYNC_BASE register fields */
	251	#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_SHF 12
	252	#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK (_ULCAST_(0xfffff) << 12)
	253	#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_SHF 0
	254	#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK (_ULCAST_(0x1) << 0)
	255
	256	/* GCR_GIC_BASE register fields */
	257	#define CM_GCR_GIC_BASE_GICBASE_SHF 17
	258	#define CM_GCR_GIC_BASE_GICBASE_MSK (_ULCAST_(0x7fff) << 17)
	259	#define CM_GCR_GIC_BASE_GICEN_SHF 0
	260	#define CM_GCR_GIC_BASE_GICEN_MSK (_ULCAST_(0x1) << 0)
	261
	262	/* GCR_CPC_BASE register fields */
	263	#define CM_GCR_CPC_BASE_CPCBASE_SHF 17
	264	#define CM_GCR_CPC_BASE_CPCBASE_MSK (_ULCAST_(0x7fff) << 17)
	265	#define CM_GCR_CPC_BASE_CPCEN_SHF 0
	266	#define CM_GCR_CPC_BASE_CPCEN_MSK (_ULCAST_(0x1) << 0)
	267
921d55e3 PB	268	/* GCR_GIC_STATUS register fields */
	269	#define CM_GCR_GIC_STATUS_GICEX_SHF 0
	270	#define CM_GCR_GIC_STATUS_GICEX_MSK (_ULCAST_(0x1) << 0)
	271
9f98f3dd PB	272	/* GCR_REGn_BASE register fields */
	273	#define CM_GCR_REGn_BASE_BASEADDR_SHF 16
	274	#define CM_GCR_REGn_BASE_BASEADDR_MSK (_ULCAST_(0xffff) << 16)
	275
	276	/* GCR_REGn_MASK register fields */
	277	#define CM_GCR_REGn_MASK_ADDRMASK_SHF 16
	278	#define CM_GCR_REGn_MASK_ADDRMASK_MSK (_ULCAST_(0xffff) << 16)
	279	#define CM_GCR_REGn_MASK_CCAOVR_SHF 5
	280	#define CM_GCR_REGn_MASK_CCAOVR_MSK (_ULCAST_(0x3) << 5)
	281	#define CM_GCR_REGn_MASK_CCAOVREN_SHF 4
	282	#define CM_GCR_REGn_MASK_CCAOVREN_MSK (_ULCAST_(0x1) << 4)
	283	#define CM_GCR_REGn_MASK_DROPL2_SHF 2
	284	#define CM_GCR_REGn_MASK_DROPL2_MSK (_ULCAST_(0x1) << 2)
	285	#define CM_GCR_REGn_MASK_CMTGT_SHF 0
	286	#define CM_GCR_REGn_MASK_CMTGT_MSK (_ULCAST_(0x3) << 0)
	287	#define CM_GCR_REGn_MASK_CMTGT_DISABLED (_ULCAST_(0x0) << 0)
	288	#define CM_GCR_REGn_MASK_CMTGT_MEM (_ULCAST_(0x1) << 0)
	289	#define CM_GCR_REGn_MASK_CMTGT_IOCU0 (_ULCAST_(0x2) << 0)
	290	#define CM_GCR_REGn_MASK_CMTGT_IOCU1 (_ULCAST_(0x3) << 0)
	291
	292	/* GCR_GIC_STATUS register fields */
	293	#define CM_GCR_GIC_STATUS_EX_SHF 0
	294	#define CM_GCR_GIC_STATUS_EX_MSK (_ULCAST_(0x1) << 0)
	295
	296	/* GCR_CPC_STATUS register fields */
	297	#define CM_GCR_CPC_STATUS_EX_SHF 0
	298	#define CM_GCR_CPC_STATUS_EX_MSK (_ULCAST_(0x1) << 0)
	299
0ba3c125 PB	300	/* GCR_L2_CONFIG register fields */
	301	#define CM_GCR_L2_CONFIG_BYPASS_SHF 20
	302	#define CM_GCR_L2_CONFIG_BYPASS_MSK (_ULCAST_(0x1) << 20)
	303	#define CM_GCR_L2_CONFIG_SET_SIZE_SHF 12
	304	#define CM_GCR_L2_CONFIG_SET_SIZE_MSK (_ULCAST_(0xf) << 12)
	305	#define CM_GCR_L2_CONFIG_LINE_SIZE_SHF 8
	306	#define CM_GCR_L2_CONFIG_LINE_SIZE_MSK (_ULCAST_(0xf) << 8)
	307	#define CM_GCR_L2_CONFIG_ASSOC_SHF 0
	308	#define CM_GCR_L2_CONFIG_ASSOC_MSK (_ULCAST_(0xff) << 0)
	309
9f98f3dd PB	310	/* GCR_Cx_COHERENCE register fields */
	311	#define CM_GCR_Cx_COHERENCE_COHDOMAINEN_SHF 0
	312	#define CM_GCR_Cx_COHERENCE_COHDOMAINEN_MSK (_ULCAST_(0xff) << 0)
	313
	314	/* GCR_Cx_CONFIG register fields */
	315	#define CM_GCR_Cx_CONFIG_IOCUTYPE_SHF 10
	316	#define CM_GCR_Cx_CONFIG_IOCUTYPE_MSK (_ULCAST_(0x3) << 10)
	317	#define CM_GCR_Cx_CONFIG_PVPE_SHF 0
	318	#define CM_GCR_Cx_CONFIG_PVPE_MSK (_ULCAST_(0x1ff) << 0)
	319
	320	/* GCR_Cx_OTHER register fields */
	321	#define CM_GCR_Cx_OTHER_CORENUM_SHF 16
	322	#define CM_GCR_Cx_OTHER_CORENUM_MSK (_ULCAST_(0xffff) << 16)
	323
	324	/* GCR_Cx_RESET_BASE register fields */
	325	#define CM_GCR_Cx_RESET_BASE_BEVEXCBASE_SHF 12
	326	#define CM_GCR_Cx_RESET_BASE_BEVEXCBASE_MSK (_ULCAST_(0xfffff) << 12)
	327
	328	/* GCR_Cx_RESET_EXT_BASE register fields */
	329	#define CM_GCR_Cx_RESET_EXT_BASE_EVARESET_SHF 31
	330	#define CM_GCR_Cx_RESET_EXT_BASE_EVARESET_MSK (_ULCAST_(0x1) << 31)
	331	#define CM_GCR_Cx_RESET_EXT_BASE_UEB_SHF 30
	332	#define CM_GCR_Cx_RESET_EXT_BASE_UEB_MSK (_ULCAST_(0x1) << 30)
	333	#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK_SHF 20
	334	#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK_MSK (_ULCAST_(0xff) << 20)
	335	#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA_SHF 1
	336	#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA_MSK (_ULCAST_(0x7f) << 1)
	337	#define CM_GCR_Cx_RESET_EXT_BASE_PRESENT_SHF 0
	338	#define CM_GCR_Cx_RESET_EXT_BASE_PRESENT_MSK (_ULCAST_(0x1) << 0)
	339
	340	/**
	341	* mips_cm_numcores - return the number of cores present in the system
	342	*
	343	* Returns the value of the PCORES field of the GCR_CONFIG register plus 1, or
	344	* zero if no Coherence Manager is present.
	345	*/
	346	static inline unsigned mips_cm_numcores(void)
	347	{
	348	if (!mips_cm_present())
	349	return 0;
	350
	351	return ((read_gcr_config() & CM_GCR_CONFIG_PCORES_MSK)
	352	>> CM_GCR_CONFIG_PCORES_SHF) + 1;
	353	}
	354
	355	/**
	356	* mips_cm_numiocu - return the number of IOCUs present in the system
	357	*
	358	* Returns the value of the NUMIOCU field of the GCR_CONFIG register, or zero
	359	* if no Coherence Manager is present.
	360	*/
	361	static inline unsigned mips_cm_numiocu(void)
	362	{
	363	if (!mips_cm_present())
	364	return 0;
	365
	366	return (read_gcr_config() & CM_GCR_CONFIG_NUMIOCU_MSK)
	367	>> CM_GCR_CONFIG_NUMIOCU_SHF;
	368	}
	369
	370	/**
	371	* mips_cm_l2sync - perform an L2-only sync operation
	372	*
	373	* If an L2-only sync region is present in the system then this function
374	* performs and L2-only sync and returns zero. Otherwise it returns -ENODEV.
375	*/
376	static inline int mips_cm_l2sync(void)
377	{
378	if (!mips_cm_has_l2sync())
379	return -ENODEV;
380
381	writel(0, mips_cm_l2sync_base);
382	return 0;
383	}
384
197e89e0 PB	385	/**
	386	* mips_cm_revision() - return CM revision
	387	*
	388	* Return: The revision of the CM, from GCR_REV, or 0 if no CM is present. The
	389	* return value should be checked against the CM_REV_* macros.
	390	*/
	391	static inline int mips_cm_revision(void)
	392	{
	393	if (!mips_cm_present())
	394	return 0;
	395
	396	return read_gcr_rev();
	397	}
	398
9f98f3dd	399	#endif /* __MIPS_ASM_MIPS_CM_H__ */