[mirror_ubuntu-focal-kernel.git] / arch / mips / include / asm / mips-cm.h

/*
 * Copyright (C) 2013 Imagination Technologies
 * Author: Paul Burton <paul.burton@imgtec.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#ifndef __MIPS_ASM_MIPS_CM_H__
#define __MIPS_ASM_MIPS_CM_H__

#include <linux/bitops.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/types.h>
#include <asm/mips-cps.h>

/* The base address of the CM GCR block */
extern void __iomem *mips_gcr_base;

/* The base address of the CM L2-only sync region */
extern void __iomem *mips_cm_l2sync_base;

/**
 * __mips_cm_phys_base - retrieve the physical base address of the CM
 *
 * This function returns the physical base address of the Coherence Manager
 * global control block, or 0 if no Coherence Manager is present. It provides
 * a default implementation which reads the CMGCRBase register where available,
 * and may be overridden by platforms which determine this address in a
 * different way by defining a function with the same prototype except for the
 * name mips_cm_phys_base (without underscores).
 */
extern phys_addr_t __mips_cm_phys_base(void);

/*
 * mips_cm_is64 - determine CM register width
 *
 * The CM register width is determined by the version of the CM, with CM3
 * introducing 64 bit GCRs and all prior CM versions having 32 bit GCRs.
 * However we may run a kernel built for MIPS32 on a system with 64 bit GCRs,
 * or vice-versa. This variable indicates the width of the memory accesses
 * that the kernel will perform to GCRs, which may differ from the actual
 * width of the GCRs.
 *
 * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.
 */
extern int mips_cm_is64;

/**
 * mips_cm_error_report - Report CM cache errors
 */
#ifdef CONFIG_MIPS_CM
extern void mips_cm_error_report(void);
#else
static inline void mips_cm_error_report(void) {}
#endif

/**
 * mips_cm_probe - probe for a Coherence Manager
 *
 * Attempt to detect the presence of a Coherence Manager. Returns 0 if a CM
 * is successfully detected, else -errno.
 */
#ifdef CONFIG_MIPS_CM
extern int mips_cm_probe(void);
#else
static inline int mips_cm_probe(void)
{
	return -ENODEV;
}
#endif

/**
 * mips_cm_present - determine whether a Coherence Manager is present
 *
 * Returns true if a CM is present in the system, else false.
 */
static inline bool mips_cm_present(void)
{
#ifdef CONFIG_MIPS_CM
	return mips_gcr_base != NULL;
#else
	return false;
#endif
}

/**
 * mips_cm_has_l2sync - determine whether an L2-only sync region is present
 *
 * Returns true if the system implements an L2-only sync region, else false.
 */
static inline bool mips_cm_has_l2sync(void)
{
#ifdef CONFIG_MIPS_CM
	return mips_cm_l2sync_base != NULL;
#else
	return false;
#endif
}

/* Offsets to register blocks from the CM base address */
#define MIPS_CM_GCB_OFS		0x0000 /* Global Control Block */
#define MIPS_CM_CLCB_OFS	0x2000 /* Core Local Control Block */
#define MIPS_CM_COCB_OFS	0x4000 /* Core Other Control Block */
#define MIPS_CM_GDB_OFS		0x6000 /* Global Debug Block */

/* Total size of the CM memory mapped registers */
#define MIPS_CM_GCR_SIZE	0x8000

/* Size of the L2-only sync region */
#define MIPS_CM_L2SYNC_SIZE	0x1000

#define GCR_ACCESSOR_RO(sz, off, name)					\
	CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_GCB_OFS + off, name)		\
	CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, redir_##name)

#define GCR_ACCESSOR_RW(sz, off, name)					\
	CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_GCB_OFS + off, name)		\
	CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_COCB_OFS + off, redir_##name)

#define GCR_CX_ACCESSOR_RO(sz, off, name)				\
	CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name)	\
	CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name)

#define GCR_CX_ACCESSOR_RW(sz, off, name)				\
	CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name)	\
	CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name)

/* GCR_CONFIG - Information about the system */
GCR_ACCESSOR_RO(64, 0x000, config)
#define CM_GCR_CONFIG_CLUSTER_COH_CAPABLE	BIT_ULL(43)
#define CM_GCR_CONFIG_CLUSTER_ID		GENMASK_ULL(39, 32)
#define CM_GCR_CONFIG_NUM_CLUSTERS		GENMASK(29, 23)
#define CM_GCR_CONFIG_NUMIOCU			GENMASK(15, 8)
#define CM_GCR_CONFIG_PCORES			GENMASK(7, 0)

/* GCR_BASE - Base address of the Global Configuration Registers (GCRs) */
GCR_ACCESSOR_RW(64, 0x008, base)
#define CM_GCR_BASE_GCRBASE			GENMASK_ULL(47, 15)
#define CM_GCR_BASE_CMDEFTGT			GENMASK(1, 0)
#define  CM_GCR_BASE_CMDEFTGT_DISABLED		0
#define  CM_GCR_BASE_CMDEFTGT_MEM		1
#define  CM_GCR_BASE_CMDEFTGT_IOCU0		2
#define  CM_GCR_BASE_CMDEFTGT_IOCU1		3

/* GCR_ACCESS - Controls core/IOCU access to GCRs */
GCR_ACCESSOR_RW(32, 0x020, access)
#define CM_GCR_ACCESS_ACCESSEN			GENMASK(7, 0)

/* GCR_REV - Indicates the Coherence Manager revision */
GCR_ACCESSOR_RO(32, 0x030, rev)
#define CM_GCR_REV_MAJOR			GENMASK(15, 8)
#define CM_GCR_REV_MINOR			GENMASK(7, 0)

#define CM_ENCODE_REV(major, minor) \
		(((major) << __ffs(CM_GCR_REV_MAJOR)) | \
		 ((minor) << __ffs(CM_GCR_REV_MINOR)))

#define CM_REV_CM2				CM_ENCODE_REV(6, 0)
#define CM_REV_CM2_5				CM_ENCODE_REV(7, 0)
#define CM_REV_CM3				CM_ENCODE_REV(8, 0)
#define CM_REV_CM3_5				CM_ENCODE_REV(9, 0)

/* GCR_ERR_CONTROL - Control error checking logic */
GCR_ACCESSOR_RW(32, 0x038, err_control)
#define CM_GCR_ERR_CONTROL_L2_ECC_EN		BIT(1)
#define CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT	BIT(0)

/* GCR_ERR_MASK - Control which errors are reported as interrupts */
GCR_ACCESSOR_RW(64, 0x040, error_mask)

/* GCR_ERR_CAUSE - Indicates the type of error that occurred */
GCR_ACCESSOR_RW(64, 0x048, error_cause)
#define CM_GCR_ERROR_CAUSE_ERRTYPE		GENMASK(31, 27)
#define CM3_GCR_ERROR_CAUSE_ERRTYPE		GENMASK_ULL(63, 58)
#define CM_GCR_ERROR_CAUSE_ERRINFO		GENMASK(26, 0)

/* GCR_ERR_ADDR - Indicates the address associated with an error */
GCR_ACCESSOR_RW(64, 0x050, error_addr)

/* GCR_ERR_MULT - Indicates when multiple errors have occurred */
GCR_ACCESSOR_RW(64, 0x058, error_mult)
#define CM_GCR_ERROR_MULT_ERR2ND		GENMASK(4, 0)

/* GCR_L2_ONLY_SYNC_BASE - Base address of the L2 cache-only sync region */
GCR_ACCESSOR_RW(64, 0x070, l2_only_sync_base)
#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE	GENMASK(31, 12)
#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN		BIT(0)

/* GCR_GIC_BASE - Base address of the Global Interrupt Controller (GIC) */
GCR_ACCESSOR_RW(64, 0x080, gic_base)
#define CM_GCR_GIC_BASE_GICBASE			GENMASK(31, 17)
#define CM_GCR_GIC_BASE_GICEN			BIT(0)

/* GCR_CPC_BASE - Base address of the Cluster Power Controller (CPC) */
GCR_ACCESSOR_RW(64, 0x088, cpc_base)
#define CM_GCR_CPC_BASE_CPCBASE			GENMASK(31, 15)
#define CM_GCR_CPC_BASE_CPCEN			BIT(0)

/* GCR_REGn_BASE - Base addresses of CM address regions */
GCR_ACCESSOR_RW(64, 0x090, reg0_base)
GCR_ACCESSOR_RW(64, 0x0a0, reg1_base)
GCR_ACCESSOR_RW(64, 0x0b0, reg2_base)
GCR_ACCESSOR_RW(64, 0x0c0, reg3_base)
#define CM_GCR_REGn_BASE_BASEADDR		GENMASK(31, 16)

/* GCR_REGn_MASK - Size & destination of CM address regions */
GCR_ACCESSOR_RW(64, 0x098, reg0_mask)
GCR_ACCESSOR_RW(64, 0x0a8, reg1_mask)
GCR_ACCESSOR_RW(64, 0x0b8, reg2_mask)
GCR_ACCESSOR_RW(64, 0x0c8, reg3_mask)
#define CM_GCR_REGn_MASK_ADDRMASK		GENMASK(31, 16)
#define CM_GCR_REGn_MASK_CCAOVR			GENMASK(7, 5)
#define CM_GCR_REGn_MASK_CCAOVREN		BIT(4)
#define CM_GCR_REGn_MASK_DROPL2			BIT(2)
#define CM_GCR_REGn_MASK_CMTGT			GENMASK(1, 0)
#define  CM_GCR_REGn_MASK_CMTGT_DISABLED	0x0
#define  CM_GCR_REGn_MASK_CMTGT_MEM		0x1
#define  CM_GCR_REGn_MASK_CMTGT_IOCU0		0x2
#define  CM_GCR_REGn_MASK_CMTGT_IOCU1		0x3

/* GCR_GIC_STATUS - Indicates presence of a Global Interrupt Controller (GIC) */
GCR_ACCESSOR_RO(32, 0x0d0, gic_status)
#define CM_GCR_GIC_STATUS_EX			BIT(0)

/* GCR_CPC_STATUS - Indicates presence of a Cluster Power Controller (CPC) */
GCR_ACCESSOR_RO(32, 0x0f0, cpc_status)
#define CM_GCR_CPC_STATUS_EX			BIT(0)

/* GCR_L2_CONFIG - Indicates L2 cache configuration when Config5.L2C=1 */
GCR_ACCESSOR_RW(32, 0x130, l2_config)
#define CM_GCR_L2_CONFIG_BYPASS			BIT(20)
#define CM_GCR_L2_CONFIG_SET_SIZE		GENMASK(15, 12)
#define CM_GCR_L2_CONFIG_LINE_SIZE		GENMASK(11, 8)
#define CM_GCR_L2_CONFIG_ASSOC			GENMASK(7, 0)

/* GCR_SYS_CONFIG2 - Further information about the system */
GCR_ACCESSOR_RO(32, 0x150, sys_config2)
#define CM_GCR_SYS_CONFIG2_MAXVPW		GENMASK(3, 0)

/* GCR_L2_PFT_CONTROL - Controls hardware L2 prefetching */
GCR_ACCESSOR_RW(32, 0x300, l2_pft_control)
#define CM_GCR_L2_PFT_CONTROL_PAGEMASK		GENMASK(31, 12)
#define CM_GCR_L2_PFT_CONTROL_PFTEN		BIT(8)
#define CM_GCR_L2_PFT_CONTROL_NPFT		GENMASK(7, 0)

/* GCR_L2_PFT_CONTROL_B - Controls hardware L2 prefetching */
GCR_ACCESSOR_RW(32, 0x308, l2_pft_control_b)
#define CM_GCR_L2_PFT_CONTROL_B_CEN		BIT(8)
#define CM_GCR_L2_PFT_CONTROL_B_PORTID		GENMASK(7, 0)

/* GCR_L2SM_COP - L2 cache op state machine control */
GCR_ACCESSOR_RW(32, 0x620, l2sm_cop)
#define CM_GCR_L2SM_COP_PRESENT			BIT(31)
#define CM_GCR_L2SM_COP_RESULT			GENMASK(8, 6)
#define  CM_GCR_L2SM_COP_RESULT_DONTCARE	0
#define  CM_GCR_L2SM_COP_RESULT_DONE_OK		1
#define  CM_GCR_L2SM_COP_RESULT_DONE_ERROR	2
#define  CM_GCR_L2SM_COP_RESULT_ABORT_OK	3
#define  CM_GCR_L2SM_COP_RESULT_ABORT_ERROR	4
#define CM_GCR_L2SM_COP_RUNNING			BIT(5)
#define CM_GCR_L2SM_COP_TYPE			GENMASK(4, 2)
#define  CM_GCR_L2SM_COP_TYPE_IDX_WBINV		0
#define  CM_GCR_L2SM_COP_TYPE_IDX_STORETAG	1
#define  CM_GCR_L2SM_COP_TYPE_IDX_STORETAGDATA	2
#define  CM_GCR_L2SM_COP_TYPE_HIT_INV		4
#define  CM_GCR_L2SM_COP_TYPE_HIT_WBINV		5
#define  CM_GCR_L2SM_COP_TYPE_HIT_WB		6
#define  CM_GCR_L2SM_COP_TYPE_FETCHLOCK		7
#define CM_GCR_L2SM_COP_CMD			GENMASK(1, 0)
#define  CM_GCR_L2SM_COP_CMD_START		1	/* only when idle */
#define  CM_GCR_L2SM_COP_CMD_ABORT		3	/* only when running */

/* GCR_L2SM_TAG_ADDR_COP - L2 cache op state machine address control */
GCR_ACCESSOR_RW(64, 0x628, l2sm_tag_addr_cop)
#define CM_GCR_L2SM_TAG_ADDR_COP_NUM_LINES	GENMASK_ULL(63, 48)
#define CM_GCR_L2SM_TAG_ADDR_COP_START_TAG	GENMASK_ULL(47, 6)

/* GCR_BEV_BASE - Controls the location of the BEV for powered up cores */
GCR_ACCESSOR_RW(64, 0x680, bev_base)

/* GCR_Cx_RESET_RELEASE - Controls core reset for CM 1.x */
GCR_CX_ACCESSOR_RW(32, 0x000, reset_release)

/* GCR_Cx_COHERENCE - Controls core coherence */
GCR_CX_ACCESSOR_RW(32, 0x008, coherence)
#define CM_GCR_Cx_COHERENCE_COHDOMAINEN		GENMASK(7, 0)
#define CM3_GCR_Cx_COHERENCE_COHEN		BIT(0)

/* GCR_Cx_CONFIG - Information about a core's configuration */
GCR_CX_ACCESSOR_RO(32, 0x010, config)
#define CM_GCR_Cx_CONFIG_IOCUTYPE		GENMASK(11, 10)
#define CM_GCR_Cx_CONFIG_PVPE			GENMASK(9, 0)

/* GCR_Cx_OTHER - Configure the core-other/redirect GCR block */
GCR_CX_ACCESSOR_RW(32, 0x018, other)
#define CM_GCR_Cx_OTHER_CORENUM			GENMASK(31, 16)	/* CM < 3 */
#define CM_GCR_Cx_OTHER_CLUSTER_EN		BIT(31)		/* CM >= 3.5 */
#define CM_GCR_Cx_OTHER_GIC_EN			BIT(30)		/* CM >= 3.5 */
#define CM_GCR_Cx_OTHER_BLOCK			GENMASK(25, 24)	/* CM >= 3.5 */
#define  CM_GCR_Cx_OTHER_BLOCK_LOCAL		0
#define  CM_GCR_Cx_OTHER_BLOCK_GLOBAL		1
#define  CM_GCR_Cx_OTHER_BLOCK_USER		2
#define  CM_GCR_Cx_OTHER_BLOCK_GLOBAL_HIGH	3
#define CM_GCR_Cx_OTHER_CLUSTER			GENMASK(21, 16)	/* CM >= 3.5 */
#define CM3_GCR_Cx_OTHER_CORE			GENMASK(13, 8)	/* CM >= 3 */
#define  CM_GCR_Cx_OTHER_CORE_CM		32
#define CM3_GCR_Cx_OTHER_VP			GENMASK(2, 0)	/* CM >= 3 */

/* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */
GCR_CX_ACCESSOR_RW(32, 0x020, reset_base)
#define CM_GCR_Cx_RESET_BASE_BEVEXCBASE		GENMASK(31, 12)

/* GCR_Cx_ID - Identify the current core */
GCR_CX_ACCESSOR_RO(32, 0x028, id)
#define CM_GCR_Cx_ID_CLUSTER			GENMASK(15, 8)
#define CM_GCR_Cx_ID_CORE			GENMASK(7, 0)

/* GCR_Cx_RESET_EXT_BASE - Configure behaviour when cores reset or power up */
GCR_CX_ACCESSOR_RW(32, 0x030, reset_ext_base)
#define CM_GCR_Cx_RESET_EXT_BASE_EVARESET	BIT(31)
#define CM_GCR_Cx_RESET_EXT_BASE_UEB		BIT(30)
#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK	GENMASK(27, 20)
#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA	GENMASK(7, 1)
#define CM_GCR_Cx_RESET_EXT_BASE_PRESENT	BIT(0)

/**
 * mips_cm_numcores - return the number of cores present in the system
 *
 * Returns the value of the PCORES field of the GCR_CONFIG register plus 1, or
 * zero if no Coherence Manager is present.
 */
static inline unsigned mips_cm_numcores(void)
{
	if (!mips_cm_present())
		return 0;

	return ((read_gcr_config() & CM_GCR_CONFIG_PCORES)
		>> __ffs(CM_GCR_CONFIG_PCORES)) + 1;
}

/**
 * mips_cm_numiocu - return the number of IOCUs present in the system
 *
 * Returns the value of the NUMIOCU field of the GCR_CONFIG register, or zero
 * if no Coherence Manager is present.
 */
static inline unsigned mips_cm_numiocu(void)
{
	if (!mips_cm_present())
		return 0;

	return (read_gcr_config() & CM_GCR_CONFIG_NUMIOCU)
		>> __ffs(CM_GCR_CONFIG_NUMIOCU);
}

/**
 * mips_cm_l2sync - perform an L2-only sync operation
 *
 * If an L2-only sync region is present in the system then this function
 * performs and L2-only sync and returns zero. Otherwise it returns -ENODEV.
 */
static inline int mips_cm_l2sync(void)
{
	if (!mips_cm_has_l2sync())
		return -ENODEV;

	writel(0, mips_cm_l2sync_base);
	return 0;
}

/**
 * mips_cm_revision() - return CM revision
 *
 * Return: The revision of the CM, from GCR_REV, or 0 if no CM is present. The
 * return value should be checked against the CM_REV_* macros.
 */
static inline int mips_cm_revision(void)
{
	if (!mips_cm_present())
		return 0;

	return read_gcr_rev();
}

/**
 * mips_cm_max_vp_width() - return the width in bits of VP indices
 *
 * Return: the width, in bits, of VP indices in fields that combine core & VP
 * indices.
 */
static inline unsigned int mips_cm_max_vp_width(void)
{
	extern int smp_num_siblings;
	uint32_t cfg;

	if (mips_cm_revision() >= CM_REV_CM3)
		return read_gcr_sys_config2() & CM_GCR_SYS_CONFIG2_MAXVPW;

	if (mips_cm_present()) {
		/*
		 * We presume that all cores in the system will have the same
		 * number of VP(E)s, and if that ever changes then this will
		 * need revisiting.
		 */
		cfg = read_gcr_cl_config() & CM_GCR_Cx_CONFIG_PVPE;
		return (cfg >> __ffs(CM_GCR_Cx_CONFIG_PVPE)) + 1;
	}

	if (IS_ENABLED(CONFIG_SMP))
		return smp_num_siblings;

	return 1;
}

/**
 * mips_cm_vp_id() - calculate the hardware VP ID for a CPU
 * @cpu: the CPU whose VP ID to calculate
 *
 * Hardware such as the GIC uses identifiers for VPs which may not match the
 * CPU numbers used by Linux. This function calculates the hardware VP
 * identifier corresponding to a given CPU.
 *
 * Return: the VP ID for the CPU.
 */
static inline unsigned int mips_cm_vp_id(unsigned int cpu)
{
	unsigned int core = cpu_core(&cpu_data[cpu]);
	unsigned int vp = cpu_vpe_id(&cpu_data[cpu]);

	return (core * mips_cm_max_vp_width()) + vp;
}

#ifdef CONFIG_MIPS_CM

/**
 * mips_cm_lock_other - lock access to another core
 * @core: the other core to be accessed
 * @vp: the VP within the other core to be accessed
 *
 * Call before operating upon a core via the 'other' register region in
 * order to prevent the region being moved during access. Must be followed
 * by a call to mips_cm_unlock_other.
 */
extern void mips_cm_lock_other(unsigned int core, unsigned int vp);

/**
 * mips_cm_unlock_other - unlock access to another core
 *
 * Call after operating upon another core via the 'other' register region.
 * Must be called after mips_cm_lock_other.
 */
extern void mips_cm_unlock_other(void);

#else /* !CONFIG_MIPS_CM */

static inline void mips_cm_lock_other(unsigned int core, unsigned int vp) { }
static inline void mips_cm_unlock_other(void) { }

#endif /* !CONFIG_MIPS_CM */

#endif /* __MIPS_ASM_MIPS_CM_H__ */
Commit	Line	Data
9f98f3dd PB	1	/*
	2	* Copyright (C) 2013 Imagination Technologies
	3	* Author: Paul Burton <paul.burton@imgtec.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License as published by the
	7	* Free Software Foundation; either version 2 of the License, or (at your
	8	* option) any later version.
	9	*/
	10
	11	#ifndef __MIPS_ASM_MIPS_CM_H__
	12	#define __MIPS_ASM_MIPS_CM_H__
	13
47b26a46	14	#include <linux/bitops.h>
56d4c99b	15	#include <linux/errno.h>
9f98f3dd PB	16	#include <linux/io.h>
9f98f3dd PB	17	#include <linux/types.h>
b025d518	18	#include <asm/mips-cps.h>
9f98f3dd PB	19
9f98f3dd PB	20	/* The base address of the CM GCR block */
abe852ea	21	extern void __iomem *mips_gcr_base;
9f98f3dd PB	22
	23	/* The base address of the CM L2-only sync region */
	24	extern void __iomem *mips_cm_l2sync_base;
	25
	26	/**
	27	* __mips_cm_phys_base - retrieve the physical base address of the CM
	28	*
	29	* This function returns the physical base address of the Coherence Manager
	30	* global control block, or 0 if no Coherence Manager is present. It provides
	31	* a default implementation which reads the CMGCRBase register where available,
92a76f6d	32	* and may be overridden by platforms which determine this address in a
9f98f3dd PB	33	* different way by defining a function with the same prototype except for the
	34	* name mips_cm_phys_base (without underscores).
	35	*/
15d45cce	36	extern phys_addr_t __mips_cm_phys_base(void);
9f98f3dd	37
c0b584a2 MC	38	/*
	39	* mips_cm_is64 - determine CM register width
	40	*
7784494a PB	41	* The CM register width is determined by the version of the CM, with CM3
	42	* introducing 64 bit GCRs and all prior CM versions having 32 bit GCRs.
	43	* However we may run a kernel built for MIPS32 on a system with 64 bit GCRs,
	44	* or vice-versa. This variable indicates the width of the memory accesses
	45	* that the kernel will perform to GCRs, which may differ from the actual
	46	* width of the GCRs.
c0b584a2 MC	47	*
	48	* It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.
	49	*/
	50	extern int mips_cm_is64;
	51
3885c2b4 MC	52	/**
	53	* mips_cm_error_report - Report CM cache errors
	54	*/
	55	#ifdef CONFIG_MIPS_CM
	56	extern void mips_cm_error_report(void);
	57	#else
	58	static inline void mips_cm_error_report(void) {}
	59	#endif
	60
9f98f3dd PB	61	/**
	62	* mips_cm_probe - probe for a Coherence Manager
	63	*
	64	* Attempt to detect the presence of a Coherence Manager. Returns 0 if a CM
	65	* is successfully detected, else -errno.
	66	*/
	67	#ifdef CONFIG_MIPS_CM
	68	extern int mips_cm_probe(void);
	69	#else
	70	static inline int mips_cm_probe(void)
	71	{
	72	return -ENODEV;
	73	}
	74	#endif
	75
	76	/**
	77	* mips_cm_present - determine whether a Coherence Manager is present
	78	*
	79	* Returns true if a CM is present in the system, else false.
	80	*/
	81	static inline bool mips_cm_present(void)
	82	{
	83	#ifdef CONFIG_MIPS_CM
abe852ea	84	return mips_gcr_base != NULL;
9f98f3dd PB	85	#else
	86	return false;
	87	#endif
	88	}
	89
	90	/**
	91	* mips_cm_has_l2sync - determine whether an L2-only sync region is present
	92	*
	93	* Returns true if the system implements an L2-only sync region, else false.
	94	*/
	95	static inline bool mips_cm_has_l2sync(void)
	96	{
	97	#ifdef CONFIG_MIPS_CM
	98	return mips_cm_l2sync_base != NULL;
	99	#else
	100	return false;
	101	#endif
	102	}
	103
	104	/* Offsets to register blocks from the CM base address */
	105	#define MIPS_CM_GCB_OFS 0x0000 /* Global Control Block */
	106	#define MIPS_CM_CLCB_OFS 0x2000 /* Core Local Control Block */
	107	#define MIPS_CM_COCB_OFS 0x4000 /* Core Other Control Block */
	108	#define MIPS_CM_GDB_OFS 0x6000 /* Global Debug Block */
	109
	110	/* Total size of the CM memory mapped registers */
	111	#define MIPS_CM_GCR_SIZE 0x8000
	112
	113	/* Size of the L2-only sync region */
	114	#define MIPS_CM_L2SYNC_SIZE 0x1000
	115
b025d518	116	#define GCR_ACCESSOR_RO(sz, off, name) \
23cb600e PB	117	CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_GCB_OFS + off, name) \
23cb600e PB	118	CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, redir_##name)
9f98f3dd	119
b025d518	120	#define GCR_ACCESSOR_RW(sz, off, name) \
23cb600e PB	121	CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_GCB_OFS + off, name) \
23cb600e PB	122	CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_COCB_OFS + off, redir_##name)
9f98f3dd	123
b025d518 PB	124	#define GCR_CX_ACCESSOR_RO(sz, off, name) \
	125	CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name) \
	126	CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name)
9f98f3dd	127
b025d518 PB	128	#define GCR_CX_ACCESSOR_RW(sz, off, name) \
	129	CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name) \
	130	CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name)
9f98f3dd	131
93c5bba5	132	/* GCR_CONFIG - Information about the system */
b025d518	133	GCR_ACCESSOR_RO(64, 0x000, config)
23cb600e PB	134	#define CM_GCR_CONFIG_CLUSTER_COH_CAPABLE BIT_ULL(43)
	135	#define CM_GCR_CONFIG_CLUSTER_ID GENMASK_ULL(39, 32)
	136	#define CM_GCR_CONFIG_NUM_CLUSTERS GENMASK(29, 23)
93c5bba5 PB	137	#define CM_GCR_CONFIG_NUMIOCU GENMASK(15, 8)
	138	#define CM_GCR_CONFIG_PCORES GENMASK(7, 0)
	139
	140	/* GCR_BASE - Base address of the Global Configuration Registers (GCRs) */
b025d518	141	GCR_ACCESSOR_RW(64, 0x008, base)
93c5bba5 PB	142	#define CM_GCR_BASE_GCRBASE GENMASK_ULL(47, 15)
	143	#define CM_GCR_BASE_CMDEFTGT GENMASK(1, 0)
	144	#define CM_GCR_BASE_CMDEFTGT_DISABLED 0
	145	#define CM_GCR_BASE_CMDEFTGT_MEM 1
	146	#define CM_GCR_BASE_CMDEFTGT_IOCU0 2
	147	#define CM_GCR_BASE_CMDEFTGT_IOCU1 3
	148
	149	/* GCR_ACCESS - Controls core/IOCU access to GCRs */
b025d518	150	GCR_ACCESSOR_RW(32, 0x020, access)
93c5bba5 PB	151	#define CM_GCR_ACCESS_ACCESSEN GENMASK(7, 0)
	152
	153	/* GCR_REV - Indicates the Coherence Manager revision */
b025d518	154	GCR_ACCESSOR_RO(32, 0x030, rev)
93c5bba5 PB	155	#define CM_GCR_REV_MAJOR GENMASK(15, 8)
	156	#define CM_GCR_REV_MINOR GENMASK(7, 0)
	157
	158	#define CM_ENCODE_REV(major, minor) \
	159	(((major) << __ffs(CM_GCR_REV_MAJOR)) \| \
	160	((minor) << __ffs(CM_GCR_REV_MINOR)))
	161
	162	#define CM_REV_CM2 CM_ENCODE_REV(6, 0)
	163	#define CM_REV_CM2_5 CM_ENCODE_REV(7, 0)
	164	#define CM_REV_CM3 CM_ENCODE_REV(8, 0)
23cb600e	165	#define CM_REV_CM3_5 CM_ENCODE_REV(9, 0)
93c5bba5 PB	166
93c5bba5 PB	167	/* GCR_ERR_CONTROL - Control error checking logic */
b025d518	168	GCR_ACCESSOR_RW(32, 0x038, err_control)
93c5bba5 PB	169	#define CM_GCR_ERR_CONTROL_L2_ECC_EN BIT(1)
	170	#define CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT BIT(0)
	171
	172	/* GCR_ERR_MASK - Control which errors are reported as interrupts */
b025d518	173	GCR_ACCESSOR_RW(64, 0x040, error_mask)
93c5bba5 PB	174
93c5bba5 PB	175	/* GCR_ERR_CAUSE - Indicates the type of error that occurred */
b025d518	176	GCR_ACCESSOR_RW(64, 0x048, error_cause)
93c5bba5 PB	177	#define CM_GCR_ERROR_CAUSE_ERRTYPE GENMASK(31, 27)
	178	#define CM3_GCR_ERROR_CAUSE_ERRTYPE GENMASK_ULL(63, 58)
	179	#define CM_GCR_ERROR_CAUSE_ERRINFO GENMASK(26, 0)
	180
	181	/* GCR_ERR_ADDR - Indicates the address associated with an error */
b025d518	182	GCR_ACCESSOR_RW(64, 0x050, error_addr)
93c5bba5 PB	183
93c5bba5 PB	184	/* GCR_ERR_MULT - Indicates when multiple errors have occurred */
b025d518	185	GCR_ACCESSOR_RW(64, 0x058, error_mult)
93c5bba5 PB	186	#define CM_GCR_ERROR_MULT_ERR2ND GENMASK(4, 0)
	187
	188	/* GCR_L2_ONLY_SYNC_BASE - Base address of the L2 cache-only sync region */
b025d518	189	GCR_ACCESSOR_RW(64, 0x070, l2_only_sync_base)
93c5bba5 PB	190	#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE GENMASK(31, 12)
	191	#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN BIT(0)
	192
	193	/* GCR_GIC_BASE - Base address of the Global Interrupt Controller (GIC) */
b025d518	194	GCR_ACCESSOR_RW(64, 0x080, gic_base)
93c5bba5 PB	195	#define CM_GCR_GIC_BASE_GICBASE GENMASK(31, 17)
	196	#define CM_GCR_GIC_BASE_GICEN BIT(0)
	197
	198	/* GCR_CPC_BASE - Base address of the Cluster Power Controller (CPC) */
b025d518	199	GCR_ACCESSOR_RW(64, 0x088, cpc_base)
93c5bba5 PB	200	#define CM_GCR_CPC_BASE_CPCBASE GENMASK(31, 15)
	201	#define CM_GCR_CPC_BASE_CPCEN BIT(0)
	202
	203	/* GCR_REGn_BASE - Base addresses of CM address regions */
b025d518	204	GCR_ACCESSOR_RW(64, 0x090, reg0_base)
b025d518	205	GCR_ACCESSOR_RW(64, 0x0a0, reg1_base)
b025d518	206	GCR_ACCESSOR_RW(64, 0x0b0, reg2_base)
b025d518	207	GCR_ACCESSOR_RW(64, 0x0c0, reg3_base)
93c5bba5 PB	208	#define CM_GCR_REGn_BASE_BASEADDR GENMASK(31, 16)
	209
	210	/* GCR_REGn_MASK - Size & destination of CM address regions */
	211	GCR_ACCESSOR_RW(64, 0x098, reg0_mask)
	212	GCR_ACCESSOR_RW(64, 0x0a8, reg1_mask)
	213	GCR_ACCESSOR_RW(64, 0x0b8, reg2_mask)
b025d518	214	GCR_ACCESSOR_RW(64, 0x0c8, reg3_mask)
93c5bba5 PB	215	#define CM_GCR_REGn_MASK_ADDRMASK GENMASK(31, 16)
	216	#define CM_GCR_REGn_MASK_CCAOVR GENMASK(7, 5)
	217	#define CM_GCR_REGn_MASK_CCAOVREN BIT(4)
	218	#define CM_GCR_REGn_MASK_DROPL2 BIT(2)
	219	#define CM_GCR_REGn_MASK_CMTGT GENMASK(1, 0)
	220	#define CM_GCR_REGn_MASK_CMTGT_DISABLED 0x0
	221	#define CM_GCR_REGn_MASK_CMTGT_MEM 0x1
	222	#define CM_GCR_REGn_MASK_CMTGT_IOCU0 0x2
	223	#define CM_GCR_REGn_MASK_CMTGT_IOCU1 0x3
	224
	225	/* GCR_GIC_STATUS - Indicates presence of a Global Interrupt Controller (GIC) */
b025d518	226	GCR_ACCESSOR_RO(32, 0x0d0, gic_status)
93c5bba5 PB	227	#define CM_GCR_GIC_STATUS_EX BIT(0)
	228
	229	/* GCR_CPC_STATUS - Indicates presence of a Cluster Power Controller (CPC) */
b025d518	230	GCR_ACCESSOR_RO(32, 0x0f0, cpc_status)
93c5bba5 PB	231	#define CM_GCR_CPC_STATUS_EX BIT(0)
	232
	233	/* GCR_L2_CONFIG - Indicates L2 cache configuration when Config5.L2C=1 */
b025d518	234	GCR_ACCESSOR_RW(32, 0x130, l2_config)
93c5bba5 PB	235	#define CM_GCR_L2_CONFIG_BYPASS BIT(20)
	236	#define CM_GCR_L2_CONFIG_SET_SIZE GENMASK(15, 12)
	237	#define CM_GCR_L2_CONFIG_LINE_SIZE GENMASK(11, 8)
	238	#define CM_GCR_L2_CONFIG_ASSOC GENMASK(7, 0)
	239
	240	/* GCR_SYS_CONFIG2 - Further information about the system */
b025d518	241	GCR_ACCESSOR_RO(32, 0x150, sys_config2)
93c5bba5 PB	242	#define CM_GCR_SYS_CONFIG2_MAXVPW GENMASK(3, 0)
	243
	244	/* GCR_L2_PFT_CONTROL - Controls hardware L2 prefetching */
b025d518	245	GCR_ACCESSOR_RW(32, 0x300, l2_pft_control)
93c5bba5 PB	246	#define CM_GCR_L2_PFT_CONTROL_PAGEMASK GENMASK(31, 12)
	247	#define CM_GCR_L2_PFT_CONTROL_PFTEN BIT(8)
	248	#define CM_GCR_L2_PFT_CONTROL_NPFT GENMASK(7, 0)
	249
	250	/* GCR_L2_PFT_CONTROL_B - Controls hardware L2 prefetching */
b025d518	251	GCR_ACCESSOR_RW(32, 0x308, l2_pft_control_b)
93c5bba5 PB	252	#define CM_GCR_L2_PFT_CONTROL_B_CEN BIT(8)
	253	#define CM_GCR_L2_PFT_CONTROL_B_PORTID GENMASK(7, 0)
	254
23cb600e PB	255	/* GCR_L2SM_COP - L2 cache op state machine control */
	256	GCR_ACCESSOR_RW(32, 0x620, l2sm_cop)
	257	#define CM_GCR_L2SM_COP_PRESENT BIT(31)
	258	#define CM_GCR_L2SM_COP_RESULT GENMASK(8, 6)
	259	#define CM_GCR_L2SM_COP_RESULT_DONTCARE 0
	260	#define CM_GCR_L2SM_COP_RESULT_DONE_OK 1
	261	#define CM_GCR_L2SM_COP_RESULT_DONE_ERROR 2
	262	#define CM_GCR_L2SM_COP_RESULT_ABORT_OK 3
	263	#define CM_GCR_L2SM_COP_RESULT_ABORT_ERROR 4
	264	#define CM_GCR_L2SM_COP_RUNNING BIT(5)
	265	#define CM_GCR_L2SM_COP_TYPE GENMASK(4, 2)
	266	#define CM_GCR_L2SM_COP_TYPE_IDX_WBINV 0
	267	#define CM_GCR_L2SM_COP_TYPE_IDX_STORETAG 1
	268	#define CM_GCR_L2SM_COP_TYPE_IDX_STORETAGDATA 2
	269	#define CM_GCR_L2SM_COP_TYPE_HIT_INV 4
	270	#define CM_GCR_L2SM_COP_TYPE_HIT_WBINV 5
	271	#define CM_GCR_L2SM_COP_TYPE_HIT_WB 6
	272	#define CM_GCR_L2SM_COP_TYPE_FETCHLOCK 7
	273	#define CM_GCR_L2SM_COP_CMD GENMASK(1, 0)
	274	#define CM_GCR_L2SM_COP_CMD_START 1 /* only when idle */
	275	#define CM_GCR_L2SM_COP_CMD_ABORT 3 /* only when running */
	276
	277	/* GCR_L2SM_TAG_ADDR_COP - L2 cache op state machine address control */
	278	GCR_ACCESSOR_RW(64, 0x628, l2sm_tag_addr_cop)
	279	#define CM_GCR_L2SM_TAG_ADDR_COP_NUM_LINES GENMASK_ULL(63, 48)
	280	#define CM_GCR_L2SM_TAG_ADDR_COP_START_TAG GENMASK_ULL(47, 6)
	281
93c5bba5	282	/* GCR_BEV_BASE - Controls the location of the BEV for powered up cores */
b025d518	283	GCR_ACCESSOR_RW(64, 0x680, bev_base)
9f98f3dd	284
93c5bba5	285	/* GCR_Cx_RESET_RELEASE - Controls core reset for CM 1.x */
b025d518	286	GCR_CX_ACCESSOR_RW(32, 0x000, reset_release)
9f98f3dd	287
93c5bba5 PB	288	/* GCR_Cx_COHERENCE - Controls core coherence */
	289	GCR_CX_ACCESSOR_RW(32, 0x008, coherence)
	290	#define CM_GCR_Cx_COHERENCE_COHDOMAINEN GENMASK(7, 0)
	291	#define CM3_GCR_Cx_COHERENCE_COHEN BIT(0)
497e803e	292
93c5bba5 PB	293	/* GCR_Cx_CONFIG - Information about a core's configuration */
	294	GCR_CX_ACCESSOR_RO(32, 0x010, config)
	295	#define CM_GCR_Cx_CONFIG_IOCUTYPE GENMASK(11, 10)
	296	#define CM_GCR_Cx_CONFIG_PVPE GENMASK(9, 0)
9f98f3dd	297
93c5bba5 PB	298	/* GCR_Cx_OTHER - Configure the core-other/redirect GCR block */
93c5bba5 PB	299	GCR_CX_ACCESSOR_RW(32, 0x018, other)
23cb600e PB	300	#define CM_GCR_Cx_OTHER_CORENUM GENMASK(31, 16) /* CM < 3 */
	301	#define CM_GCR_Cx_OTHER_CLUSTER_EN BIT(31) /* CM >= 3.5 */
	302	#define CM_GCR_Cx_OTHER_GIC_EN BIT(30) /* CM >= 3.5 */
	303	#define CM_GCR_Cx_OTHER_BLOCK GENMASK(25, 24) /* CM >= 3.5 */
	304	#define CM_GCR_Cx_OTHER_BLOCK_LOCAL 0
	305	#define CM_GCR_Cx_OTHER_BLOCK_GLOBAL 1
	306	#define CM_GCR_Cx_OTHER_BLOCK_USER 2
	307	#define CM_GCR_Cx_OTHER_BLOCK_GLOBAL_HIGH 3
	308	#define CM_GCR_Cx_OTHER_CLUSTER GENMASK(21, 16) /* CM >= 3.5 */
	309	#define CM3_GCR_Cx_OTHER_CORE GENMASK(13, 8) /* CM >= 3 */
	310	#define CM_GCR_Cx_OTHER_CORE_CM 32
	311	#define CM3_GCR_Cx_OTHER_VP GENMASK(2, 0) /* CM >= 3 */
9f98f3dd	312
93c5bba5 PB	313	/* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */
	314	GCR_CX_ACCESSOR_RW(32, 0x020, reset_base)
	315	#define CM_GCR_Cx_RESET_BASE_BEVEXCBASE GENMASK(31, 12)
197e89e0	316
93c5bba5 PB	317	/* GCR_Cx_ID - Identify the current core */
93c5bba5 PB	318	GCR_CX_ACCESSOR_RO(32, 0x028, id)
23cb600e PB	319	#define CM_GCR_Cx_ID_CLUSTER GENMASK(15, 8)
23cb600e PB	320	#define CM_GCR_Cx_ID_CORE GENMASK(7, 0)
197e89e0	321
93c5bba5 PB	322	/* GCR_Cx_RESET_EXT_BASE - Configure behaviour when cores reset or power up */
	323	GCR_CX_ACCESSOR_RW(32, 0x030, reset_ext_base)
	324	#define CM_GCR_Cx_RESET_EXT_BASE_EVARESET BIT(31)
	325	#define CM_GCR_Cx_RESET_EXT_BASE_UEB BIT(30)
	326	#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK GENMASK(27, 20)
	327	#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA GENMASK(7, 1)
	328	#define CM_GCR_Cx_RESET_EXT_BASE_PRESENT BIT(0)
9f98f3dd PB	329
	330	/**
	331	* mips_cm_numcores - return the number of cores present in the system
	332	*
	333	* Returns the value of the PCORES field of the GCR_CONFIG register plus 1, or
	334	* zero if no Coherence Manager is present.
	335	*/
	336	static inline unsigned mips_cm_numcores(void)
	337	{
	338	if (!mips_cm_present())
	339	return 0;
	340
93c5bba5 PB	341	return ((read_gcr_config() & CM_GCR_CONFIG_PCORES)
93c5bba5 PB	342	>> __ffs(CM_GCR_CONFIG_PCORES)) + 1;
9f98f3dd PB	343	}
	344
	345	/**
	346	* mips_cm_numiocu - return the number of IOCUs present in the system
	347	*
	348	* Returns the value of the NUMIOCU field of the GCR_CONFIG register, or zero
	349	* if no Coherence Manager is present.
	350	*/
	351	static inline unsigned mips_cm_numiocu(void)
	352	{
	353	if (!mips_cm_present())
	354	return 0;
	355
93c5bba5 PB	356	return (read_gcr_config() & CM_GCR_CONFIG_NUMIOCU)
93c5bba5 PB	357	>> __ffs(CM_GCR_CONFIG_NUMIOCU);
9f98f3dd PB	358	}
	359
	360	/**
	361	* mips_cm_l2sync - perform an L2-only sync operation
	362	*
	363	* If an L2-only sync region is present in the system then this function
	364	* performs and L2-only sync and returns zero. Otherwise it returns -ENODEV.
	365	*/
	366	static inline int mips_cm_l2sync(void)
	367	{
	368	if (!mips_cm_has_l2sync())
	369	return -ENODEV;
	370
	371	writel(0, mips_cm_l2sync_base);
	372	return 0;
	373	}
	374
197e89e0 PB	375	/**
	376	* mips_cm_revision() - return CM revision
	377	*
	378	* Return: The revision of the CM, from GCR_REV, or 0 if no CM is present. The
	379	* return value should be checked against the CM_REV_* macros.
	380	*/
	381	static inline int mips_cm_revision(void)
	382	{
	383	if (!mips_cm_present())
	384	return 0;
	385
	386	return read_gcr_rev();
	387	}
	388
7573b94e PB	389	/**
	390	* mips_cm_max_vp_width() - return the width in bits of VP indices
	391	*
	392	* Return: the width, in bits, of VP indices in fields that combine core & VP
	393	* indices.
	394	*/
	395	static inline unsigned int mips_cm_max_vp_width(void)
	396	{
	397	extern int smp_num_siblings;
6605d156	398	uint32_t cfg;
7573b94e PB	399
7573b94e PB	400	if (mips_cm_revision() >= CM_REV_CM3)
93c5bba5	401	return read_gcr_sys_config2() & CM_GCR_SYS_CONFIG2_MAXVPW;
7573b94e	402
6605d156 PB	403	if (mips_cm_present()) {
	404	/*
	405	* We presume that all cores in the system will have the same
	406	* number of VP(E)s, and if that ever changes then this will
	407	* need revisiting.
	408	*/
93c5bba5 PB	409	cfg = read_gcr_cl_config() & CM_GCR_Cx_CONFIG_PVPE;
93c5bba5 PB	410	return (cfg >> __ffs(CM_GCR_Cx_CONFIG_PVPE)) + 1;
6605d156 PB	411	}
6605d156 PB	412
97f2645f	413	if (IS_ENABLED(CONFIG_SMP))
a60ae81e PB	414	return smp_num_siblings;
	415
	416	return 1;
7573b94e PB	417	}
	418
	419	/**
	420	* mips_cm_vp_id() - calculate the hardware VP ID for a CPU
	421	* @cpu: the CPU whose VP ID to calculate
	422	*
	423	* Hardware such as the GIC uses identifiers for VPs which may not match the
	424	* CPU numbers used by Linux. This function calculates the hardware VP
	425	* identifier corresponding to a given CPU.
	426	*
	427	* Return: the VP ID for the CPU.
	428	*/
	429	static inline unsigned int mips_cm_vp_id(unsigned int cpu)
	430	{
f875a832	431	unsigned int core = cpu_core(&cpu_data[cpu]);
7573b94e PB	432	unsigned int vp = cpu_vpe_id(&cpu_data[cpu]);
	433
	434	return (core * mips_cm_max_vp_width()) + vp;
	435	}
	436
23d5de8e PB	437	#ifdef CONFIG_MIPS_CM
	438
	439	/**
	440	* mips_cm_lock_other - lock access to another core
	441	* @core: the other core to be accessed
	442	* @vp: the VP within the other core to be accessed
	443	*
	444	* Call before operating upon a core via the 'other' register region in
	445	* order to prevent the region being moved during access. Must be followed
	446	* by a call to mips_cm_unlock_other.
	447	*/
	448	extern void mips_cm_lock_other(unsigned int core, unsigned int vp);
	449
	450	/**
	451	* mips_cm_unlock_other - unlock access to another core
	452	*
	453	* Call after operating upon another core via the 'other' register region.
	454	* Must be called after mips_cm_lock_other.
	455	*/
	456	extern void mips_cm_unlock_other(void);
	457
	458	#else /* !CONFIG_MIPS_CM */
	459
0868971a	460	static inline void mips_cm_lock_other(unsigned int core, unsigned int vp) { }
23d5de8e PB	461	static inline void mips_cm_unlock_other(void) { }
	462
	463	#endif /* !CONFIG_MIPS_CM */
	464
9f98f3dd	465	#endif /* __MIPS_ASM_MIPS_CM_H__ */