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1 | /* |
2 | * Copyright (C) 2013 Imagination Technologies | |
3 | * Author: Paul Burton <paul.burton@imgtec.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2 of the License, or (at your | |
8 | * option) any later version. | |
9 | */ | |
10 | ||
11 | #ifndef __MIPS_ASM_MIPS_CM_H__ | |
12 | #define __MIPS_ASM_MIPS_CM_H__ | |
13 | ||
14 | #include <linux/io.h> | |
15 | #include <linux/types.h> | |
16 | ||
17 | /* The base address of the CM GCR block */ | |
18 | extern void __iomem *mips_cm_base; | |
19 | ||
20 | /* The base address of the CM L2-only sync region */ | |
21 | extern void __iomem *mips_cm_l2sync_base; | |
22 | ||
23 | /** | |
24 | * __mips_cm_phys_base - retrieve the physical base address of the CM | |
25 | * | |
26 | * This function returns the physical base address of the Coherence Manager | |
27 | * global control block, or 0 if no Coherence Manager is present. It provides | |
28 | * a default implementation which reads the CMGCRBase register where available, | |
29 | * and may be overriden by platforms which determine this address in a | |
30 | * different way by defining a function with the same prototype except for the | |
31 | * name mips_cm_phys_base (without underscores). | |
32 | */ | |
15d45cce | 33 | extern phys_addr_t __mips_cm_phys_base(void); |
9f98f3dd PB |
34 | |
35 | /** | |
36 | * mips_cm_probe - probe for a Coherence Manager | |
37 | * | |
38 | * Attempt to detect the presence of a Coherence Manager. Returns 0 if a CM | |
39 | * is successfully detected, else -errno. | |
40 | */ | |
41 | #ifdef CONFIG_MIPS_CM | |
42 | extern int mips_cm_probe(void); | |
43 | #else | |
44 | static inline int mips_cm_probe(void) | |
45 | { | |
46 | return -ENODEV; | |
47 | } | |
48 | #endif | |
49 | ||
50 | /** | |
51 | * mips_cm_present - determine whether a Coherence Manager is present | |
52 | * | |
53 | * Returns true if a CM is present in the system, else false. | |
54 | */ | |
55 | static inline bool mips_cm_present(void) | |
56 | { | |
57 | #ifdef CONFIG_MIPS_CM | |
58 | return mips_cm_base != NULL; | |
59 | #else | |
60 | return false; | |
61 | #endif | |
62 | } | |
63 | ||
64 | /** | |
65 | * mips_cm_has_l2sync - determine whether an L2-only sync region is present | |
66 | * | |
67 | * Returns true if the system implements an L2-only sync region, else false. | |
68 | */ | |
69 | static inline bool mips_cm_has_l2sync(void) | |
70 | { | |
71 | #ifdef CONFIG_MIPS_CM | |
72 | return mips_cm_l2sync_base != NULL; | |
73 | #else | |
74 | return false; | |
75 | #endif | |
76 | } | |
77 | ||
78 | /* Offsets to register blocks from the CM base address */ | |
79 | #define MIPS_CM_GCB_OFS 0x0000 /* Global Control Block */ | |
80 | #define MIPS_CM_CLCB_OFS 0x2000 /* Core Local Control Block */ | |
81 | #define MIPS_CM_COCB_OFS 0x4000 /* Core Other Control Block */ | |
82 | #define MIPS_CM_GDB_OFS 0x6000 /* Global Debug Block */ | |
83 | ||
84 | /* Total size of the CM memory mapped registers */ | |
85 | #define MIPS_CM_GCR_SIZE 0x8000 | |
86 | ||
87 | /* Size of the L2-only sync region */ | |
88 | #define MIPS_CM_L2SYNC_SIZE 0x1000 | |
89 | ||
90 | /* Macros to ease the creation of register access functions */ | |
91 | #define BUILD_CM_R_(name, off) \ | |
50083928 | 92 | static inline u32 __iomem *addr_gcr_##name(void) \ |
9f98f3dd | 93 | { \ |
50083928 | 94 | return (u32 __iomem *)(mips_cm_base + (off)); \ |
9f98f3dd PB |
95 | } \ |
96 | \ | |
97 | static inline u32 read_gcr_##name(void) \ | |
98 | { \ | |
cd217546 | 99 | return __raw_readl(addr_gcr_##name()); \ |
9f98f3dd PB |
100 | } |
101 | ||
102 | #define BUILD_CM__W(name, off) \ | |
103 | static inline void write_gcr_##name(u32 value) \ | |
104 | { \ | |
cd217546 | 105 | __raw_writel(value, addr_gcr_##name()); \ |
9f98f3dd PB |
106 | } |
107 | ||
108 | #define BUILD_CM_RW(name, off) \ | |
109 | BUILD_CM_R_(name, off) \ | |
110 | BUILD_CM__W(name, off) | |
111 | ||
112 | #define BUILD_CM_Cx_R_(name, off) \ | |
113 | BUILD_CM_R_(cl_##name, MIPS_CM_CLCB_OFS + (off)) \ | |
114 | BUILD_CM_R_(co_##name, MIPS_CM_COCB_OFS + (off)) | |
115 | ||
116 | #define BUILD_CM_Cx__W(name, off) \ | |
117 | BUILD_CM__W(cl_##name, MIPS_CM_CLCB_OFS + (off)) \ | |
118 | BUILD_CM__W(co_##name, MIPS_CM_COCB_OFS + (off)) | |
119 | ||
120 | #define BUILD_CM_Cx_RW(name, off) \ | |
121 | BUILD_CM_Cx_R_(name, off) \ | |
122 | BUILD_CM_Cx__W(name, off) | |
123 | ||
124 | /* GCB register accessor functions */ | |
125 | BUILD_CM_R_(config, MIPS_CM_GCB_OFS + 0x00) | |
126 | BUILD_CM_RW(base, MIPS_CM_GCB_OFS + 0x08) | |
127 | BUILD_CM_RW(access, MIPS_CM_GCB_OFS + 0x20) | |
128 | BUILD_CM_R_(rev, MIPS_CM_GCB_OFS + 0x30) | |
129 | BUILD_CM_RW(error_mask, MIPS_CM_GCB_OFS + 0x40) | |
130 | BUILD_CM_RW(error_cause, MIPS_CM_GCB_OFS + 0x48) | |
131 | BUILD_CM_RW(error_addr, MIPS_CM_GCB_OFS + 0x50) | |
132 | BUILD_CM_RW(error_mult, MIPS_CM_GCB_OFS + 0x58) | |
133 | BUILD_CM_RW(l2_only_sync_base, MIPS_CM_GCB_OFS + 0x70) | |
134 | BUILD_CM_RW(gic_base, MIPS_CM_GCB_OFS + 0x80) | |
135 | BUILD_CM_RW(cpc_base, MIPS_CM_GCB_OFS + 0x88) | |
136 | BUILD_CM_RW(reg0_base, MIPS_CM_GCB_OFS + 0x90) | |
137 | BUILD_CM_RW(reg0_mask, MIPS_CM_GCB_OFS + 0x98) | |
138 | BUILD_CM_RW(reg1_base, MIPS_CM_GCB_OFS + 0xa0) | |
139 | BUILD_CM_RW(reg1_mask, MIPS_CM_GCB_OFS + 0xa8) | |
140 | BUILD_CM_RW(reg2_base, MIPS_CM_GCB_OFS + 0xb0) | |
141 | BUILD_CM_RW(reg2_mask, MIPS_CM_GCB_OFS + 0xb8) | |
142 | BUILD_CM_RW(reg3_base, MIPS_CM_GCB_OFS + 0xc0) | |
143 | BUILD_CM_RW(reg3_mask, MIPS_CM_GCB_OFS + 0xc8) | |
144 | BUILD_CM_R_(gic_status, MIPS_CM_GCB_OFS + 0xd0) | |
145 | BUILD_CM_R_(cpc_status, MIPS_CM_GCB_OFS + 0xf0) | |
146 | ||
147 | /* Core Local & Core Other register accessor functions */ | |
148 | BUILD_CM_Cx_RW(reset_release, 0x00) | |
149 | BUILD_CM_Cx_RW(coherence, 0x08) | |
150 | BUILD_CM_Cx_R_(config, 0x10) | |
151 | BUILD_CM_Cx_RW(other, 0x18) | |
152 | BUILD_CM_Cx_RW(reset_base, 0x20) | |
153 | BUILD_CM_Cx_R_(id, 0x28) | |
154 | BUILD_CM_Cx_RW(reset_ext_base, 0x30) | |
155 | BUILD_CM_Cx_R_(tcid_0_priority, 0x40) | |
156 | BUILD_CM_Cx_R_(tcid_1_priority, 0x48) | |
157 | BUILD_CM_Cx_R_(tcid_2_priority, 0x50) | |
158 | BUILD_CM_Cx_R_(tcid_3_priority, 0x58) | |
159 | BUILD_CM_Cx_R_(tcid_4_priority, 0x60) | |
160 | BUILD_CM_Cx_R_(tcid_5_priority, 0x68) | |
161 | BUILD_CM_Cx_R_(tcid_6_priority, 0x70) | |
162 | BUILD_CM_Cx_R_(tcid_7_priority, 0x78) | |
163 | BUILD_CM_Cx_R_(tcid_8_priority, 0x80) | |
164 | ||
165 | /* GCR_CONFIG register fields */ | |
166 | #define CM_GCR_CONFIG_NUMIOCU_SHF 8 | |
167 | #define CM_GCR_CONFIG_NUMIOCU_MSK (_ULCAST_(0xf) << 8) | |
168 | #define CM_GCR_CONFIG_PCORES_SHF 0 | |
169 | #define CM_GCR_CONFIG_PCORES_MSK (_ULCAST_(0xff) << 0) | |
170 | ||
171 | /* GCR_BASE register fields */ | |
172 | #define CM_GCR_BASE_GCRBASE_SHF 15 | |
173 | #define CM_GCR_BASE_GCRBASE_MSK (_ULCAST_(0x1ffff) << 15) | |
174 | #define CM_GCR_BASE_CMDEFTGT_SHF 0 | |
175 | #define CM_GCR_BASE_CMDEFTGT_MSK (_ULCAST_(0x3) << 0) | |
176 | #define CM_GCR_BASE_CMDEFTGT_DISABLED 0 | |
177 | #define CM_GCR_BASE_CMDEFTGT_MEM 1 | |
178 | #define CM_GCR_BASE_CMDEFTGT_IOCU0 2 | |
179 | #define CM_GCR_BASE_CMDEFTGT_IOCU1 3 | |
180 | ||
181 | /* GCR_ACCESS register fields */ | |
182 | #define CM_GCR_ACCESS_ACCESSEN_SHF 0 | |
183 | #define CM_GCR_ACCESS_ACCESSEN_MSK (_ULCAST_(0xff) << 0) | |
184 | ||
185 | /* GCR_REV register fields */ | |
186 | #define CM_GCR_REV_MAJOR_SHF 8 | |
187 | #define CM_GCR_REV_MAJOR_MSK (_ULCAST_(0xff) << 8) | |
188 | #define CM_GCR_REV_MINOR_SHF 0 | |
189 | #define CM_GCR_REV_MINOR_MSK (_ULCAST_(0xff) << 0) | |
190 | ||
191 | /* GCR_ERROR_CAUSE register fields */ | |
192 | #define CM_GCR_ERROR_CAUSE_ERRTYPE_SHF 27 | |
193 | #define CM_GCR_ERROR_CAUSE_ERRTYPE_MSK (_ULCAST_(0x1f) << 27) | |
194 | #define CM_GCR_ERROR_CAUSE_ERRINFO_SHF 0 | |
195 | #define CM_GCR_ERROR_CAUSE_ERRINGO_MSK (_ULCAST_(0x7ffffff) << 0) | |
196 | ||
197 | /* GCR_ERROR_MULT register fields */ | |
198 | #define CM_GCR_ERROR_MULT_ERR2ND_SHF 0 | |
199 | #define CM_GCR_ERROR_MULT_ERR2ND_MSK (_ULCAST_(0x1f) << 0) | |
200 | ||
201 | /* GCR_L2_ONLY_SYNC_BASE register fields */ | |
202 | #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_SHF 12 | |
203 | #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK (_ULCAST_(0xfffff) << 12) | |
204 | #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_SHF 0 | |
205 | #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK (_ULCAST_(0x1) << 0) | |
206 | ||
207 | /* GCR_GIC_BASE register fields */ | |
208 | #define CM_GCR_GIC_BASE_GICBASE_SHF 17 | |
209 | #define CM_GCR_GIC_BASE_GICBASE_MSK (_ULCAST_(0x7fff) << 17) | |
210 | #define CM_GCR_GIC_BASE_GICEN_SHF 0 | |
211 | #define CM_GCR_GIC_BASE_GICEN_MSK (_ULCAST_(0x1) << 0) | |
212 | ||
213 | /* GCR_CPC_BASE register fields */ | |
214 | #define CM_GCR_CPC_BASE_CPCBASE_SHF 17 | |
215 | #define CM_GCR_CPC_BASE_CPCBASE_MSK (_ULCAST_(0x7fff) << 17) | |
216 | #define CM_GCR_CPC_BASE_CPCEN_SHF 0 | |
217 | #define CM_GCR_CPC_BASE_CPCEN_MSK (_ULCAST_(0x1) << 0) | |
218 | ||
921d55e3 PB |
219 | /* GCR_GIC_STATUS register fields */ |
220 | #define CM_GCR_GIC_STATUS_GICEX_SHF 0 | |
221 | #define CM_GCR_GIC_STATUS_GICEX_MSK (_ULCAST_(0x1) << 0) | |
222 | ||
9f98f3dd PB |
223 | /* GCR_REGn_BASE register fields */ |
224 | #define CM_GCR_REGn_BASE_BASEADDR_SHF 16 | |
225 | #define CM_GCR_REGn_BASE_BASEADDR_MSK (_ULCAST_(0xffff) << 16) | |
226 | ||
227 | /* GCR_REGn_MASK register fields */ | |
228 | #define CM_GCR_REGn_MASK_ADDRMASK_SHF 16 | |
229 | #define CM_GCR_REGn_MASK_ADDRMASK_MSK (_ULCAST_(0xffff) << 16) | |
230 | #define CM_GCR_REGn_MASK_CCAOVR_SHF 5 | |
231 | #define CM_GCR_REGn_MASK_CCAOVR_MSK (_ULCAST_(0x3) << 5) | |
232 | #define CM_GCR_REGn_MASK_CCAOVREN_SHF 4 | |
233 | #define CM_GCR_REGn_MASK_CCAOVREN_MSK (_ULCAST_(0x1) << 4) | |
234 | #define CM_GCR_REGn_MASK_DROPL2_SHF 2 | |
235 | #define CM_GCR_REGn_MASK_DROPL2_MSK (_ULCAST_(0x1) << 2) | |
236 | #define CM_GCR_REGn_MASK_CMTGT_SHF 0 | |
237 | #define CM_GCR_REGn_MASK_CMTGT_MSK (_ULCAST_(0x3) << 0) | |
238 | #define CM_GCR_REGn_MASK_CMTGT_DISABLED (_ULCAST_(0x0) << 0) | |
239 | #define CM_GCR_REGn_MASK_CMTGT_MEM (_ULCAST_(0x1) << 0) | |
240 | #define CM_GCR_REGn_MASK_CMTGT_IOCU0 (_ULCAST_(0x2) << 0) | |
241 | #define CM_GCR_REGn_MASK_CMTGT_IOCU1 (_ULCAST_(0x3) << 0) | |
242 | ||
243 | /* GCR_GIC_STATUS register fields */ | |
244 | #define CM_GCR_GIC_STATUS_EX_SHF 0 | |
245 | #define CM_GCR_GIC_STATUS_EX_MSK (_ULCAST_(0x1) << 0) | |
246 | ||
247 | /* GCR_CPC_STATUS register fields */ | |
248 | #define CM_GCR_CPC_STATUS_EX_SHF 0 | |
249 | #define CM_GCR_CPC_STATUS_EX_MSK (_ULCAST_(0x1) << 0) | |
250 | ||
251 | /* GCR_Cx_COHERENCE register fields */ | |
252 | #define CM_GCR_Cx_COHERENCE_COHDOMAINEN_SHF 0 | |
253 | #define CM_GCR_Cx_COHERENCE_COHDOMAINEN_MSK (_ULCAST_(0xff) << 0) | |
254 | ||
255 | /* GCR_Cx_CONFIG register fields */ | |
256 | #define CM_GCR_Cx_CONFIG_IOCUTYPE_SHF 10 | |
257 | #define CM_GCR_Cx_CONFIG_IOCUTYPE_MSK (_ULCAST_(0x3) << 10) | |
258 | #define CM_GCR_Cx_CONFIG_PVPE_SHF 0 | |
259 | #define CM_GCR_Cx_CONFIG_PVPE_MSK (_ULCAST_(0x1ff) << 0) | |
260 | ||
261 | /* GCR_Cx_OTHER register fields */ | |
262 | #define CM_GCR_Cx_OTHER_CORENUM_SHF 16 | |
263 | #define CM_GCR_Cx_OTHER_CORENUM_MSK (_ULCAST_(0xffff) << 16) | |
264 | ||
265 | /* GCR_Cx_RESET_BASE register fields */ | |
266 | #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE_SHF 12 | |
267 | #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE_MSK (_ULCAST_(0xfffff) << 12) | |
268 | ||
269 | /* GCR_Cx_RESET_EXT_BASE register fields */ | |
270 | #define CM_GCR_Cx_RESET_EXT_BASE_EVARESET_SHF 31 | |
271 | #define CM_GCR_Cx_RESET_EXT_BASE_EVARESET_MSK (_ULCAST_(0x1) << 31) | |
272 | #define CM_GCR_Cx_RESET_EXT_BASE_UEB_SHF 30 | |
273 | #define CM_GCR_Cx_RESET_EXT_BASE_UEB_MSK (_ULCAST_(0x1) << 30) | |
274 | #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK_SHF 20 | |
275 | #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK_MSK (_ULCAST_(0xff) << 20) | |
276 | #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA_SHF 1 | |
277 | #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA_MSK (_ULCAST_(0x7f) << 1) | |
278 | #define CM_GCR_Cx_RESET_EXT_BASE_PRESENT_SHF 0 | |
279 | #define CM_GCR_Cx_RESET_EXT_BASE_PRESENT_MSK (_ULCAST_(0x1) << 0) | |
280 | ||
281 | /** | |
282 | * mips_cm_numcores - return the number of cores present in the system | |
283 | * | |
284 | * Returns the value of the PCORES field of the GCR_CONFIG register plus 1, or | |
285 | * zero if no Coherence Manager is present. | |
286 | */ | |
287 | static inline unsigned mips_cm_numcores(void) | |
288 | { | |
289 | if (!mips_cm_present()) | |
290 | return 0; | |
291 | ||
292 | return ((read_gcr_config() & CM_GCR_CONFIG_PCORES_MSK) | |
293 | >> CM_GCR_CONFIG_PCORES_SHF) + 1; | |
294 | } | |
295 | ||
296 | /** | |
297 | * mips_cm_numiocu - return the number of IOCUs present in the system | |
298 | * | |
299 | * Returns the value of the NUMIOCU field of the GCR_CONFIG register, or zero | |
300 | * if no Coherence Manager is present. | |
301 | */ | |
302 | static inline unsigned mips_cm_numiocu(void) | |
303 | { | |
304 | if (!mips_cm_present()) | |
305 | return 0; | |
306 | ||
307 | return (read_gcr_config() & CM_GCR_CONFIG_NUMIOCU_MSK) | |
308 | >> CM_GCR_CONFIG_NUMIOCU_SHF; | |
309 | } | |
310 | ||
311 | /** | |
312 | * mips_cm_l2sync - perform an L2-only sync operation | |
313 | * | |
314 | * If an L2-only sync region is present in the system then this function | |
315 | * performs and L2-only sync and returns zero. Otherwise it returns -ENODEV. | |
316 | */ | |
317 | static inline int mips_cm_l2sync(void) | |
318 | { | |
319 | if (!mips_cm_has_l2sync()) | |
320 | return -ENODEV; | |
321 | ||
322 | writel(0, mips_cm_l2sync_base); | |
323 | return 0; | |
324 | } | |
325 | ||
326 | #endif /* __MIPS_ASM_MIPS_CM_H__ */ |