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9f98f3dd PB |
1 | /* |
2 | * Copyright (C) 2013 Imagination Technologies | |
3 | * Author: Paul Burton <paul.burton@imgtec.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2 of the License, or (at your | |
8 | * option) any later version. | |
9 | */ | |
10 | ||
11 | #ifndef __MIPS_ASM_MIPS_CM_H__ | |
12 | #define __MIPS_ASM_MIPS_CM_H__ | |
13 | ||
56d4c99b | 14 | #include <linux/errno.h> |
9f98f3dd PB |
15 | #include <linux/io.h> |
16 | #include <linux/types.h> | |
17 | ||
18 | /* The base address of the CM GCR block */ | |
19 | extern void __iomem *mips_cm_base; | |
20 | ||
21 | /* The base address of the CM L2-only sync region */ | |
22 | extern void __iomem *mips_cm_l2sync_base; | |
23 | ||
24 | /** | |
25 | * __mips_cm_phys_base - retrieve the physical base address of the CM | |
26 | * | |
27 | * This function returns the physical base address of the Coherence Manager | |
28 | * global control block, or 0 if no Coherence Manager is present. It provides | |
29 | * a default implementation which reads the CMGCRBase register where available, | |
30 | * and may be overriden by platforms which determine this address in a | |
31 | * different way by defining a function with the same prototype except for the | |
32 | * name mips_cm_phys_base (without underscores). | |
33 | */ | |
15d45cce | 34 | extern phys_addr_t __mips_cm_phys_base(void); |
9f98f3dd | 35 | |
c0b584a2 MC |
36 | /* |
37 | * mips_cm_is64 - determine CM register width | |
38 | * | |
7784494a PB |
39 | * The CM register width is determined by the version of the CM, with CM3 |
40 | * introducing 64 bit GCRs and all prior CM versions having 32 bit GCRs. | |
41 | * However we may run a kernel built for MIPS32 on a system with 64 bit GCRs, | |
42 | * or vice-versa. This variable indicates the width of the memory accesses | |
43 | * that the kernel will perform to GCRs, which may differ from the actual | |
44 | * width of the GCRs. | |
c0b584a2 MC |
45 | * |
46 | * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses. | |
47 | */ | |
48 | extern int mips_cm_is64; | |
49 | ||
3885c2b4 MC |
50 | /** |
51 | * mips_cm_error_report - Report CM cache errors | |
52 | */ | |
53 | #ifdef CONFIG_MIPS_CM | |
54 | extern void mips_cm_error_report(void); | |
55 | #else | |
56 | static inline void mips_cm_error_report(void) {} | |
57 | #endif | |
58 | ||
9f98f3dd PB |
59 | /** |
60 | * mips_cm_probe - probe for a Coherence Manager | |
61 | * | |
62 | * Attempt to detect the presence of a Coherence Manager. Returns 0 if a CM | |
63 | * is successfully detected, else -errno. | |
64 | */ | |
65 | #ifdef CONFIG_MIPS_CM | |
66 | extern int mips_cm_probe(void); | |
67 | #else | |
68 | static inline int mips_cm_probe(void) | |
69 | { | |
70 | return -ENODEV; | |
71 | } | |
72 | #endif | |
73 | ||
74 | /** | |
75 | * mips_cm_present - determine whether a Coherence Manager is present | |
76 | * | |
77 | * Returns true if a CM is present in the system, else false. | |
78 | */ | |
79 | static inline bool mips_cm_present(void) | |
80 | { | |
81 | #ifdef CONFIG_MIPS_CM | |
82 | return mips_cm_base != NULL; | |
83 | #else | |
84 | return false; | |
85 | #endif | |
86 | } | |
87 | ||
88 | /** | |
89 | * mips_cm_has_l2sync - determine whether an L2-only sync region is present | |
90 | * | |
91 | * Returns true if the system implements an L2-only sync region, else false. | |
92 | */ | |
93 | static inline bool mips_cm_has_l2sync(void) | |
94 | { | |
95 | #ifdef CONFIG_MIPS_CM | |
96 | return mips_cm_l2sync_base != NULL; | |
97 | #else | |
98 | return false; | |
99 | #endif | |
100 | } | |
101 | ||
102 | /* Offsets to register blocks from the CM base address */ | |
103 | #define MIPS_CM_GCB_OFS 0x0000 /* Global Control Block */ | |
104 | #define MIPS_CM_CLCB_OFS 0x2000 /* Core Local Control Block */ | |
105 | #define MIPS_CM_COCB_OFS 0x4000 /* Core Other Control Block */ | |
106 | #define MIPS_CM_GDB_OFS 0x6000 /* Global Debug Block */ | |
107 | ||
108 | /* Total size of the CM memory mapped registers */ | |
109 | #define MIPS_CM_GCR_SIZE 0x8000 | |
110 | ||
111 | /* Size of the L2-only sync region */ | |
112 | #define MIPS_CM_L2SYNC_SIZE 0x1000 | |
113 | ||
114 | /* Macros to ease the creation of register access functions */ | |
115 | #define BUILD_CM_R_(name, off) \ | |
c0b584a2 | 116 | static inline unsigned long __iomem *addr_gcr_##name(void) \ |
9f98f3dd | 117 | { \ |
c0b584a2 | 118 | return (unsigned long __iomem *)(mips_cm_base + (off)); \ |
9f98f3dd PB |
119 | } \ |
120 | \ | |
c0b584a2 | 121 | static inline u32 read32_gcr_##name(void) \ |
9f98f3dd | 122 | { \ |
cd217546 | 123 | return __raw_readl(addr_gcr_##name()); \ |
c0b584a2 MC |
124 | } \ |
125 | \ | |
126 | static inline u64 read64_gcr_##name(void) \ | |
127 | { \ | |
b657a628 PB |
128 | void __iomem *addr = addr_gcr_##name(); \ |
129 | u64 ret; \ | |
130 | \ | |
131 | if (mips_cm_is64) { \ | |
132 | ret = __raw_readq(addr); \ | |
133 | } else { \ | |
134 | ret = __raw_readl(addr); \ | |
135 | ret |= (u64)__raw_readl(addr + 0x4) << 32; \ | |
136 | } \ | |
137 | \ | |
138 | return ret; \ | |
c0b584a2 MC |
139 | } \ |
140 | \ | |
141 | static inline unsigned long read_gcr_##name(void) \ | |
142 | { \ | |
143 | if (mips_cm_is64) \ | |
144 | return read64_gcr_##name(); \ | |
145 | else \ | |
146 | return read32_gcr_##name(); \ | |
9f98f3dd PB |
147 | } |
148 | ||
149 | #define BUILD_CM__W(name, off) \ | |
c0b584a2 | 150 | static inline void write32_gcr_##name(u32 value) \ |
9f98f3dd | 151 | { \ |
cd217546 | 152 | __raw_writel(value, addr_gcr_##name()); \ |
c0b584a2 MC |
153 | } \ |
154 | \ | |
155 | static inline void write64_gcr_##name(u64 value) \ | |
156 | { \ | |
157 | __raw_writeq(value, addr_gcr_##name()); \ | |
158 | } \ | |
159 | \ | |
160 | static inline void write_gcr_##name(unsigned long value) \ | |
161 | { \ | |
162 | if (mips_cm_is64) \ | |
163 | write64_gcr_##name(value); \ | |
164 | else \ | |
165 | write32_gcr_##name(value); \ | |
9f98f3dd PB |
166 | } |
167 | ||
168 | #define BUILD_CM_RW(name, off) \ | |
169 | BUILD_CM_R_(name, off) \ | |
170 | BUILD_CM__W(name, off) | |
171 | ||
172 | #define BUILD_CM_Cx_R_(name, off) \ | |
173 | BUILD_CM_R_(cl_##name, MIPS_CM_CLCB_OFS + (off)) \ | |
174 | BUILD_CM_R_(co_##name, MIPS_CM_COCB_OFS + (off)) | |
175 | ||
176 | #define BUILD_CM_Cx__W(name, off) \ | |
177 | BUILD_CM__W(cl_##name, MIPS_CM_CLCB_OFS + (off)) \ | |
178 | BUILD_CM__W(co_##name, MIPS_CM_COCB_OFS + (off)) | |
179 | ||
180 | #define BUILD_CM_Cx_RW(name, off) \ | |
181 | BUILD_CM_Cx_R_(name, off) \ | |
182 | BUILD_CM_Cx__W(name, off) | |
183 | ||
184 | /* GCB register accessor functions */ | |
185 | BUILD_CM_R_(config, MIPS_CM_GCB_OFS + 0x00) | |
186 | BUILD_CM_RW(base, MIPS_CM_GCB_OFS + 0x08) | |
187 | BUILD_CM_RW(access, MIPS_CM_GCB_OFS + 0x20) | |
188 | BUILD_CM_R_(rev, MIPS_CM_GCB_OFS + 0x30) | |
189 | BUILD_CM_RW(error_mask, MIPS_CM_GCB_OFS + 0x40) | |
190 | BUILD_CM_RW(error_cause, MIPS_CM_GCB_OFS + 0x48) | |
191 | BUILD_CM_RW(error_addr, MIPS_CM_GCB_OFS + 0x50) | |
192 | BUILD_CM_RW(error_mult, MIPS_CM_GCB_OFS + 0x58) | |
193 | BUILD_CM_RW(l2_only_sync_base, MIPS_CM_GCB_OFS + 0x70) | |
194 | BUILD_CM_RW(gic_base, MIPS_CM_GCB_OFS + 0x80) | |
195 | BUILD_CM_RW(cpc_base, MIPS_CM_GCB_OFS + 0x88) | |
196 | BUILD_CM_RW(reg0_base, MIPS_CM_GCB_OFS + 0x90) | |
197 | BUILD_CM_RW(reg0_mask, MIPS_CM_GCB_OFS + 0x98) | |
198 | BUILD_CM_RW(reg1_base, MIPS_CM_GCB_OFS + 0xa0) | |
199 | BUILD_CM_RW(reg1_mask, MIPS_CM_GCB_OFS + 0xa8) | |
200 | BUILD_CM_RW(reg2_base, MIPS_CM_GCB_OFS + 0xb0) | |
201 | BUILD_CM_RW(reg2_mask, MIPS_CM_GCB_OFS + 0xb8) | |
202 | BUILD_CM_RW(reg3_base, MIPS_CM_GCB_OFS + 0xc0) | |
203 | BUILD_CM_RW(reg3_mask, MIPS_CM_GCB_OFS + 0xc8) | |
204 | BUILD_CM_R_(gic_status, MIPS_CM_GCB_OFS + 0xd0) | |
205 | BUILD_CM_R_(cpc_status, MIPS_CM_GCB_OFS + 0xf0) | |
0ba3c125 | 206 | BUILD_CM_RW(l2_config, MIPS_CM_GCB_OFS + 0x130) |
7573b94e | 207 | BUILD_CM_RW(sys_config2, MIPS_CM_GCB_OFS + 0x150) |
4d035516 PB |
208 | BUILD_CM_RW(l2_pft_control, MIPS_CM_GCB_OFS + 0x300) |
209 | BUILD_CM_RW(l2_pft_control_b, MIPS_CM_GCB_OFS + 0x308) | |
9f98f3dd PB |
210 | |
211 | /* Core Local & Core Other register accessor functions */ | |
212 | BUILD_CM_Cx_RW(reset_release, 0x00) | |
213 | BUILD_CM_Cx_RW(coherence, 0x08) | |
214 | BUILD_CM_Cx_R_(config, 0x10) | |
215 | BUILD_CM_Cx_RW(other, 0x18) | |
216 | BUILD_CM_Cx_RW(reset_base, 0x20) | |
217 | BUILD_CM_Cx_R_(id, 0x28) | |
218 | BUILD_CM_Cx_RW(reset_ext_base, 0x30) | |
219 | BUILD_CM_Cx_R_(tcid_0_priority, 0x40) | |
220 | BUILD_CM_Cx_R_(tcid_1_priority, 0x48) | |
221 | BUILD_CM_Cx_R_(tcid_2_priority, 0x50) | |
222 | BUILD_CM_Cx_R_(tcid_3_priority, 0x58) | |
223 | BUILD_CM_Cx_R_(tcid_4_priority, 0x60) | |
224 | BUILD_CM_Cx_R_(tcid_5_priority, 0x68) | |
225 | BUILD_CM_Cx_R_(tcid_6_priority, 0x70) | |
226 | BUILD_CM_Cx_R_(tcid_7_priority, 0x78) | |
227 | BUILD_CM_Cx_R_(tcid_8_priority, 0x80) | |
228 | ||
229 | /* GCR_CONFIG register fields */ | |
230 | #define CM_GCR_CONFIG_NUMIOCU_SHF 8 | |
231 | #define CM_GCR_CONFIG_NUMIOCU_MSK (_ULCAST_(0xf) << 8) | |
232 | #define CM_GCR_CONFIG_PCORES_SHF 0 | |
233 | #define CM_GCR_CONFIG_PCORES_MSK (_ULCAST_(0xff) << 0) | |
234 | ||
235 | /* GCR_BASE register fields */ | |
236 | #define CM_GCR_BASE_GCRBASE_SHF 15 | |
237 | #define CM_GCR_BASE_GCRBASE_MSK (_ULCAST_(0x1ffff) << 15) | |
238 | #define CM_GCR_BASE_CMDEFTGT_SHF 0 | |
239 | #define CM_GCR_BASE_CMDEFTGT_MSK (_ULCAST_(0x3) << 0) | |
240 | #define CM_GCR_BASE_CMDEFTGT_DISABLED 0 | |
241 | #define CM_GCR_BASE_CMDEFTGT_MEM 1 | |
242 | #define CM_GCR_BASE_CMDEFTGT_IOCU0 2 | |
243 | #define CM_GCR_BASE_CMDEFTGT_IOCU1 3 | |
244 | ||
245 | /* GCR_ACCESS register fields */ | |
246 | #define CM_GCR_ACCESS_ACCESSEN_SHF 0 | |
247 | #define CM_GCR_ACCESS_ACCESSEN_MSK (_ULCAST_(0xff) << 0) | |
248 | ||
249 | /* GCR_REV register fields */ | |
250 | #define CM_GCR_REV_MAJOR_SHF 8 | |
251 | #define CM_GCR_REV_MAJOR_MSK (_ULCAST_(0xff) << 8) | |
252 | #define CM_GCR_REV_MINOR_SHF 0 | |
253 | #define CM_GCR_REV_MINOR_MSK (_ULCAST_(0xff) << 0) | |
254 | ||
197e89e0 PB |
255 | #define CM_ENCODE_REV(major, minor) \ |
256 | (((major) << CM_GCR_REV_MAJOR_SHF) | \ | |
257 | ((minor) << CM_GCR_REV_MINOR_SHF)) | |
258 | ||
259 | #define CM_REV_CM2 CM_ENCODE_REV(6, 0) | |
4d035516 | 260 | #define CM_REV_CM2_5 CM_ENCODE_REV(7, 0) |
197e89e0 PB |
261 | #define CM_REV_CM3 CM_ENCODE_REV(8, 0) |
262 | ||
9f98f3dd PB |
263 | /* GCR_ERROR_CAUSE register fields */ |
264 | #define CM_GCR_ERROR_CAUSE_ERRTYPE_SHF 27 | |
265 | #define CM_GCR_ERROR_CAUSE_ERRTYPE_MSK (_ULCAST_(0x1f) << 27) | |
266 | #define CM_GCR_ERROR_CAUSE_ERRINFO_SHF 0 | |
267 | #define CM_GCR_ERROR_CAUSE_ERRINGO_MSK (_ULCAST_(0x7ffffff) << 0) | |
268 | ||
269 | /* GCR_ERROR_MULT register fields */ | |
270 | #define CM_GCR_ERROR_MULT_ERR2ND_SHF 0 | |
271 | #define CM_GCR_ERROR_MULT_ERR2ND_MSK (_ULCAST_(0x1f) << 0) | |
272 | ||
273 | /* GCR_L2_ONLY_SYNC_BASE register fields */ | |
274 | #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_SHF 12 | |
275 | #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK (_ULCAST_(0xfffff) << 12) | |
276 | #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_SHF 0 | |
277 | #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK (_ULCAST_(0x1) << 0) | |
278 | ||
279 | /* GCR_GIC_BASE register fields */ | |
280 | #define CM_GCR_GIC_BASE_GICBASE_SHF 17 | |
281 | #define CM_GCR_GIC_BASE_GICBASE_MSK (_ULCAST_(0x7fff) << 17) | |
282 | #define CM_GCR_GIC_BASE_GICEN_SHF 0 | |
283 | #define CM_GCR_GIC_BASE_GICEN_MSK (_ULCAST_(0x1) << 0) | |
284 | ||
285 | /* GCR_CPC_BASE register fields */ | |
286 | #define CM_GCR_CPC_BASE_CPCBASE_SHF 17 | |
287 | #define CM_GCR_CPC_BASE_CPCBASE_MSK (_ULCAST_(0x7fff) << 17) | |
288 | #define CM_GCR_CPC_BASE_CPCEN_SHF 0 | |
289 | #define CM_GCR_CPC_BASE_CPCEN_MSK (_ULCAST_(0x1) << 0) | |
290 | ||
921d55e3 PB |
291 | /* GCR_GIC_STATUS register fields */ |
292 | #define CM_GCR_GIC_STATUS_GICEX_SHF 0 | |
293 | #define CM_GCR_GIC_STATUS_GICEX_MSK (_ULCAST_(0x1) << 0) | |
294 | ||
9f98f3dd PB |
295 | /* GCR_REGn_BASE register fields */ |
296 | #define CM_GCR_REGn_BASE_BASEADDR_SHF 16 | |
297 | #define CM_GCR_REGn_BASE_BASEADDR_MSK (_ULCAST_(0xffff) << 16) | |
298 | ||
299 | /* GCR_REGn_MASK register fields */ | |
300 | #define CM_GCR_REGn_MASK_ADDRMASK_SHF 16 | |
301 | #define CM_GCR_REGn_MASK_ADDRMASK_MSK (_ULCAST_(0xffff) << 16) | |
302 | #define CM_GCR_REGn_MASK_CCAOVR_SHF 5 | |
303 | #define CM_GCR_REGn_MASK_CCAOVR_MSK (_ULCAST_(0x3) << 5) | |
304 | #define CM_GCR_REGn_MASK_CCAOVREN_SHF 4 | |
305 | #define CM_GCR_REGn_MASK_CCAOVREN_MSK (_ULCAST_(0x1) << 4) | |
306 | #define CM_GCR_REGn_MASK_DROPL2_SHF 2 | |
307 | #define CM_GCR_REGn_MASK_DROPL2_MSK (_ULCAST_(0x1) << 2) | |
308 | #define CM_GCR_REGn_MASK_CMTGT_SHF 0 | |
309 | #define CM_GCR_REGn_MASK_CMTGT_MSK (_ULCAST_(0x3) << 0) | |
310 | #define CM_GCR_REGn_MASK_CMTGT_DISABLED (_ULCAST_(0x0) << 0) | |
311 | #define CM_GCR_REGn_MASK_CMTGT_MEM (_ULCAST_(0x1) << 0) | |
312 | #define CM_GCR_REGn_MASK_CMTGT_IOCU0 (_ULCAST_(0x2) << 0) | |
313 | #define CM_GCR_REGn_MASK_CMTGT_IOCU1 (_ULCAST_(0x3) << 0) | |
314 | ||
315 | /* GCR_GIC_STATUS register fields */ | |
316 | #define CM_GCR_GIC_STATUS_EX_SHF 0 | |
317 | #define CM_GCR_GIC_STATUS_EX_MSK (_ULCAST_(0x1) << 0) | |
318 | ||
319 | /* GCR_CPC_STATUS register fields */ | |
320 | #define CM_GCR_CPC_STATUS_EX_SHF 0 | |
321 | #define CM_GCR_CPC_STATUS_EX_MSK (_ULCAST_(0x1) << 0) | |
322 | ||
0ba3c125 PB |
323 | /* GCR_L2_CONFIG register fields */ |
324 | #define CM_GCR_L2_CONFIG_BYPASS_SHF 20 | |
325 | #define CM_GCR_L2_CONFIG_BYPASS_MSK (_ULCAST_(0x1) << 20) | |
326 | #define CM_GCR_L2_CONFIG_SET_SIZE_SHF 12 | |
327 | #define CM_GCR_L2_CONFIG_SET_SIZE_MSK (_ULCAST_(0xf) << 12) | |
328 | #define CM_GCR_L2_CONFIG_LINE_SIZE_SHF 8 | |
329 | #define CM_GCR_L2_CONFIG_LINE_SIZE_MSK (_ULCAST_(0xf) << 8) | |
330 | #define CM_GCR_L2_CONFIG_ASSOC_SHF 0 | |
331 | #define CM_GCR_L2_CONFIG_ASSOC_MSK (_ULCAST_(0xff) << 0) | |
332 | ||
7573b94e PB |
333 | /* GCR_SYS_CONFIG2 register fields */ |
334 | #define CM_GCR_SYS_CONFIG2_MAXVPW_SHF 0 | |
335 | #define CM_GCR_SYS_CONFIG2_MAXVPW_MSK (_ULCAST_(0xf) << 0) | |
336 | ||
4d035516 PB |
337 | /* GCR_L2_PFT_CONTROL register fields */ |
338 | #define CM_GCR_L2_PFT_CONTROL_PAGEMASK_SHF 12 | |
339 | #define CM_GCR_L2_PFT_CONTROL_PAGEMASK_MSK (_ULCAST_(0xfffff) << 12) | |
340 | #define CM_GCR_L2_PFT_CONTROL_PFTEN_SHF 8 | |
341 | #define CM_GCR_L2_PFT_CONTROL_PFTEN_MSK (_ULCAST_(0x1) << 8) | |
342 | #define CM_GCR_L2_PFT_CONTROL_NPFT_SHF 0 | |
343 | #define CM_GCR_L2_PFT_CONTROL_NPFT_MSK (_ULCAST_(0xff) << 0) | |
344 | ||
345 | /* GCR_L2_PFT_CONTROL_B register fields */ | |
346 | #define CM_GCR_L2_PFT_CONTROL_B_CEN_SHF 8 | |
347 | #define CM_GCR_L2_PFT_CONTROL_B_CEN_MSK (_ULCAST_(0x1) << 8) | |
348 | #define CM_GCR_L2_PFT_CONTROL_B_PORTID_SHF 0 | |
349 | #define CM_GCR_L2_PFT_CONTROL_B_PORTID_MSK (_ULCAST_(0xff) << 0) | |
350 | ||
9f98f3dd PB |
351 | /* GCR_Cx_COHERENCE register fields */ |
352 | #define CM_GCR_Cx_COHERENCE_COHDOMAINEN_SHF 0 | |
353 | #define CM_GCR_Cx_COHERENCE_COHDOMAINEN_MSK (_ULCAST_(0xff) << 0) | |
354 | ||
355 | /* GCR_Cx_CONFIG register fields */ | |
356 | #define CM_GCR_Cx_CONFIG_IOCUTYPE_SHF 10 | |
357 | #define CM_GCR_Cx_CONFIG_IOCUTYPE_MSK (_ULCAST_(0x3) << 10) | |
358 | #define CM_GCR_Cx_CONFIG_PVPE_SHF 0 | |
359 | #define CM_GCR_Cx_CONFIG_PVPE_MSK (_ULCAST_(0x1ff) << 0) | |
360 | ||
361 | /* GCR_Cx_OTHER register fields */ | |
362 | #define CM_GCR_Cx_OTHER_CORENUM_SHF 16 | |
363 | #define CM_GCR_Cx_OTHER_CORENUM_MSK (_ULCAST_(0xffff) << 16) | |
364 | ||
365 | /* GCR_Cx_RESET_BASE register fields */ | |
366 | #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE_SHF 12 | |
367 | #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE_MSK (_ULCAST_(0xfffff) << 12) | |
368 | ||
369 | /* GCR_Cx_RESET_EXT_BASE register fields */ | |
370 | #define CM_GCR_Cx_RESET_EXT_BASE_EVARESET_SHF 31 | |
371 | #define CM_GCR_Cx_RESET_EXT_BASE_EVARESET_MSK (_ULCAST_(0x1) << 31) | |
372 | #define CM_GCR_Cx_RESET_EXT_BASE_UEB_SHF 30 | |
373 | #define CM_GCR_Cx_RESET_EXT_BASE_UEB_MSK (_ULCAST_(0x1) << 30) | |
374 | #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK_SHF 20 | |
375 | #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK_MSK (_ULCAST_(0xff) << 20) | |
376 | #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA_SHF 1 | |
377 | #define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA_MSK (_ULCAST_(0x7f) << 1) | |
378 | #define CM_GCR_Cx_RESET_EXT_BASE_PRESENT_SHF 0 | |
379 | #define CM_GCR_Cx_RESET_EXT_BASE_PRESENT_MSK (_ULCAST_(0x1) << 0) | |
380 | ||
381 | /** | |
382 | * mips_cm_numcores - return the number of cores present in the system | |
383 | * | |
384 | * Returns the value of the PCORES field of the GCR_CONFIG register plus 1, or | |
385 | * zero if no Coherence Manager is present. | |
386 | */ | |
387 | static inline unsigned mips_cm_numcores(void) | |
388 | { | |
389 | if (!mips_cm_present()) | |
390 | return 0; | |
391 | ||
392 | return ((read_gcr_config() & CM_GCR_CONFIG_PCORES_MSK) | |
393 | >> CM_GCR_CONFIG_PCORES_SHF) + 1; | |
394 | } | |
395 | ||
396 | /** | |
397 | * mips_cm_numiocu - return the number of IOCUs present in the system | |
398 | * | |
399 | * Returns the value of the NUMIOCU field of the GCR_CONFIG register, or zero | |
400 | * if no Coherence Manager is present. | |
401 | */ | |
402 | static inline unsigned mips_cm_numiocu(void) | |
403 | { | |
404 | if (!mips_cm_present()) | |
405 | return 0; | |
406 | ||
407 | return (read_gcr_config() & CM_GCR_CONFIG_NUMIOCU_MSK) | |
408 | >> CM_GCR_CONFIG_NUMIOCU_SHF; | |
409 | } | |
410 | ||
411 | /** | |
412 | * mips_cm_l2sync - perform an L2-only sync operation | |
413 | * | |
414 | * If an L2-only sync region is present in the system then this function | |
415 | * performs and L2-only sync and returns zero. Otherwise it returns -ENODEV. | |
416 | */ | |
417 | static inline int mips_cm_l2sync(void) | |
418 | { | |
419 | if (!mips_cm_has_l2sync()) | |
420 | return -ENODEV; | |
421 | ||
422 | writel(0, mips_cm_l2sync_base); | |
423 | return 0; | |
424 | } | |
425 | ||
197e89e0 PB |
426 | /** |
427 | * mips_cm_revision() - return CM revision | |
428 | * | |
429 | * Return: The revision of the CM, from GCR_REV, or 0 if no CM is present. The | |
430 | * return value should be checked against the CM_REV_* macros. | |
431 | */ | |
432 | static inline int mips_cm_revision(void) | |
433 | { | |
434 | if (!mips_cm_present()) | |
435 | return 0; | |
436 | ||
437 | return read_gcr_rev(); | |
438 | } | |
439 | ||
7573b94e PB |
440 | /** |
441 | * mips_cm_max_vp_width() - return the width in bits of VP indices | |
442 | * | |
443 | * Return: the width, in bits, of VP indices in fields that combine core & VP | |
444 | * indices. | |
445 | */ | |
446 | static inline unsigned int mips_cm_max_vp_width(void) | |
447 | { | |
448 | extern int smp_num_siblings; | |
449 | ||
450 | if (mips_cm_revision() >= CM_REV_CM3) | |
451 | return read_gcr_sys_config2() & CM_GCR_SYS_CONFIG2_MAXVPW_MSK; | |
452 | ||
453 | return smp_num_siblings; | |
454 | } | |
455 | ||
456 | /** | |
457 | * mips_cm_vp_id() - calculate the hardware VP ID for a CPU | |
458 | * @cpu: the CPU whose VP ID to calculate | |
459 | * | |
460 | * Hardware such as the GIC uses identifiers for VPs which may not match the | |
461 | * CPU numbers used by Linux. This function calculates the hardware VP | |
462 | * identifier corresponding to a given CPU. | |
463 | * | |
464 | * Return: the VP ID for the CPU. | |
465 | */ | |
466 | static inline unsigned int mips_cm_vp_id(unsigned int cpu) | |
467 | { | |
468 | unsigned int core = cpu_data[cpu].core; | |
469 | unsigned int vp = cpu_vpe_id(&cpu_data[cpu]); | |
470 | ||
471 | return (core * mips_cm_max_vp_width()) + vp; | |
472 | } | |
473 | ||
9f98f3dd | 474 | #endif /* __MIPS_ASM_MIPS_CM_H__ */ |