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5c642506 J |
1 | /* |
2 | * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights | |
3 | * reserved. | |
4 | * | |
5 | * This software is available to you under a choice of one of two | |
6 | * licenses. You may choose to be licensed under the terms of the GNU | |
7 | * General Public License (GPL) Version 2, available from the file | |
8 | * COPYING in the main directory of this source tree, or the NetLogic | |
9 | * license below: | |
10 | * | |
11 | * Redistribution and use in source and binary forms, with or without | |
12 | * modification, are permitted provided that the following conditions | |
13 | * are met: | |
14 | * | |
15 | * 1. Redistributions of source code must retain the above copyright | |
16 | * notice, this list of conditions and the following disclaimer. | |
17 | * 2. Redistributions in binary form must reproduce the above copyright | |
18 | * notice, this list of conditions and the following disclaimer in | |
19 | * the documentation and/or other materials provided with the | |
20 | * distribution. | |
21 | * | |
22 | * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR | |
23 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | |
24 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
25 | * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE | |
26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
28 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | |
29 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | |
30 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | |
31 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | |
32 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
33 | */ | |
34 | ||
35 | #ifndef _ASM_NLM_MIPS_EXTS_H | |
36 | #define _ASM_NLM_MIPS_EXTS_H | |
37 | ||
38 | /* | |
39 | * XLR and XLP interrupt request and interrupt mask registers | |
40 | */ | |
41 | #define read_c0_eirr() __read_64bit_c0_register($9, 6) | |
42 | #define read_c0_eimr() __read_64bit_c0_register($9, 7) | |
43 | #define write_c0_eirr(val) __write_64bit_c0_register($9, 6, val) | |
44 | ||
45 | /* | |
46 | * Writing EIMR in 32 bit is a special case, the lower 8 bit of the | |
47 | * EIMR is shadowed in the status register, so we cannot save and | |
48 | * restore status register for split read. | |
49 | */ | |
50 | #define write_c0_eimr(val) \ | |
51 | do { \ | |
70342287 | 52 | if (sizeof(unsigned long) == 4) { \ |
5c642506 J |
53 | unsigned long __flags; \ |
54 | \ | |
55 | local_irq_save(__flags); \ | |
56 | __asm__ __volatile__( \ | |
57 | ".set\tmips64\n\t" \ | |
58 | "dsll\t%L0, %L0, 32\n\t" \ | |
59 | "dsrl\t%L0, %L0, 32\n\t" \ | |
60 | "dsll\t%M0, %M0, 32\n\t" \ | |
61 | "or\t%L0, %L0, %M0\n\t" \ | |
62 | "dmtc0\t%L0, $9, 7\n\t" \ | |
63 | ".set\tmips0" \ | |
64 | : : "r" (val)); \ | |
65 | __flags = (__flags & 0xffff00ff) | (((val) & 0xff) << 8);\ | |
66 | local_irq_restore(__flags); \ | |
67 | } else \ | |
68 | __write_64bit_c0_register($9, 7, (val)); \ | |
69 | } while (0) | |
70 | ||
71 | static inline int hard_smp_processor_id(void) | |
72 | { | |
73 | return __read_32bit_c0_register($15, 1) & 0x3ff; | |
74 | } | |
75 | ||
77ae798f J |
76 | static inline int nlm_nodeid(void) |
77 | { | |
78 | return (__read_32bit_c0_register($15, 1) >> 5) & 0x3; | |
79 | } | |
80 | ||
ed21cfe2 GR |
81 | static inline unsigned int nlm_core_id(void) |
82 | { | |
83 | return (read_c0_ebase() & 0x1c) >> 2; | |
84 | } | |
85 | ||
86 | static inline unsigned int nlm_thread_id(void) | |
87 | { | |
88 | return read_c0_ebase() & 0x3; | |
89 | } | |
90 | ||
91 | #define __read_64bit_c2_split(source, sel) \ | |
92 | ({ \ | |
93 | unsigned long long __val; \ | |
94 | unsigned long __flags; \ | |
95 | \ | |
96 | local_irq_save(__flags); \ | |
97 | if (sel == 0) \ | |
98 | __asm__ __volatile__( \ | |
99 | ".set\tmips64\n\t" \ | |
100 | "dmfc2\t%M0, " #source "\n\t" \ | |
101 | "dsll\t%L0, %M0, 32\n\t" \ | |
102 | "dsra\t%M0, %M0, 32\n\t" \ | |
103 | "dsra\t%L0, %L0, 32\n\t" \ | |
104 | ".set\tmips0\n\t" \ | |
105 | : "=r" (__val)); \ | |
106 | else \ | |
107 | __asm__ __volatile__( \ | |
108 | ".set\tmips64\n\t" \ | |
109 | "dmfc2\t%M0, " #source ", " #sel "\n\t" \ | |
110 | "dsll\t%L0, %M0, 32\n\t" \ | |
111 | "dsra\t%M0, %M0, 32\n\t" \ | |
112 | "dsra\t%L0, %L0, 32\n\t" \ | |
113 | ".set\tmips0\n\t" \ | |
114 | : "=r" (__val)); \ | |
115 | local_irq_restore(__flags); \ | |
116 | \ | |
117 | __val; \ | |
118 | }) | |
119 | ||
120 | #define __write_64bit_c2_split(source, sel, val) \ | |
121 | do { \ | |
122 | unsigned long __flags; \ | |
123 | \ | |
124 | local_irq_save(__flags); \ | |
125 | if (sel == 0) \ | |
126 | __asm__ __volatile__( \ | |
127 | ".set\tmips64\n\t" \ | |
128 | "dsll\t%L0, %L0, 32\n\t" \ | |
129 | "dsrl\t%L0, %L0, 32\n\t" \ | |
130 | "dsll\t%M0, %M0, 32\n\t" \ | |
131 | "or\t%L0, %L0, %M0\n\t" \ | |
132 | "dmtc2\t%L0, " #source "\n\t" \ | |
133 | ".set\tmips0\n\t" \ | |
134 | : : "r" (val)); \ | |
135 | else \ | |
136 | __asm__ __volatile__( \ | |
137 | ".set\tmips64\n\t" \ | |
138 | "dsll\t%L0, %L0, 32\n\t" \ | |
139 | "dsrl\t%L0, %L0, 32\n\t" \ | |
140 | "dsll\t%M0, %M0, 32\n\t" \ | |
141 | "or\t%L0, %L0, %M0\n\t" \ | |
142 | "dmtc2\t%L0, " #source ", " #sel "\n\t" \ | |
143 | ".set\tmips0\n\t" \ | |
144 | : : "r" (val)); \ | |
145 | local_irq_restore(__flags); \ | |
146 | } while (0) | |
147 | ||
148 | #define __read_32bit_c2_register(source, sel) \ | |
149 | ({ uint32_t __res; \ | |
150 | if (sel == 0) \ | |
151 | __asm__ __volatile__( \ | |
152 | ".set\tmips32\n\t" \ | |
153 | "mfc2\t%0, " #source "\n\t" \ | |
154 | ".set\tmips0\n\t" \ | |
155 | : "=r" (__res)); \ | |
156 | else \ | |
157 | __asm__ __volatile__( \ | |
158 | ".set\tmips32\n\t" \ | |
159 | "mfc2\t%0, " #source ", " #sel "\n\t" \ | |
160 | ".set\tmips0\n\t" \ | |
161 | : "=r" (__res)); \ | |
162 | __res; \ | |
163 | }) | |
164 | ||
165 | #define __read_64bit_c2_register(source, sel) \ | |
166 | ({ unsigned long long __res; \ | |
167 | if (sizeof(unsigned long) == 4) \ | |
168 | __res = __read_64bit_c2_split(source, sel); \ | |
169 | else if (sel == 0) \ | |
170 | __asm__ __volatile__( \ | |
171 | ".set\tmips64\n\t" \ | |
172 | "dmfc2\t%0, " #source "\n\t" \ | |
173 | ".set\tmips0\n\t" \ | |
174 | : "=r" (__res)); \ | |
175 | else \ | |
176 | __asm__ __volatile__( \ | |
177 | ".set\tmips64\n\t" \ | |
178 | "dmfc2\t%0, " #source ", " #sel "\n\t" \ | |
179 | ".set\tmips0\n\t" \ | |
180 | : "=r" (__res)); \ | |
181 | __res; \ | |
182 | }) | |
183 | ||
184 | #define __write_64bit_c2_register(register, sel, value) \ | |
185 | do { \ | |
186 | if (sizeof(unsigned long) == 4) \ | |
187 | __write_64bit_c2_split(register, sel, value); \ | |
188 | else if (sel == 0) \ | |
189 | __asm__ __volatile__( \ | |
190 | ".set\tmips64\n\t" \ | |
191 | "dmtc2\t%z0, " #register "\n\t" \ | |
192 | ".set\tmips0\n\t" \ | |
193 | : : "Jr" (value)); \ | |
194 | else \ | |
195 | __asm__ __volatile__( \ | |
196 | ".set\tmips64\n\t" \ | |
197 | "dmtc2\t%z0, " #register ", " #sel "\n\t" \ | |
198 | ".set\tmips0\n\t" \ | |
199 | : : "Jr" (value)); \ | |
200 | } while (0) | |
201 | ||
202 | #define __write_32bit_c2_register(reg, sel, value) \ | |
203 | ({ \ | |
204 | if (sel == 0) \ | |
205 | __asm__ __volatile__( \ | |
206 | ".set\tmips32\n\t" \ | |
207 | "mtc2\t%z0, " #reg "\n\t" \ | |
208 | ".set\tmips0\n\t" \ | |
209 | : : "Jr" (value)); \ | |
210 | else \ | |
70342287 | 211 | __asm__ __volatile__( \ |
ed21cfe2 GR |
212 | ".set\tmips32\n\t" \ |
213 | "mtc2\t%z0, " #reg ", " #sel "\n\t" \ | |
214 | ".set\tmips0\n\t" \ | |
215 | : : "Jr" (value)); \ | |
216 | }) | |
217 | ||
5c642506 | 218 | #endif /*_ASM_NLM_MIPS_EXTS_H */ |