[mirror_ubuntu-artful-kernel.git] / arch / mips / include / asm / netlogic / xlp-hal / xlp.h

/*
 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
 * reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the NetLogic
 * license below:
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _NLM_HAL_XLP_H
#define _NLM_HAL_XLP_H

#define PIC_UART_0_IRQ			17
#define PIC_UART_1_IRQ			18

#define PIC_PCIE_LINK_LEGACY_IRQ_BASE	19
#define PIC_PCIE_LINK_LEGACY_IRQ(i)	(19 + (i))

#define PIC_EHCI_0_IRQ			23
#define PIC_EHCI_1_IRQ			24
#define PIC_OHCI_0_IRQ			25
#define PIC_OHCI_1_IRQ			26
#define PIC_OHCI_2_IRQ			27
#define PIC_OHCI_3_IRQ			28
#define PIC_2XX_XHCI_0_IRQ		23
#define PIC_2XX_XHCI_1_IRQ		24
#define PIC_2XX_XHCI_2_IRQ		25

#define PIC_MMC_IRQ			29
#define PIC_I2C_0_IRQ			30
#define PIC_I2C_1_IRQ			31
#define PIC_I2C_2_IRQ			32
#define PIC_I2C_3_IRQ			33

#define PIC_PCIE_LINK_MSI_IRQ_BASE	44	/* 44 - 47 MSI IRQ */
#define PIC_PCIE_LINK_MSI_IRQ(i)	(44 + (i))

/* MSI-X with second link-level dispatch */
#define PIC_PCIE_MSIX_IRQ_BASE		48	/* 48 - 51 MSI-X IRQ */
#define PIC_PCIE_MSIX_IRQ(i)		(48 + (i))

#define NLM_MSIX_VEC_BASE		96	/* 96 - 127 - MSIX mapped */
#define NLM_MSI_VEC_BASE		128	/* 128 -255 - MSI mapped */

#define NLM_PIC_INDIRECT_VEC_BASE	512
#define NLM_GPIO_VEC_BASE		768

#define PIC_IRQ_BASE			8
#define PIC_IRT_FIRST_IRQ		PIC_IRQ_BASE
#define PIC_IRT_LAST_IRQ		63

#ifndef __ASSEMBLY__

/* SMP support functions */
void xlp_boot_core0_siblings(void);
void xlp_wakeup_secondary_cpus(void);

void xlp_mmu_init(void);
void nlm_hal_init(void);
int xlp_get_dram_map(int n, uint64_t *dram_map);

/* Device tree related */
void xlp_early_init_devtree(void);
void *xlp_dt_init(void *fdtp);

static inline int cpu_is_xlpii(void)
{
	int chip = read_c0_prid() & 0xff00;

	return chip == PRID_IMP_NETLOGIC_XLP2XX ||
		chip == PRID_IMP_NETLOGIC_XLP9XX;
}

static inline int cpu_is_xlp9xx(void)
{
	int chip = read_c0_prid() & 0xff00;

	return chip == PRID_IMP_NETLOGIC_XLP9XX;
}
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_NLM_XLP_H */
Commit	Line	Data
65040e22 J	1	/*
	2	* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
	3	* reserved.
	4	*
	5	* This software is available to you under a choice of one of two
	6	* licenses. You may choose to be licensed under the terms of the GNU
	7	* General Public License (GPL) Version 2, available from the file
	8	* COPYING in the main directory of this source tree, or the NetLogic
	9	* license below:
	10	*
	11	* Redistribution and use in source and binary forms, with or without
	12	* modification, are permitted provided that the following conditions
	13	* are met:
	14	*
	15	* 1. Redistributions of source code must retain the above copyright
	16	* notice, this list of conditions and the following disclaimer.
	17	* 2. Redistributions in binary form must reproduce the above copyright
	18	* notice, this list of conditions and the following disclaimer in
	19	* the documentation and/or other materials provided with the
	20	* distribution.
	21	*
	22	* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
	23	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	24	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	25	* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	27	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	28	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
	29	* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
	30	* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
	31	* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
	32	* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	33	*/
	34
	35	#ifndef _NLM_HAL_XLP_H
	36	#define _NLM_HAL_XLP_H
	37
9bac624b GR	38	#define PIC_UART_0_IRQ 17
9bac624b GR	39	#define PIC_UART_1_IRQ 18
c24a8a7a J	40
	41	#define PIC_PCIE_LINK_LEGACY_IRQ_BASE 19
	42	#define PIC_PCIE_LINK_LEGACY_IRQ(i) (19 + (i))
9eac3591	43
1004165f GR	44	#define PIC_EHCI_0_IRQ 23
	45	#define PIC_EHCI_1_IRQ 24
	46	#define PIC_OHCI_0_IRQ 25
	47	#define PIC_OHCI_1_IRQ 26
	48	#define PIC_OHCI_2_IRQ 27
	49	#define PIC_OHCI_3_IRQ 28
9eac3591 GR	50	#define PIC_2XX_XHCI_0_IRQ 23
	51	#define PIC_2XX_XHCI_1_IRQ 24
	52	#define PIC_2XX_XHCI_2_IRQ 25
	53
57d7cdb6 J	54	#define PIC_MMC_IRQ 29
	55	#define PIC_I2C_0_IRQ 30
	56	#define PIC_I2C_1_IRQ 31
e5be1fd0 GR	57	#define PIC_I2C_2_IRQ 32
e5be1fd0 GR	58	#define PIC_I2C_3_IRQ 33
65040e22	59
c24a8a7a J	60	#define PIC_PCIE_LINK_MSI_IRQ_BASE 44 /* 44 - 47 MSI IRQ */
	61	#define PIC_PCIE_LINK_MSI_IRQ(i) (44 + (i))
	62
	63	/* MSI-X with second link-level dispatch */
	64	#define PIC_PCIE_MSIX_IRQ_BASE 48 /* 48 - 51 MSI-X IRQ */
	65	#define PIC_PCIE_MSIX_IRQ(i) (48 + (i))
	66
	67	#define NLM_MSIX_VEC_BASE 96 /* 96 - 127 - MSIX mapped */
	68	#define NLM_MSI_VEC_BASE 128 /* 128 -255 - MSI mapped */
	69
	70	#define NLM_PIC_INDIRECT_VEC_BASE 512
	71	#define NLM_GPIO_VEC_BASE 768
	72
	73	#define PIC_IRQ_BASE 8
	74	#define PIC_IRT_FIRST_IRQ PIC_IRQ_BASE
	75	#define PIC_IRT_LAST_IRQ 63
	76
65040e22 J	77	#ifndef __ASSEMBLY__
	78
	79	/* SMP support functions */
66d29985 J	80	void xlp_boot_core0_siblings(void);
66d29985 J	81	void xlp_wakeup_secondary_cpus(void);
65040e22 J	82
	83	void xlp_mmu_init(void);
	84	void nlm_hal_init(void);
a2ba6cd6 J	85	int xlp_get_dram_map(int n, uint64_t *dram_map);
	86
	87	/* Device tree related */
e363bbac	88	void xlp_early_init_devtree(void);
aceee09d	89	void xlp_dt_init(void fdtp);
65040e22	90
4ca86a2f J	91	static inline int cpu_is_xlpii(void)
	92	{
	93	int chip = read_c0_prid() & 0xff00;
	94
8907c55e J	95	return chip == PRID_IMP_NETLOGIC_XLP2XX \|\|
8907c55e J	96	chip == PRID_IMP_NETLOGIC_XLP9XX;
4ca86a2f J	97	}
4ca86a2f J	98
8907c55e J	99	static inline int cpu_is_xlp9xx(void)
	100	{
	101	int chip = read_c0_prid() & 0xff00;
	102
	103	return chip == PRID_IMP_NETLOGIC_XLP9XX;
	104	}
65040e22 J	105	#endif /* !__ASSEMBLY__ */
65040e22 J	106	#endif /* _ASM_NLM_XLP_H */