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1 | /***********************license start*************** |
2 | * Author: Cavium Networks | |
3 | * | |
4 | * Contact: support@caviumnetworks.com | |
5 | * This file is part of the OCTEON SDK | |
6 | * | |
7 | * Copyright (c) 2003-2008 Cavium Networks | |
8 | * | |
9 | * This file is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License, Version 2, as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This file is distributed in the hope that it will be useful, but | |
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | |
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | |
16 | * NONINFRINGEMENT. See the GNU General Public License for more | |
17 | * details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this file; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
22 | * or visit http://www.gnu.org/licenses/. | |
23 | * | |
24 | * This file may also be available under a different license from Cavium. | |
25 | * Contact Cavium Networks for more information | |
26 | ***********************license end**************************************/ | |
27 | ||
28 | /* | |
29 | * | |
30 | * This is file defines ASM primitives for the executive. | |
31 | */ | |
32 | #ifndef __CVMX_ASM_H__ | |
33 | #define __CVMX_ASM_H__ | |
34 | ||
a1ce3928 | 35 | #include <asm/octeon/octeon-model.h> |
58f07778 DD |
36 | |
37 | /* other useful stuff */ | |
38 | #define CVMX_SYNC asm volatile ("sync" : : : "memory") | |
39 | /* String version of SYNCW macro for using in inline asm constructs */ | |
40 | #define CVMX_SYNCW_STR "syncw\nsyncw\n" | |
41 | #ifdef __OCTEON__ | |
42 | ||
43 | /* Deprecated, will be removed in future release */ | |
44 | #define CVMX_SYNCIO asm volatile ("nop") | |
45 | ||
46 | #define CVMX_SYNCIOBDMA asm volatile ("synciobdma" : : : "memory") | |
47 | ||
48 | /* Deprecated, will be removed in future release */ | |
49 | #define CVMX_SYNCIOALL asm volatile ("nop") | |
50 | ||
51 | /* | |
52 | * We actually use two syncw instructions in a row when we need a write | |
53 | * memory barrier. This is because the CN3XXX series of Octeons have | |
54 | * errata Core-401. This can cause a single syncw to not enforce | |
55 | * ordering under very rare conditions. Even if it is rare, better safe | |
56 | * than sorry. | |
57 | */ | |
58 | #define CVMX_SYNCW asm volatile ("syncw\n\tsyncw" : : : "memory") | |
59 | ||
60 | /* | |
61 | * Define new sync instructions to be normal SYNC instructions for | |
62 | * operating systems that use threads. | |
63 | */ | |
64 | #define CVMX_SYNCWS CVMX_SYNCW | |
65 | #define CVMX_SYNCS CVMX_SYNC | |
66 | #define CVMX_SYNCWS_STR CVMX_SYNCW_STR | |
67 | #else | |
68 | /* | |
69 | * Not using a Cavium compiler, always use the slower sync so the | |
70 | * assembler stays happy. | |
71 | */ | |
72 | /* Deprecated, will be removed in future release */ | |
73 | #define CVMX_SYNCIO asm volatile ("nop") | |
74 | ||
75 | #define CVMX_SYNCIOBDMA asm volatile ("sync" : : : "memory") | |
76 | ||
77 | /* Deprecated, will be removed in future release */ | |
78 | #define CVMX_SYNCIOALL asm volatile ("nop") | |
79 | ||
80 | #define CVMX_SYNCW asm volatile ("sync" : : : "memory") | |
81 | #define CVMX_SYNCWS CVMX_SYNCW | |
82 | #define CVMX_SYNCS CVMX_SYNC | |
83 | #define CVMX_SYNCWS_STR CVMX_SYNCW_STR | |
84 | #endif | |
85 | ||
86 | /* | |
87 | * CVMX_PREPARE_FOR_STORE makes each byte of the block unpredictable | |
88 | * (actually old value or zero) until that byte is stored to (by this or | |
89 | * another processor. Note that the value of each byte is not only | |
90 | * unpredictable, but may also change again - up until the point when one | |
91 | * of the cores stores to the byte. | |
92 | */ | |
93 | #define CVMX_PREPARE_FOR_STORE(address, offset) \ | |
94 | asm volatile ("pref 30, " CVMX_TMP_STR(offset) "(%[rbase])" : : \ | |
95 | [rbase] "d" (address)) | |
96 | /* | |
97 | * This is a command headed to the L2 controller to tell it to clear | |
98 | * its dirty bit for a block. Basically, SW is telling HW that the | |
99 | * current version of the block will not be used. | |
100 | */ | |
101 | #define CVMX_DONT_WRITE_BACK(address, offset) \ | |
102 | asm volatile ("pref 29, " CVMX_TMP_STR(offset) "(%[rbase])" : : \ | |
103 | [rbase] "d" (address)) | |
104 | ||
105 | /* flush stores, invalidate entire icache */ | |
106 | #define CVMX_ICACHE_INVALIDATE \ | |
107 | { CVMX_SYNC; asm volatile ("synci 0($0)" : : ); } | |
108 | ||
109 | /* flush stores, invalidate entire icache */ | |
110 | #define CVMX_ICACHE_INVALIDATE2 \ | |
111 | { CVMX_SYNC; asm volatile ("cache 0, 0($0)" : : ); } | |
112 | ||
113 | /* complete prefetches, invalidate entire dcache */ | |
114 | #define CVMX_DCACHE_INVALIDATE \ | |
115 | { CVMX_SYNC; asm volatile ("cache 9, 0($0)" : : ); } | |
116 | ||
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117 | #define CVMX_CACHE(op, address, offset) \ |
118 | asm volatile ("cache " CVMX_TMP_STR(op) ", " CVMX_TMP_STR(offset) "(%[rbase])" \ | |
119 | : : [rbase] "d" (address) ) | |
120 | /* fetch and lock the state. */ | |
121 | #define CVMX_CACHE_LCKL2(address, offset) CVMX_CACHE(31, address, offset) | |
122 | /* unlock the state. */ | |
123 | #define CVMX_CACHE_WBIL2(address, offset) CVMX_CACHE(23, address, offset) | |
124 | /* invalidate the cache block and clear the USED bits for the block */ | |
125 | #define CVMX_CACHE_WBIL2I(address, offset) CVMX_CACHE(3, address, offset) | |
126 | /* load virtual tag and data for the L2 cache block into L2C_TAD0_TAG register */ | |
127 | #define CVMX_CACHE_LTGL2I(address, offset) CVMX_CACHE(7, address, offset) | |
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128 | |
129 | #define CVMX_POP(result, input) \ | |
130 | asm ("pop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input)) | |
131 | #define CVMX_DPOP(result, input) \ | |
132 | asm ("dpop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input)) | |
133 | ||
134 | /* some new cop0-like stuff */ | |
135 | #define CVMX_RDHWR(result, regstr) \ | |
136 | asm volatile ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result)) | |
137 | #define CVMX_RDHWRNV(result, regstr) \ | |
138 | asm ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result)) | |
139 | #endif /* __CVMX_ASM_H__ */ |