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1 | /***********************license start*************** |
2 | * Author: Cavium Inc. | |
3 | * | |
4 | * Contact: support@cavium.com | |
5 | * This file is part of the OCTEON SDK | |
6 | * | |
7 | * Copyright (c) 2003-2014 Cavium Inc. | |
8 | * | |
9 | * This file is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License, Version 2, as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This file is distributed in the hope that it will be useful, but | |
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | |
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | |
16 | * NONINFRINGEMENT. See the GNU General Public License for more | |
17 | * details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this file; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
22 | * or visit http://www.gnu.org/licenses/. | |
23 | * | |
24 | * This file may also be available under a different license from Cavium. | |
25 | * Contact Cavium Inc. for more information | |
26 | ***********************license end**************************************/ | |
27 | ||
28 | #ifndef __CVMX_RST_DEFS_H__ | |
29 | #define __CVMX_RST_DEFS_H__ | |
30 | ||
31 | #define CVMX_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180006001600ull)) | |
32 | #define CVMX_RST_CFG (CVMX_ADD_IO_SEG(0x0001180006001610ull)) | |
33 | #define CVMX_RST_CKILL (CVMX_ADD_IO_SEG(0x0001180006001638ull)) | |
34 | #define CVMX_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180006001640ull) + ((offset) & 3) * 8) | |
35 | #define CVMX_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180006001608ull)) | |
36 | #define CVMX_RST_ECO (CVMX_ADD_IO_SEG(0x00011800060017B8ull)) | |
37 | #define CVMX_RST_INT (CVMX_ADD_IO_SEG(0x0001180006001628ull)) | |
38 | #define CVMX_RST_OCX (CVMX_ADD_IO_SEG(0x0001180006001618ull)) | |
39 | #define CVMX_RST_POWER_DBG (CVMX_ADD_IO_SEG(0x0001180006001708ull)) | |
40 | #define CVMX_RST_PP_POWER (CVMX_ADD_IO_SEG(0x0001180006001700ull)) | |
41 | #define CVMX_RST_SOFT_PRSTX(offset) (CVMX_ADD_IO_SEG(0x00011800060016C0ull) + ((offset) & 3) * 8) | |
42 | #define CVMX_RST_SOFT_RST (CVMX_ADD_IO_SEG(0x0001180006001680ull)) | |
43 | ||
44 | union cvmx_rst_boot { | |
45 | uint64_t u64; | |
46 | struct cvmx_rst_boot_s { | |
47 | #ifdef __BIG_ENDIAN_BITFIELD | |
48 | uint64_t chipkill:1; | |
49 | uint64_t jtcsrdis:1; | |
50 | uint64_t ejtagdis:1; | |
51 | uint64_t romen:1; | |
52 | uint64_t ckill_ppdis:1; | |
53 | uint64_t jt_tstmode:1; | |
54 | uint64_t vrm_err:1; | |
55 | uint64_t reserved_37_56:20; | |
56 | uint64_t c_mul:7; | |
57 | uint64_t pnr_mul:6; | |
58 | uint64_t reserved_21_23:3; | |
59 | uint64_t lboot_oci:3; | |
60 | uint64_t lboot_ext:6; | |
61 | uint64_t lboot:10; | |
62 | uint64_t rboot:1; | |
63 | uint64_t rboot_pin:1; | |
64 | #else | |
65 | uint64_t rboot_pin:1; | |
66 | uint64_t rboot:1; | |
67 | uint64_t lboot:10; | |
68 | uint64_t lboot_ext:6; | |
69 | uint64_t lboot_oci:3; | |
70 | uint64_t reserved_21_23:3; | |
71 | uint64_t pnr_mul:6; | |
72 | uint64_t c_mul:7; | |
73 | uint64_t reserved_37_56:20; | |
74 | uint64_t vrm_err:1; | |
75 | uint64_t jt_tstmode:1; | |
76 | uint64_t ckill_ppdis:1; | |
77 | uint64_t romen:1; | |
78 | uint64_t ejtagdis:1; | |
79 | uint64_t jtcsrdis:1; | |
80 | uint64_t chipkill:1; | |
81 | #endif | |
82 | } s; | |
83 | struct cvmx_rst_boot_s cn70xx; | |
84 | struct cvmx_rst_boot_s cn70xxp1; | |
85 | struct cvmx_rst_boot_s cn78xx; | |
86 | }; | |
87 | ||
88 | union cvmx_rst_cfg { | |
89 | uint64_t u64; | |
90 | struct cvmx_rst_cfg_s { | |
91 | #ifdef __BIG_ENDIAN_BITFIELD | |
92 | uint64_t bist_delay:58; | |
93 | uint64_t reserved_3_5:3; | |
94 | uint64_t cntl_clr_bist:1; | |
95 | uint64_t warm_clr_bist:1; | |
96 | uint64_t soft_clr_bist:1; | |
97 | #else | |
98 | uint64_t soft_clr_bist:1; | |
99 | uint64_t warm_clr_bist:1; | |
100 | uint64_t cntl_clr_bist:1; | |
101 | uint64_t reserved_3_5:3; | |
102 | uint64_t bist_delay:58; | |
103 | #endif | |
104 | } s; | |
105 | struct cvmx_rst_cfg_s cn70xx; | |
106 | struct cvmx_rst_cfg_s cn70xxp1; | |
107 | struct cvmx_rst_cfg_s cn78xx; | |
108 | }; | |
109 | ||
110 | union cvmx_rst_ckill { | |
111 | uint64_t u64; | |
112 | struct cvmx_rst_ckill_s { | |
113 | #ifdef __BIG_ENDIAN_BITFIELD | |
114 | uint64_t reserved_47_63:17; | |
115 | uint64_t timer:47; | |
116 | #else | |
117 | uint64_t timer:47; | |
118 | uint64_t reserved_47_63:17; | |
119 | #endif | |
120 | } s; | |
121 | struct cvmx_rst_ckill_s cn70xx; | |
122 | struct cvmx_rst_ckill_s cn70xxp1; | |
123 | struct cvmx_rst_ckill_s cn78xx; | |
124 | }; | |
125 | ||
126 | union cvmx_rst_ctlx { | |
127 | uint64_t u64; | |
128 | struct cvmx_rst_ctlx_s { | |
129 | #ifdef __BIG_ENDIAN_BITFIELD | |
130 | uint64_t reserved_10_63:54; | |
131 | uint64_t prst_link:1; | |
132 | uint64_t rst_done:1; | |
133 | uint64_t rst_link:1; | |
134 | uint64_t host_mode:1; | |
135 | uint64_t reserved_4_5:2; | |
136 | uint64_t rst_drv:1; | |
137 | uint64_t rst_rcv:1; | |
138 | uint64_t rst_chip:1; | |
139 | uint64_t rst_val:1; | |
140 | #else | |
141 | uint64_t rst_val:1; | |
142 | uint64_t rst_chip:1; | |
143 | uint64_t rst_rcv:1; | |
144 | uint64_t rst_drv:1; | |
145 | uint64_t reserved_4_5:2; | |
146 | uint64_t host_mode:1; | |
147 | uint64_t rst_link:1; | |
148 | uint64_t rst_done:1; | |
149 | uint64_t prst_link:1; | |
150 | uint64_t reserved_10_63:54; | |
151 | #endif | |
152 | } s; | |
153 | struct cvmx_rst_ctlx_s cn70xx; | |
154 | struct cvmx_rst_ctlx_s cn70xxp1; | |
155 | struct cvmx_rst_ctlx_s cn78xx; | |
156 | }; | |
157 | ||
158 | union cvmx_rst_delay { | |
159 | uint64_t u64; | |
160 | struct cvmx_rst_delay_s { | |
161 | #ifdef __BIG_ENDIAN_BITFIELD | |
162 | uint64_t reserved_32_63:32; | |
163 | uint64_t warm_rst_dly:16; | |
164 | uint64_t soft_rst_dly:16; | |
165 | #else | |
166 | uint64_t soft_rst_dly:16; | |
167 | uint64_t warm_rst_dly:16; | |
168 | uint64_t reserved_32_63:32; | |
169 | #endif | |
170 | } s; | |
171 | struct cvmx_rst_delay_s cn70xx; | |
172 | struct cvmx_rst_delay_s cn70xxp1; | |
173 | struct cvmx_rst_delay_s cn78xx; | |
174 | }; | |
175 | ||
176 | union cvmx_rst_eco { | |
177 | uint64_t u64; | |
178 | struct cvmx_rst_eco_s { | |
179 | #ifdef __BIG_ENDIAN_BITFIELD | |
180 | uint64_t reserved_32_63:32; | |
181 | uint64_t eco_rw:32; | |
182 | #else | |
183 | uint64_t eco_rw:32; | |
184 | uint64_t reserved_32_63:32; | |
185 | #endif | |
186 | } s; | |
187 | struct cvmx_rst_eco_s cn78xx; | |
188 | }; | |
189 | ||
190 | union cvmx_rst_int { | |
191 | uint64_t u64; | |
192 | struct cvmx_rst_int_s { | |
193 | #ifdef __BIG_ENDIAN_BITFIELD | |
194 | uint64_t reserved_12_63:52; | |
195 | uint64_t perst:4; | |
196 | uint64_t reserved_4_7:4; | |
197 | uint64_t rst_link:4; | |
198 | #else | |
199 | uint64_t rst_link:4; | |
200 | uint64_t reserved_4_7:4; | |
201 | uint64_t perst:4; | |
202 | uint64_t reserved_12_63:52; | |
203 | #endif | |
204 | } s; | |
205 | struct cvmx_rst_int_cn70xx { | |
206 | #ifdef __BIG_ENDIAN_BITFIELD | |
207 | uint64_t reserved_11_63:53; | |
208 | uint64_t perst:3; | |
209 | uint64_t reserved_3_7:5; | |
210 | uint64_t rst_link:3; | |
211 | #else | |
212 | uint64_t rst_link:3; | |
213 | uint64_t reserved_3_7:5; | |
214 | uint64_t perst:3; | |
215 | uint64_t reserved_11_63:53; | |
216 | #endif | |
217 | } cn70xx; | |
218 | struct cvmx_rst_int_cn70xx cn70xxp1; | |
219 | struct cvmx_rst_int_s cn78xx; | |
220 | }; | |
221 | ||
222 | union cvmx_rst_ocx { | |
223 | uint64_t u64; | |
224 | struct cvmx_rst_ocx_s { | |
225 | #ifdef __BIG_ENDIAN_BITFIELD | |
226 | uint64_t reserved_3_63:61; | |
227 | uint64_t rst_link:3; | |
228 | #else | |
229 | uint64_t rst_link:3; | |
230 | uint64_t reserved_3_63:61; | |
231 | #endif | |
232 | } s; | |
233 | struct cvmx_rst_ocx_s cn78xx; | |
234 | }; | |
235 | ||
236 | union cvmx_rst_power_dbg { | |
237 | uint64_t u64; | |
238 | struct cvmx_rst_power_dbg_s { | |
239 | #ifdef __BIG_ENDIAN_BITFIELD | |
240 | uint64_t reserved_3_63:61; | |
241 | uint64_t str:3; | |
242 | #else | |
243 | uint64_t str:3; | |
244 | uint64_t reserved_3_63:61; | |
245 | #endif | |
246 | } s; | |
247 | struct cvmx_rst_power_dbg_s cn78xx; | |
248 | }; | |
249 | ||
250 | union cvmx_rst_pp_power { | |
251 | uint64_t u64; | |
252 | struct cvmx_rst_pp_power_s { | |
253 | #ifdef __BIG_ENDIAN_BITFIELD | |
254 | uint64_t reserved_48_63:16; | |
255 | uint64_t gate:48; | |
256 | #else | |
257 | uint64_t gate:48; | |
258 | uint64_t reserved_48_63:16; | |
259 | #endif | |
260 | } s; | |
261 | struct cvmx_rst_pp_power_cn70xx { | |
262 | #ifdef __BIG_ENDIAN_BITFIELD | |
263 | uint64_t reserved_4_63:60; | |
264 | uint64_t gate:4; | |
265 | #else | |
266 | uint64_t gate:4; | |
267 | uint64_t reserved_4_63:60; | |
268 | #endif | |
269 | } cn70xx; | |
270 | struct cvmx_rst_pp_power_cn70xx cn70xxp1; | |
271 | struct cvmx_rst_pp_power_s cn78xx; | |
272 | }; | |
273 | ||
274 | union cvmx_rst_soft_prstx { | |
275 | uint64_t u64; | |
276 | struct cvmx_rst_soft_prstx_s { | |
277 | #ifdef __BIG_ENDIAN_BITFIELD | |
278 | uint64_t reserved_1_63:63; | |
279 | uint64_t soft_prst:1; | |
280 | #else | |
281 | uint64_t soft_prst:1; | |
282 | uint64_t reserved_1_63:63; | |
283 | #endif | |
284 | } s; | |
285 | struct cvmx_rst_soft_prstx_s cn70xx; | |
286 | struct cvmx_rst_soft_prstx_s cn70xxp1; | |
287 | struct cvmx_rst_soft_prstx_s cn78xx; | |
288 | }; | |
289 | ||
290 | union cvmx_rst_soft_rst { | |
291 | uint64_t u64; | |
292 | struct cvmx_rst_soft_rst_s { | |
293 | #ifdef __BIG_ENDIAN_BITFIELD | |
294 | uint64_t reserved_1_63:63; | |
295 | uint64_t soft_rst:1; | |
296 | #else | |
297 | uint64_t soft_rst:1; | |
298 | uint64_t reserved_1_63:63; | |
299 | #endif | |
300 | } s; | |
301 | struct cvmx_rst_soft_rst_s cn70xx; | |
302 | struct cvmx_rst_soft_rst_s cn70xxp1; | |
303 | struct cvmx_rst_soft_rst_s cn78xx; | |
304 | }; | |
305 | ||
306 | #endif |