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[mirror_ubuntu-artful-kernel.git] / arch / mips / include / asm / octeon / cvmx-smix-defs.h
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25d967b7
DD		 1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
c5aa59e8 7 * Copyright (c) 2003-2012 Cavium Networks
25d967b7
DD		 8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_SMIX_DEFS_H__
29#define __CVMX_SMIX_DEFS_H__
30
c5aa59e8
DD		 31static inline uint64_t CVMX_SMIX_CLK(unsigned long offset)
32{
33 switch (cvmx_get_octeon_family()) {
34 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
35 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
36 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
37 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
38 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
39 return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256;
40 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
41 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
42 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
43 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
44 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
45 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
46 return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256;
47 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
48 return CVMX_ADD_IO_SEG(0x0001180000003818ull) + (offset) * 128;
49 }
50 return CVMX_ADD_IO_SEG(0x0001180000001818ull) + (offset) * 256;
51}
52
53static inline uint64_t CVMX_SMIX_CMD(unsigned long offset)
54{
55 switch (cvmx_get_octeon_family()) {
56 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
57 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
58 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
59 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
60 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
61 return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256;
62 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
63 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
64 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
65 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
66 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
67 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
68 return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256;
69 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
70 return CVMX_ADD_IO_SEG(0x0001180000003800ull) + (offset) * 128;
71 }
72 return CVMX_ADD_IO_SEG(0x0001180000001800ull) + (offset) * 256;
73}
74
75static inline uint64_t CVMX_SMIX_EN(unsigned long offset)
76{
77 switch (cvmx_get_octeon_family()) {
78 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
79 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
80 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
81 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
82 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
83 return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256;
84 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
85 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
86 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
87 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
88 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
89 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
90 return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256;
91 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
92 return CVMX_ADD_IO_SEG(0x0001180000003820ull) + (offset) * 128;
93 }
94 return CVMX_ADD_IO_SEG(0x0001180000001820ull) + (offset) * 256;
95}
96
97static inline uint64_t CVMX_SMIX_RD_DAT(unsigned long offset)
98{
99 switch (cvmx_get_octeon_family()) {
100 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
101 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
102 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
103 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
104 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
105 return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256;
106 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
107 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
108 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
109 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
110 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
111 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
112 return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256;
113 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
114 return CVMX_ADD_IO_SEG(0x0001180000003810ull) + (offset) * 128;
115 }
116 return CVMX_ADD_IO_SEG(0x0001180000001810ull) + (offset) * 256;
117}
118
119static inline uint64_t CVMX_SMIX_WR_DAT(unsigned long offset)
120{
121 switch (cvmx_get_octeon_family()) {
122 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
123 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
124 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
125 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
126 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
127 return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256;
128 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
129 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
130 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
131 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
132 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
133 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
134 return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256;
135 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
136 return CVMX_ADD_IO_SEG(0x0001180000003808ull) + (offset) * 128;
137 }
138 return CVMX_ADD_IO_SEG(0x0001180000001808ull) + (offset) * 256;
139}
25d967b7
DD		 140
141union cvmx_smix_clk {
142 uint64_t u64;
143 struct cvmx_smix_clk_s {
c5aa59e8 144#ifdef __BIG_ENDIAN_BITFIELD
25d967b7
DD		 145 uint64_t reserved_25_63:39;
146 uint64_t mode:1;
147 uint64_t reserved_21_23:3;
148 uint64_t sample_hi:5;
149 uint64_t sample_mode:1;
150 uint64_t reserved_14_14:1;
151 uint64_t clk_idle:1;
152 uint64_t preamble:1;
153 uint64_t sample:4;
154 uint64_t phase:8;
c5aa59e8
DD		 155#else
156 uint64_t phase:8;
157 uint64_t sample:4;
158 uint64_t preamble:1;
159 uint64_t clk_idle:1;
160 uint64_t reserved_14_14:1;
161 uint64_t sample_mode:1;
162 uint64_t sample_hi:5;
163 uint64_t reserved_21_23:3;
164 uint64_t mode:1;
165 uint64_t reserved_25_63:39;
166#endif
25d967b7
DD		 167 } s;
168 struct cvmx_smix_clk_cn30xx {
c5aa59e8 169#ifdef __BIG_ENDIAN_BITFIELD
25d967b7
DD		 170 uint64_t reserved_21_63:43;
171 uint64_t sample_hi:5;
aa32a955
DD		 172 uint64_t sample_mode:1;
173 uint64_t reserved_14_14:1;
25d967b7
DD		 174 uint64_t clk_idle:1;
175 uint64_t preamble:1;
176 uint64_t sample:4;
177 uint64_t phase:8;
c5aa59e8
DD		 178#else
179 uint64_t phase:8;
180 uint64_t sample:4;
181 uint64_t preamble:1;
182 uint64_t clk_idle:1;
183 uint64_t reserved_14_14:1;
184 uint64_t sample_mode:1;
185 uint64_t sample_hi:5;
186 uint64_t reserved_21_63:43;
187#endif
25d967b7
DD		 188 } cn30xx;
189 struct cvmx_smix_clk_cn30xx cn31xx;
190 struct cvmx_smix_clk_cn30xx cn38xx;
191 struct cvmx_smix_clk_cn30xx cn38xxp2;
aa32a955 192 struct cvmx_smix_clk_s cn50xx;
25d967b7 193 struct cvmx_smix_clk_s cn52xx;
aa32a955 194 struct cvmx_smix_clk_s cn52xxp1;
25d967b7 195 struct cvmx_smix_clk_s cn56xx;
aa32a955 196 struct cvmx_smix_clk_s cn56xxp1;
25d967b7
DD		 197 struct cvmx_smix_clk_cn30xx cn58xx;
198 struct cvmx_smix_clk_cn30xx cn58xxp1;
c5aa59e8 199 struct cvmx_smix_clk_s cn61xx;
aa32a955
DD		 200 struct cvmx_smix_clk_s cn63xx;
201 struct cvmx_smix_clk_s cn63xxp1;
c5aa59e8
DD		 202 struct cvmx_smix_clk_s cn66xx;
203 struct cvmx_smix_clk_s cn68xx;
204 struct cvmx_smix_clk_s cn68xxp1;
205 struct cvmx_smix_clk_s cnf71xx;
25d967b7
DD		 206};
207
208union cvmx_smix_cmd {
209 uint64_t u64;
210 struct cvmx_smix_cmd_s {
c5aa59e8 211#ifdef __BIG_ENDIAN_BITFIELD
25d967b7
DD		 212 uint64_t reserved_18_63:46;
213 uint64_t phy_op:2;
214 uint64_t reserved_13_15:3;
215 uint64_t phy_adr:5;
216 uint64_t reserved_5_7:3;
217 uint64_t reg_adr:5;
c5aa59e8
DD		 218#else
219 uint64_t reg_adr:5;
220 uint64_t reserved_5_7:3;
221 uint64_t phy_adr:5;
222 uint64_t reserved_13_15:3;
223 uint64_t phy_op:2;
224 uint64_t reserved_18_63:46;
225#endif
25d967b7
DD		 226 } s;
227 struct cvmx_smix_cmd_cn30xx {
c5aa59e8 228#ifdef __BIG_ENDIAN_BITFIELD
25d967b7
DD		 229 uint64_t reserved_17_63:47;
230 uint64_t phy_op:1;
231 uint64_t reserved_13_15:3;
232 uint64_t phy_adr:5;
233 uint64_t reserved_5_7:3;
234 uint64_t reg_adr:5;
c5aa59e8
DD		 235#else
236 uint64_t reg_adr:5;
237 uint64_t reserved_5_7:3;
238 uint64_t phy_adr:5;
239 uint64_t reserved_13_15:3;
240 uint64_t phy_op:1;
241 uint64_t reserved_17_63:47;
242#endif
25d967b7
DD		 243 } cn30xx;
244 struct cvmx_smix_cmd_cn30xx cn31xx;
245 struct cvmx_smix_cmd_cn30xx cn38xx;
246 struct cvmx_smix_cmd_cn30xx cn38xxp2;
247 struct cvmx_smix_cmd_s cn50xx;
248 struct cvmx_smix_cmd_s cn52xx;
249 struct cvmx_smix_cmd_s cn52xxp1;
250 struct cvmx_smix_cmd_s cn56xx;
251 struct cvmx_smix_cmd_s cn56xxp1;
252 struct cvmx_smix_cmd_cn30xx cn58xx;
253 struct cvmx_smix_cmd_cn30xx cn58xxp1;
c5aa59e8 254 struct cvmx_smix_cmd_s cn61xx;
aa32a955
DD		 255 struct cvmx_smix_cmd_s cn63xx;
256 struct cvmx_smix_cmd_s cn63xxp1;
c5aa59e8
DD		 257 struct cvmx_smix_cmd_s cn66xx;
258 struct cvmx_smix_cmd_s cn68xx;
259 struct cvmx_smix_cmd_s cn68xxp1;
260 struct cvmx_smix_cmd_s cnf71xx;
25d967b7
DD		 261};
262
263union cvmx_smix_en {
264 uint64_t u64;
265 struct cvmx_smix_en_s {
c5aa59e8 266#ifdef __BIG_ENDIAN_BITFIELD
25d967b7
DD		 267 uint64_t reserved_1_63:63;
268 uint64_t en:1;
c5aa59e8
DD		 269#else
270 uint64_t en:1;
271 uint64_t reserved_1_63:63;
272#endif
25d967b7
DD		 273 } s;
274 struct cvmx_smix_en_s cn30xx;
275 struct cvmx_smix_en_s cn31xx;
276 struct cvmx_smix_en_s cn38xx;
277 struct cvmx_smix_en_s cn38xxp2;
278 struct cvmx_smix_en_s cn50xx;
279 struct cvmx_smix_en_s cn52xx;
280 struct cvmx_smix_en_s cn52xxp1;
281 struct cvmx_smix_en_s cn56xx;
282 struct cvmx_smix_en_s cn56xxp1;
283 struct cvmx_smix_en_s cn58xx;
284 struct cvmx_smix_en_s cn58xxp1;
c5aa59e8 285 struct cvmx_smix_en_s cn61xx;
aa32a955
DD		 286 struct cvmx_smix_en_s cn63xx;
287 struct cvmx_smix_en_s cn63xxp1;
c5aa59e8
DD		 288 struct cvmx_smix_en_s cn66xx;
289 struct cvmx_smix_en_s cn68xx;
290 struct cvmx_smix_en_s cn68xxp1;
291 struct cvmx_smix_en_s cnf71xx;
25d967b7
DD		 292};
293
294union cvmx_smix_rd_dat {
295 uint64_t u64;
296 struct cvmx_smix_rd_dat_s {
c5aa59e8 297#ifdef __BIG_ENDIAN_BITFIELD
25d967b7
DD		 298 uint64_t reserved_18_63:46;
299 uint64_t pending:1;
300 uint64_t val:1;
301 uint64_t dat:16;
c5aa59e8
DD		 302#else
303 uint64_t dat:16;
304 uint64_t val:1;
305 uint64_t pending:1;
306 uint64_t reserved_18_63:46;
307#endif
25d967b7
DD		 308 } s;
309 struct cvmx_smix_rd_dat_s cn30xx;
310 struct cvmx_smix_rd_dat_s cn31xx;
311 struct cvmx_smix_rd_dat_s cn38xx;
312 struct cvmx_smix_rd_dat_s cn38xxp2;
313 struct cvmx_smix_rd_dat_s cn50xx;
314 struct cvmx_smix_rd_dat_s cn52xx;
315 struct cvmx_smix_rd_dat_s cn52xxp1;
316 struct cvmx_smix_rd_dat_s cn56xx;
317 struct cvmx_smix_rd_dat_s cn56xxp1;
318 struct cvmx_smix_rd_dat_s cn58xx;
319 struct cvmx_smix_rd_dat_s cn58xxp1;
c5aa59e8 320 struct cvmx_smix_rd_dat_s cn61xx;
aa32a955
DD		 321 struct cvmx_smix_rd_dat_s cn63xx;
322 struct cvmx_smix_rd_dat_s cn63xxp1;
c5aa59e8
DD		 323 struct cvmx_smix_rd_dat_s cn66xx;
324 struct cvmx_smix_rd_dat_s cn68xx;
325 struct cvmx_smix_rd_dat_s cn68xxp1;
326 struct cvmx_smix_rd_dat_s cnf71xx;
25d967b7
DD		 327};
328
329union cvmx_smix_wr_dat {
330 uint64_t u64;
331 struct cvmx_smix_wr_dat_s {
c5aa59e8 332#ifdef __BIG_ENDIAN_BITFIELD
25d967b7
DD		 333 uint64_t reserved_18_63:46;
334 uint64_t pending:1;
335 uint64_t val:1;
336 uint64_t dat:16;
c5aa59e8
DD		 337#else
338 uint64_t dat:16;
339 uint64_t val:1;
340 uint64_t pending:1;
341 uint64_t reserved_18_63:46;
342#endif
25d967b7
DD		 343 } s;
344 struct cvmx_smix_wr_dat_s cn30xx;
345 struct cvmx_smix_wr_dat_s cn31xx;
346 struct cvmx_smix_wr_dat_s cn38xx;
347 struct cvmx_smix_wr_dat_s cn38xxp2;
348 struct cvmx_smix_wr_dat_s cn50xx;
349 struct cvmx_smix_wr_dat_s cn52xx;
350 struct cvmx_smix_wr_dat_s cn52xxp1;
351 struct cvmx_smix_wr_dat_s cn56xx;
352 struct cvmx_smix_wr_dat_s cn56xxp1;
353 struct cvmx_smix_wr_dat_s cn58xx;
354 struct cvmx_smix_wr_dat_s cn58xxp1;
c5aa59e8 355 struct cvmx_smix_wr_dat_s cn61xx;
aa32a955
DD		 356 struct cvmx_smix_wr_dat_s cn63xx;
357 struct cvmx_smix_wr_dat_s cn63xxp1;
c5aa59e8
DD		 358 struct cvmx_smix_wr_dat_s cn66xx;
359 struct cvmx_smix_wr_dat_s cn68xx;
360 struct cvmx_smix_wr_dat_s cn68xxp1;
361 struct cvmx_smix_wr_dat_s cnf71xx;
25d967b7
DD		 362};
363
364#endif
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