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1da177e4
LT
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000, 03 Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 */
9#ifndef _ASM_PAGE_H
10#define _ASM_PAGE_H
11
1da177e4 12#include <spaces.h>
99502d94 13#include <linux/const.h>
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14#include <linux/kernel.h>
15#include <asm/mipsregs.h>
1da177e4 16
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17/*
18 * PAGE_SHIFT determines the page size
19 */
20#ifdef CONFIG_PAGE_SIZE_4KB
21#define PAGE_SHIFT 12
22#endif
23#ifdef CONFIG_PAGE_SIZE_8KB
24#define PAGE_SHIFT 13
25#endif
26#ifdef CONFIG_PAGE_SIZE_16KB
27#define PAGE_SHIFT 14
28#endif
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29#ifdef CONFIG_PAGE_SIZE_32KB
30#define PAGE_SHIFT 15
31#endif
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32#ifdef CONFIG_PAGE_SIZE_64KB
33#define PAGE_SHIFT 16
34#endif
99502d94 35#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT)
3b5e50ed 36#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1))
1da177e4 37
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38/*
39 * This is used for calculating the real page sizes
91ff7ac0 40 * for FTLB or VTLB + FTLB configurations.
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41 */
42static inline unsigned int page_size_ftlb(unsigned int mmuextdef)
43{
44 switch (mmuextdef) {
45 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
46 if (PAGE_SIZE == (1 << 30))
47 return 5;
48 if (PAGE_SIZE == (1llu << 32))
49 return 6;
50 if (PAGE_SIZE > (256 << 10))
51 return 7; /* reserved */
52 /* fall through */
53 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
54 return (PAGE_SHIFT - 10) / 2;
55 default:
56 panic("Invalid FTLB configuration with Conf4_mmuextdef=%d value\n",
57 mmuextdef >> 14);
58 }
59}
60
aa1762f4 61#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
dd794392 62#define HPAGE_SHIFT (PAGE_SHIFT + PAGE_SHIFT - 3)
99502d94 63#define HPAGE_SIZE (_AC(1,UL) << HPAGE_SHIFT)
dd794392
DD
64#define HPAGE_MASK (~(HPAGE_SIZE - 1))
65#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
aa1762f4 66#else /* !CONFIG_MIPS_HUGE_TLB_SUPPORT */
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HD
67#define HPAGE_SHIFT ({BUILD_BUG(); 0; })
68#define HPAGE_SIZE ({BUILD_BUG(); 0; })
69#define HPAGE_MASK ({BUILD_BUG(); 0; })
70#define HUGETLB_PAGE_ORDER ({BUILD_BUG(); 0; })
aa1762f4 71#endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
dd794392 72
41b0483e 73#include <linux/pfn.h>
6f284a2c 74
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DV
75extern void build_clear_page(void);
76extern void build_copy_page(void);
77
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78/*
79 * It's normally defined only for FLATMEM config but it's
80 * used in our early mem init code for all memory models.
81 * So always define it.
82 */
83#define ARCH_PFN_OFFSET PFN_UP(PHYS_OFFSET)
84
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85extern void clear_page(void * page);
86extern void copy_page(void * to, void * from);
87
88extern unsigned long shm_align_mask;
89
90static inline unsigned long pages_do_alias(unsigned long addr1,
91 unsigned long addr2)
92{
93 return (addr1 ^ addr2) & shm_align_mask;
94}
95
96struct page;
97
98static inline void clear_user_page(void *addr, unsigned long vaddr,
99 struct page *page)
100{
101 extern void (*flush_data_cache_page)(unsigned long addr);
102
103 clear_page(addr);
585fa724 104 if (pages_do_alias((unsigned long) addr, vaddr & PAGE_MASK))
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105 flush_data_cache_page((unsigned long)addr);
106}
107
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AN
108extern void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
109 struct page *to);
110struct vm_area_struct;
111extern void copy_user_highpage(struct page *to, struct page *from,
112 unsigned long vaddr, struct vm_area_struct *vma);
1da177e4 113
bcd02280 114#define __HAVE_ARCH_COPY_USER_HIGHPAGE
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115
116/*
117 * These are used to make use of C type-checking..
118 */
119#ifdef CONFIG_64BIT_PHYS_ADDR
ec917c2c 120 #ifdef CONFIG_CPU_MIPS32
1da177e4 121 typedef struct { unsigned long pte_low, pte_high; } pte_t;
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122 #define pte_val(x) ((x).pte_low | ((unsigned long long)(x).pte_high << 32))
123 #define __pte(x) ({ pte_t __pte = {(x), ((unsigned long long)(x)) >> 32}; __pte; })
1da177e4
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124 #else
125 typedef struct { unsigned long long pte; } pte_t;
70342287 126 #define pte_val(x) ((x).pte)
d34555fb 127 #define __pte(x) ((pte_t) { (x) } )
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128 #endif
129#else
130typedef struct { unsigned long pte; } pte_t;
131#define pte_val(x) ((x).pte)
c6e8b587 132#define __pte(x) ((pte_t) { (x) } )
d34555fb 133#endif
2f569afd 134typedef struct page *pgtable_t;
1da177e4 135
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136/*
137 * Right now we don't support 4-level pagetables, so all pud-related
138 * definitions come from <asm-generic/pgtable-nopud.h>.
139 */
140
141/*
142 * Finall the top of the hierarchy, the pgd
143 */
144typedef struct { unsigned long pgd; } pgd_t;
145#define pgd_val(x) ((x).pgd)
1da177e4 146#define __pgd(x) ((pgd_t) { (x) } )
c6e8b587
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147
148/*
149 * Manipulate page protection bits
150 */
151typedef struct { unsigned long pgprot; } pgprot_t;
152#define pgprot_val(x) ((x).pgprot)
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153#define __pgprot(x) ((pgprot_t) { (x) } )
154
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155/*
156 * On R4000-style MMUs where a TLB entry is mapping a adjacent even / odd
157 * pair of pages we only have a single global bit per pair of pages. When
158 * writing to the TLB make sure we always have the bit set for both pages
159 * or none. This macro is used to access the `buddy' of the pte we're just
160 * working on.
161 */
162#define ptep_buddy(x) ((pte_t *)((unsigned long)(x) ^ sizeof(pte_t)))
163
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FBH
164/*
165 * __pa()/__va() should be used only during mem init.
166 */
f4fae826 167#ifdef CONFIG_64BIT
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FBH
168#define __pa(x) \
169({ \
170 unsigned long __x = (unsigned long)(x); \
171 __x < CKSEG0 ? XPHYSADDR(__x) : CPHYSADDR(__x); \
172})
620a4802 173#else
b1c65b39
FBH
174#define __pa(x) \
175 ((unsigned long)(x) - PAGE_OFFSET + PHYS_OFFSET)
620a4802 176#endif
6f284a2c 177#define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET))
49c426ba 178#include <asm/io.h>
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RB
179
180/*
181 * RELOC_HIDE was originally added by 6007b903dfe5f1d13e0c711ac2894bdd4a61b1ad
182 * (lmo) rsp. 8431fd094d625b94d364fe393076ccef88e6ce18 (kernel.org). The
183 * discussion can be found in lkml posting
184 * <a2ebde260608230500o3407b108hc03debb9da6e62c@mail.gmail.com> which is
185 * archived at http://lists.linuxcoding.com/kernel/2006-q3/msg17360.html
186 *
187 * It is unclear if the misscompilations mentioned in
188 * http://lkml.org/lkml/2010/8/8/138 also affect MIPS so we keep this one
189 * until GCC 3.x has been retired before we can apply
190 * https://patchwork.linux-mips.org/patch/1541/
191 */
192
27b3db20 193#ifndef __pa_symbol
21a151d8 194#define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x), 0))
27b3db20 195#endif
1da177e4
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196
197#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
198
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199#ifdef CONFIG_FLATMEM
200
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201static inline int pfn_valid(unsigned long pfn)
202{
203 /* avoid <linux/mm.h> include hell */
204 extern unsigned long max_mapnr;
205
206 return pfn >= ARCH_PFN_OFFSET && pfn < max_mapnr;
207}
e53639d8 208
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AN
209#elif defined(CONFIG_SPARSEMEM)
210
211/* pfn_valid is defined in linux/mmzone.h */
212
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213#elif defined(CONFIG_NEED_MULTIPLE_NODES)
214
215#define pfn_valid(pfn) \
216({ \
217 unsigned long __pfn = (pfn); \
218 int __n = pfn_to_nid(__pfn); \
219 ((__n >= 0) ? (__pfn < NODE_DATA(__n)->node_start_pfn + \
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220 NODE_DATA(__n)->node_spanned_pages) \
221 : 0); \
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222})
223
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224#endif
225
99e3b942 226#define virt_to_page(kaddr) pfn_to_page(PFN_DOWN(virt_to_phys(kaddr)))
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227
228extern int __virt_addr_valid(const volatile void *kaddr);
229#define virt_addr_valid(kaddr) \
230 __virt_addr_valid((const volatile void *) (kaddr))
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231
232#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
233 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
234
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235#define UNCAC_ADDR(addr) ((addr) - PAGE_OFFSET + UNCAC_BASE)
236#define CAC_ADDR(addr) ((addr) - UNCAC_BASE + PAGE_OFFSET)
1da177e4 237
a02036e7 238#include <asm-generic/memory_model.h>
5b17e1cd 239#include <asm-generic/getorder.h>
fd4fd5aa 240
1da177e4 241#endif /* _ASM_PAGE_H */