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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle | |
7 | * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. | |
8 | */ | |
9 | #ifndef _ASM_PGTABLE_64_H | |
10 | #define _ASM_PGTABLE_64_H | |
11 | ||
344afa65 | 12 | #include <linux/compiler.h> |
1da177e4 LT |
13 | #include <linux/linkage.h> |
14 | ||
15 | #include <asm/addrspace.h> | |
16 | #include <asm/page.h> | |
17 | #include <asm/cachectl.h> | |
656be92f | 18 | #include <asm/fixmap.h> |
1da177e4 | 19 | |
9849a569 | 20 | #define __ARCH_USE_5LEVEL_HACK |
1e321fa9 | 21 | #if defined(CONFIG_PAGE_SIZE_64KB) && !defined(CONFIG_MIPS_VA_BITS_48) |
325f8a0a DD |
22 | #include <asm-generic/pgtable-nopmd.h> |
23 | #else | |
c6e8b587 | 24 | #include <asm-generic/pgtable-nopud.h> |
325f8a0a | 25 | #endif |
c6e8b587 | 26 | |
1da177e4 LT |
27 | /* |
28 | * Each address space has 2 4K pages as its page directory, giving 1024 | |
29 | * (== PTRS_PER_PGD) 8 byte pointers to pmd tables. Each pmd table is a | |
c6e8b587 RB |
30 | * single 4K page, giving 512 (== PTRS_PER_PMD) 8 byte pointers to page |
31 | * tables. Each page table is also a single 4K page, giving 512 (== | |
32 | * PTRS_PER_PTE) 8 byte ptes. Each pud entry is initialized to point to | |
33 | * invalid_pmd_table, each pmd entry is initialized to point to | |
1da177e4 LT |
34 | * invalid_pte_table, each pte is initialized to 0. When memory is low, |
35 | * and a pmd table or a page table allocation fails, empty_bad_pmd_table | |
36 | * and empty_bad_page_table is returned back to higher layer code, so | |
37 | * that the failure is recognized later on. Linux does not seem to | |
38 | * handle these failures very well though. The empty_bad_page_table has | |
39 | * invalid pte entries in it, to force page faults. | |
40 | * | |
41 | * Kernel mappings: kernel mappings are held in the swapper_pg_table. | |
42 | * The layout is identical to userspace except it's indexed with the | |
43 | * fault address - VMALLOC_START. | |
44 | */ | |
45 | ||
325f8a0a DD |
46 | |
47 | /* PGDIR_SHIFT determines what a third-level page table entry can map */ | |
48 | #ifdef __PAGETABLE_PMD_FOLDED | |
49 | #define PGDIR_SHIFT (PAGE_SHIFT + PAGE_SHIFT + PTE_ORDER - 3) | |
50 | #else | |
51 | ||
1da177e4 | 52 | /* PMD_SHIFT determines the size of the area a second-level page table can map */ |
c6e8b587 | 53 | #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 3)) |
1da177e4 LT |
54 | #define PMD_SIZE (1UL << PMD_SHIFT) |
55 | #define PMD_MASK (~(PMD_SIZE-1)) | |
56 | ||
325f8a0a | 57 | |
c6e8b587 | 58 | #define PGDIR_SHIFT (PMD_SHIFT + (PAGE_SHIFT + PMD_ORDER - 3)) |
325f8a0a | 59 | #endif |
1da177e4 LT |
60 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) |
61 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | |
62 | ||
63 | /* | |
c6e8b587 | 64 | * For 4kB page size we use a 3 level page tree and an 8kB pud, which |
1da177e4 LT |
65 | * permits us mapping 40 bits of virtual address space. |
66 | * | |
67 | * We used to implement 41 bits by having an order 1 pmd level but that seemed | |
68 | * rather pointless. | |
69 | * | |
70 | * For 8kB page size we use a 3 level page tree which permits a total of | |
71 | * 8TB of address space. Alternatively a 33-bit / 8GB organization using | |
72 | * two levels would be easy to implement. | |
73 | * | |
74 | * For 16kB page size we use a 2 level page tree which permits a total of | |
f29244a5 | 75 | * 36 bits of virtual address space. We could add a third level but it seems |
1da177e4 LT |
76 | * like at the moment there's no need for this. |
77 | * | |
78 | * For 64kB page size we use a 2 level page table tree for a total of 42 bits | |
79 | * of virtual address space. | |
80 | */ | |
81 | #ifdef CONFIG_PAGE_SIZE_4KB | |
82 | #define PGD_ORDER 1 | |
c6e8b587 | 83 | #define PUD_ORDER aieeee_attempt_to_allocate_pud |
1da177e4 LT |
84 | #define PMD_ORDER 0 |
85 | #define PTE_ORDER 0 | |
86 | #endif | |
87 | #ifdef CONFIG_PAGE_SIZE_8KB | |
88 | #define PGD_ORDER 0 | |
c6e8b587 | 89 | #define PUD_ORDER aieeee_attempt_to_allocate_pud |
1da177e4 LT |
90 | #define PMD_ORDER 0 |
91 | #define PTE_ORDER 0 | |
92 | #endif | |
93 | #ifdef CONFIG_PAGE_SIZE_16KB | |
1e321fa9 LY |
94 | #ifdef CONFIG_MIPS_VA_BITS_48 |
95 | #define PGD_ORDER 1 | |
96 | #else | |
97 | #define PGD_ORDER 0 | |
98 | #endif | |
c6e8b587 | 99 | #define PUD_ORDER aieeee_attempt_to_allocate_pud |
1da177e4 LT |
100 | #define PMD_ORDER 0 |
101 | #define PTE_ORDER 0 | |
102 | #endif | |
c52399be RB |
103 | #ifdef CONFIG_PAGE_SIZE_32KB |
104 | #define PGD_ORDER 0 | |
105 | #define PUD_ORDER aieeee_attempt_to_allocate_pud | |
106 | #define PMD_ORDER 0 | |
107 | #define PTE_ORDER 0 | |
108 | #endif | |
1da177e4 LT |
109 | #ifdef CONFIG_PAGE_SIZE_64KB |
110 | #define PGD_ORDER 0 | |
c6e8b587 | 111 | #define PUD_ORDER aieeee_attempt_to_allocate_pud |
1e321fa9 LY |
112 | #ifdef CONFIG_MIPS_VA_BITS_48 |
113 | #define PMD_ORDER 0 | |
114 | #else | |
325f8a0a | 115 | #define PMD_ORDER aieeee_attempt_to_allocate_pmd |
1e321fa9 | 116 | #endif |
1da177e4 LT |
117 | #define PTE_ORDER 0 |
118 | #endif | |
119 | ||
120 | #define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t)) | |
325f8a0a | 121 | #ifndef __PAGETABLE_PMD_FOLDED |
1da177e4 | 122 | #define PTRS_PER_PMD ((PAGE_SIZE << PMD_ORDER) / sizeof(pmd_t)) |
325f8a0a | 123 | #endif |
1da177e4 LT |
124 | #define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t)) |
125 | ||
1e321fa9 | 126 | #define USER_PTRS_PER_PGD ((TASK_SIZE64 / PGDIR_SIZE)?(TASK_SIZE64 / PGDIR_SIZE):1) |
9dbd7b91 | 127 | #define FIRST_USER_ADDRESS 0UL |
1da177e4 | 128 | |
c8f3cc0b DD |
129 | /* |
130 | * TLB refill handlers also map the vmalloc area into xuseg. Avoid | |
131 | * the first couple of pages so NULL pointer dereferences will still | |
132 | * reliably trap. | |
133 | */ | |
134 | #define VMALLOC_START (MAP_BASE + (2 * PAGE_SIZE)) | |
1da177e4 | 135 | #define VMALLOC_END \ |
c8f3cc0b | 136 | (MAP_BASE + \ |
91dfc423 GR |
137 | min(PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE, \ |
138 | (1UL << cpu_vmbits)) - (1UL << 32)) | |
139 | ||
054c51b4 | 140 | #if defined(CONFIG_MODULES) && defined(KBUILD_64BIT_SYM32) && \ |
656be92f AN |
141 | VMALLOC_START != CKSSEG |
142 | /* Load modules into 32bit-compatible segment. */ | |
143 | #define MODULE_START CKSSEG | |
144 | #define MODULE_END (FIXADDR_START-2*PAGE_SIZE) | |
656be92f | 145 | #endif |
1da177e4 LT |
146 | |
147 | #define pte_ERROR(e) \ | |
148 | printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e)) | |
325f8a0a | 149 | #ifndef __PAGETABLE_PMD_FOLDED |
1da177e4 LT |
150 | #define pmd_ERROR(e) \ |
151 | printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e)) | |
325f8a0a | 152 | #endif |
1da177e4 LT |
153 | #define pgd_ERROR(e) \ |
154 | printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e)) | |
155 | ||
c6e8b587 RB |
156 | extern pte_t invalid_pte_table[PTRS_PER_PTE]; |
157 | extern pte_t empty_bad_page_table[PTRS_PER_PTE]; | |
325f8a0a DD |
158 | |
159 | ||
160 | #ifndef __PAGETABLE_PMD_FOLDED | |
161 | /* | |
162 | * For 3-level pagetables we defines these ourselves, for 2-level the | |
163 | * definitions are supplied by <asm-generic/pgtable-nopmd.h>. | |
164 | */ | |
165 | typedef struct { unsigned long pmd; } pmd_t; | |
166 | #define pmd_val(x) ((x).pmd) | |
167 | #define __pmd(x) ((pmd_t) { (x) } ) | |
168 | ||
169 | ||
c6e8b587 | 170 | extern pmd_t invalid_pmd_table[PTRS_PER_PMD]; |
325f8a0a | 171 | #endif |
1da177e4 LT |
172 | |
173 | /* | |
1b3a6e97 | 174 | * Empty pgd/pmd entries point to the invalid_pte_table. |
1da177e4 LT |
175 | */ |
176 | static inline int pmd_none(pmd_t pmd) | |
177 | { | |
178 | return pmd_val(pmd) == (unsigned long) invalid_pte_table; | |
179 | } | |
180 | ||
344afa65 RB |
181 | static inline int pmd_bad(pmd_t pmd) |
182 | { | |
970d032f | 183 | #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
344afa65 RB |
184 | /* pmd_huge(pmd) but inline */ |
185 | if (unlikely(pmd_val(pmd) & _PAGE_HUGE)) | |
186 | return 0; | |
187 | #endif | |
188 | ||
189 | if (unlikely(pmd_val(pmd) & ~PAGE_MASK)) | |
190 | return 1; | |
191 | ||
192 | return 0; | |
193 | } | |
1da177e4 LT |
194 | |
195 | static inline int pmd_present(pmd_t pmd) | |
196 | { | |
197 | return pmd_val(pmd) != (unsigned long) invalid_pte_table; | |
198 | } | |
199 | ||
200 | static inline void pmd_clear(pmd_t *pmdp) | |
201 | { | |
202 | pmd_val(*pmdp) = ((unsigned long) invalid_pte_table); | |
203 | } | |
325f8a0a | 204 | #ifndef __PAGETABLE_PMD_FOLDED |
1da177e4 LT |
205 | |
206 | /* | |
f29244a5 | 207 | * Empty pud entries point to the invalid_pmd_table. |
1da177e4 | 208 | */ |
c6e8b587 | 209 | static inline int pud_none(pud_t pud) |
1da177e4 | 210 | { |
c6e8b587 | 211 | return pud_val(pud) == (unsigned long) invalid_pmd_table; |
1da177e4 LT |
212 | } |
213 | ||
c6e8b587 RB |
214 | static inline int pud_bad(pud_t pud) |
215 | { | |
216 | return pud_val(pud) & ~PAGE_MASK; | |
217 | } | |
1da177e4 | 218 | |
c6e8b587 | 219 | static inline int pud_present(pud_t pud) |
1da177e4 | 220 | { |
c6e8b587 | 221 | return pud_val(pud) != (unsigned long) invalid_pmd_table; |
1da177e4 LT |
222 | } |
223 | ||
c6e8b587 | 224 | static inline void pud_clear(pud_t *pudp) |
1da177e4 | 225 | { |
c6e8b587 | 226 | pud_val(*pudp) = ((unsigned long) invalid_pmd_table); |
1da177e4 | 227 | } |
325f8a0a | 228 | #endif |
1da177e4 | 229 | |
1b3a6e97 TS |
230 | #define pte_page(x) pfn_to_page(pte_pfn(x)) |
231 | ||
1da177e4 LT |
232 | #ifdef CONFIG_CPU_VR41XX |
233 | #define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2))) | |
234 | #define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot)) | |
235 | #else | |
6dd9344c DD |
236 | #define pte_pfn(x) ((unsigned long)((x).pte >> _PFN_SHIFT)) |
237 | #define pfn_pte(pfn, prot) __pte(((pfn) << _PFN_SHIFT) | pgprot_val(prot)) | |
86ea9c51 | 238 | #define pfn_pmd(pfn, prot) __pmd(((pfn) << _PFN_SHIFT) | pgprot_val(prot)) |
1da177e4 LT |
239 | #endif |
240 | ||
241 | #define __pgd_offset(address) pgd_index(address) | |
f29244a5 | 242 | #define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) |
1b3a6e97 | 243 | #define __pmd_offset(address) pmd_index(address) |
1da177e4 LT |
244 | |
245 | /* to find an entry in a kernel page-table-directory */ | |
e0cc87f5 | 246 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) |
1da177e4 | 247 | |
f29244a5 | 248 | #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) |
1b3a6e97 | 249 | #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) |
1da177e4 LT |
250 | |
251 | /* to find an entry in a page-table-directory */ | |
21a151d8 | 252 | #define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr)) |
1da177e4 | 253 | |
325f8a0a | 254 | #ifndef __PAGETABLE_PMD_FOLDED |
46a82b2d | 255 | static inline unsigned long pud_page_vaddr(pud_t pud) |
1da177e4 | 256 | { |
c6e8b587 | 257 | return pud_val(pud); |
1da177e4 | 258 | } |
c9d06962 | 259 | #define pud_phys(pud) virt_to_phys((void *)pud_val(pud)) |
46a82b2d | 260 | #define pud_page(pud) (pfn_to_page(pud_phys(pud) >> PAGE_SHIFT)) |
1da177e4 LT |
261 | |
262 | /* Find an entry in the second-level page table.. */ | |
c6e8b587 | 263 | static inline pmd_t *pmd_offset(pud_t * pud, unsigned long address) |
1da177e4 | 264 | { |
46a82b2d | 265 | return (pmd_t *) pud_page_vaddr(*pud) + pmd_index(address); |
1da177e4 | 266 | } |
325f8a0a | 267 | #endif |
1da177e4 LT |
268 | |
269 | /* Find an entry in the third-level page table.. */ | |
270 | #define __pte_offset(address) \ | |
271 | (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) | |
272 | #define pte_offset(dir, address) \ | |
5b70a317 | 273 | ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address)) |
1da177e4 | 274 | #define pte_offset_kernel(dir, address) \ |
5b70a317 | 275 | ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address)) |
1da177e4 LT |
276 | #define pte_offset_map(dir, address) \ |
277 | ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address)) | |
1da177e4 | 278 | #define pte_unmap(pte) ((void)(pte)) |
1da177e4 LT |
279 | |
280 | /* | |
281 | * Initialize a new pgd / pmd table with invalid pointers. | |
282 | */ | |
283 | extern void pgd_init(unsigned long page); | |
284 | extern void pmd_init(unsigned long page, unsigned long pagetable); | |
285 | ||
286 | /* | |
5ae03b12 DD |
287 | * Non-present pages: high 40 bits are offset, next 8 bits type, |
288 | * low 16 bits zero. | |
1da177e4 LT |
289 | */ |
290 | static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) | |
5ae03b12 | 291 | { pte_t pte; pte_val(pte) = (type << 16) | (offset << 24); return pte; } |
1da177e4 | 292 | |
5ae03b12 DD |
293 | #define __swp_type(x) (((x).val >> 16) & 0xff) |
294 | #define __swp_offset(x) ((x).val >> 24) | |
21a151d8 | 295 | #define __swp_entry(type, offset) ((swp_entry_t) { pte_val(mk_swap_pte((type), (offset))) }) |
70342287 | 296 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) |
1da177e4 LT |
297 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) |
298 | ||
1da177e4 | 299 | #endif /* _ASM_PGTABLE_64_H */ |