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1a59d1b8 | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
4cbf2bea AI |
2 | /* ********************************************************************* |
3 | * BCM1280/BCM1480 Board Support Package | |
4 | * | |
70342287 | 5 | * Memory Controller constants File: bcm1480_mc.h |
4cbf2bea AI |
6 | * |
7 | * This module contains constants and macros useful for | |
8 | * programming the memory controller. | |
9 | * | |
10 | * BCM1400 specification level: 1280-UM100-D1 (11/14/03 Review Copy) | |
11 | * | |
12 | ********************************************************************* | |
13 | * | |
14 | * Copyright 2000,2001,2002,2003 | |
15 | * Broadcom Corporation. All rights reserved. | |
16 | * | |
4cbf2bea AI |
17 | ********************************************************************* */ |
18 | ||
19 | ||
20 | #ifndef _BCM1480_MC_H | |
21 | #define _BCM1480_MC_H | |
22 | ||
a1ce3928 | 23 | #include <asm/sibyte/sb1250_defs.h> |
4cbf2bea AI |
24 | |
25 | /* | |
26 | * Memory Channel Configuration Register (Table 81) | |
27 | */ | |
28 | ||
70342287 RB |
29 | #define S_BCM1480_MC_INTLV0 0 |
30 | #define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0) | |
31 | #define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0) | |
32 | #define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0) | |
33 | #define V_BCM1480_MC_INTLV0_DEFAULT V_BCM1480_MC_INTLV0(0) | |
34 | ||
35 | #define S_BCM1480_MC_INTLV1 8 | |
36 | #define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1) | |
37 | #define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1) | |
38 | #define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1) | |
39 | #define V_BCM1480_MC_INTLV1_DEFAULT V_BCM1480_MC_INTLV1(0) | |
40 | ||
41 | #define S_BCM1480_MC_INTLV2 16 | |
42 | #define M_BCM1480_MC_INTLV2 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV2) | |
43 | #define V_BCM1480_MC_INTLV2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV2) | |
44 | #define G_BCM1480_MC_INTLV2(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV2, M_BCM1480_MC_INTLV2) | |
45 | #define V_BCM1480_MC_INTLV2_DEFAULT V_BCM1480_MC_INTLV2(0) | |
46 | ||
47 | #define S_BCM1480_MC_CS_MODE 32 | |
48 | #define M_BCM1480_MC_CS_MODE _SB_MAKEMASK(8, S_BCM1480_MC_CS_MODE) | |
49 | #define V_BCM1480_MC_CS_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS_MODE) | |
50 | #define G_BCM1480_MC_CS_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_CS_MODE, M_BCM1480_MC_CS_MODE) | |
51 | #define V_BCM1480_MC_CS_MODE_DEFAULT V_BCM1480_MC_CS_MODE(0) | |
52 | ||
53 | #define V_BCM1480_MC_CONFIG_DEFAULT (V_BCM1480_MC_INTLV0_DEFAULT | \ | |
54 | V_BCM1480_MC_INTLV1_DEFAULT | \ | |
55 | V_BCM1480_MC_INTLV2_DEFAULT | \ | |
4cbf2bea AI |
56 | V_BCM1480_MC_CS_MODE_DEFAULT) |
57 | ||
58 | #define K_BCM1480_MC_CS01_MODE 0x03 | |
59 | #define K_BCM1480_MC_CS02_MODE 0x05 | |
60 | #define K_BCM1480_MC_CS0123_MODE 0x0F | |
61 | #define K_BCM1480_MC_CS0246_MODE 0x55 | |
62 | #define K_BCM1480_MC_CS0145_MODE 0x33 | |
63 | #define K_BCM1480_MC_CS0167_MODE 0xC3 | |
64 | #define K_BCM1480_MC_CSFULL_MODE 0xFF | |
65 | ||
66 | /* | |
67 | * Chip Select Start Address Register (Table 82) | |
68 | */ | |
69 | ||
70342287 RB |
70 | #define S_BCM1480_MC_CS0_START 0 |
71 | #define M_BCM1480_MC_CS0_START _SB_MAKEMASK(12, S_BCM1480_MC_CS0_START) | |
72 | #define V_BCM1480_MC_CS0_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_START) | |
73 | #define G_BCM1480_MC_CS0_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0_START, M_BCM1480_MC_CS0_START) | |
4cbf2bea | 74 | |
70342287 RB |
75 | #define S_BCM1480_MC_CS1_START 16 |
76 | #define M_BCM1480_MC_CS1_START _SB_MAKEMASK(12, S_BCM1480_MC_CS1_START) | |
77 | #define V_BCM1480_MC_CS1_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_START) | |
78 | #define G_BCM1480_MC_CS1_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS1_START, M_BCM1480_MC_CS1_START) | |
4cbf2bea | 79 | |
70342287 RB |
80 | #define S_BCM1480_MC_CS2_START 32 |
81 | #define M_BCM1480_MC_CS2_START _SB_MAKEMASK(12, S_BCM1480_MC_CS2_START) | |
82 | #define V_BCM1480_MC_CS2_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_START) | |
83 | #define G_BCM1480_MC_CS2_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS2_START, M_BCM1480_MC_CS2_START) | |
4cbf2bea | 84 | |
70342287 RB |
85 | #define S_BCM1480_MC_CS3_START 48 |
86 | #define M_BCM1480_MC_CS3_START _SB_MAKEMASK(12, S_BCM1480_MC_CS3_START) | |
87 | #define V_BCM1480_MC_CS3_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_START) | |
88 | #define G_BCM1480_MC_CS3_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS3_START, M_BCM1480_MC_CS3_START) | |
4cbf2bea AI |
89 | |
90 | /* | |
91 | * Chip Select End Address Register (Table 83) | |
92 | */ | |
93 | ||
70342287 RB |
94 | #define S_BCM1480_MC_CS0_END 0 |
95 | #define M_BCM1480_MC_CS0_END _SB_MAKEMASK(12, S_BCM1480_MC_CS0_END) | |
96 | #define V_BCM1480_MC_CS0_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_END) | |
97 | #define G_BCM1480_MC_CS0_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0_END, M_BCM1480_MC_CS0_END) | |
4cbf2bea | 98 | |
70342287 RB |
99 | #define S_BCM1480_MC_CS1_END 16 |
100 | #define M_BCM1480_MC_CS1_END _SB_MAKEMASK(12, S_BCM1480_MC_CS1_END) | |
101 | #define V_BCM1480_MC_CS1_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_END) | |
102 | #define G_BCM1480_MC_CS1_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS1_END, M_BCM1480_MC_CS1_END) | |
4cbf2bea | 103 | |
70342287 RB |
104 | #define S_BCM1480_MC_CS2_END 32 |
105 | #define M_BCM1480_MC_CS2_END _SB_MAKEMASK(12, S_BCM1480_MC_CS2_END) | |
106 | #define V_BCM1480_MC_CS2_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_END) | |
107 | #define G_BCM1480_MC_CS2_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS2_END, M_BCM1480_MC_CS2_END) | |
4cbf2bea | 108 | |
70342287 RB |
109 | #define S_BCM1480_MC_CS3_END 48 |
110 | #define M_BCM1480_MC_CS3_END _SB_MAKEMASK(12, S_BCM1480_MC_CS3_END) | |
111 | #define V_BCM1480_MC_CS3_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_END) | |
112 | #define G_BCM1480_MC_CS3_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS3_END, M_BCM1480_MC_CS3_END) | |
4cbf2bea AI |
113 | |
114 | /* | |
115 | * Row Address Bit Select Register 0 (Table 84) | |
116 | */ | |
117 | ||
70342287 RB |
118 | #define S_BCM1480_MC_ROW00 0 |
119 | #define M_BCM1480_MC_ROW00 _SB_MAKEMASK(6, S_BCM1480_MC_ROW00) | |
120 | #define V_BCM1480_MC_ROW00(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW00) | |
121 | #define G_BCM1480_MC_ROW00(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW00, M_BCM1480_MC_ROW00) | |
122 | ||
123 | #define S_BCM1480_MC_ROW01 8 | |
124 | #define M_BCM1480_MC_ROW01 _SB_MAKEMASK(6, S_BCM1480_MC_ROW01) | |
125 | #define V_BCM1480_MC_ROW01(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW01) | |
126 | #define G_BCM1480_MC_ROW01(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW01, M_BCM1480_MC_ROW01) | |
127 | ||
128 | #define S_BCM1480_MC_ROW02 16 | |
129 | #define M_BCM1480_MC_ROW02 _SB_MAKEMASK(6, S_BCM1480_MC_ROW02) | |
130 | #define V_BCM1480_MC_ROW02(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW02) | |
131 | #define G_BCM1480_MC_ROW02(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW02, M_BCM1480_MC_ROW02) | |
132 | ||
133 | #define S_BCM1480_MC_ROW03 24 | |
134 | #define M_BCM1480_MC_ROW03 _SB_MAKEMASK(6, S_BCM1480_MC_ROW03) | |
135 | #define V_BCM1480_MC_ROW03(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW03) | |
136 | #define G_BCM1480_MC_ROW03(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW03, M_BCM1480_MC_ROW03) | |
137 | ||
138 | #define S_BCM1480_MC_ROW04 32 | |
139 | #define M_BCM1480_MC_ROW04 _SB_MAKEMASK(6, S_BCM1480_MC_ROW04) | |
140 | #define V_BCM1480_MC_ROW04(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW04) | |
141 | #define G_BCM1480_MC_ROW04(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW04, M_BCM1480_MC_ROW04) | |
142 | ||
143 | #define S_BCM1480_MC_ROW05 40 | |
144 | #define M_BCM1480_MC_ROW05 _SB_MAKEMASK(6, S_BCM1480_MC_ROW05) | |
145 | #define V_BCM1480_MC_ROW05(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW05) | |
146 | #define G_BCM1480_MC_ROW05(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW05, M_BCM1480_MC_ROW05) | |
147 | ||
148 | #define S_BCM1480_MC_ROW06 48 | |
149 | #define M_BCM1480_MC_ROW06 _SB_MAKEMASK(6, S_BCM1480_MC_ROW06) | |
150 | #define V_BCM1480_MC_ROW06(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW06) | |
151 | #define G_BCM1480_MC_ROW06(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW06, M_BCM1480_MC_ROW06) | |
152 | ||
153 | #define S_BCM1480_MC_ROW07 56 | |
154 | #define M_BCM1480_MC_ROW07 _SB_MAKEMASK(6, S_BCM1480_MC_ROW07) | |
155 | #define V_BCM1480_MC_ROW07(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW07) | |
156 | #define G_BCM1480_MC_ROW07(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW07, M_BCM1480_MC_ROW07) | |
4cbf2bea AI |
157 | |
158 | /* | |
159 | * Row Address Bit Select Register 1 (Table 85) | |
160 | */ | |
161 | ||
70342287 RB |
162 | #define S_BCM1480_MC_ROW08 0 |
163 | #define M_BCM1480_MC_ROW08 _SB_MAKEMASK(6, S_BCM1480_MC_ROW08) | |
164 | #define V_BCM1480_MC_ROW08(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW08) | |
165 | #define G_BCM1480_MC_ROW08(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW08, M_BCM1480_MC_ROW08) | |
4cbf2bea | 166 | |
70342287 RB |
167 | #define S_BCM1480_MC_ROW09 8 |
168 | #define M_BCM1480_MC_ROW09 _SB_MAKEMASK(6, S_BCM1480_MC_ROW09) | |
169 | #define V_BCM1480_MC_ROW09(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW09) | |
170 | #define G_BCM1480_MC_ROW09(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW09, M_BCM1480_MC_ROW09) | |
4cbf2bea | 171 | |
70342287 RB |
172 | #define S_BCM1480_MC_ROW10 16 |
173 | #define M_BCM1480_MC_ROW10 _SB_MAKEMASK(6, S_BCM1480_MC_ROW10) | |
174 | #define V_BCM1480_MC_ROW10(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW10) | |
175 | #define G_BCM1480_MC_ROW10(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW10, M_BCM1480_MC_ROW10) | |
4cbf2bea | 176 | |
70342287 RB |
177 | #define S_BCM1480_MC_ROW11 24 |
178 | #define M_BCM1480_MC_ROW11 _SB_MAKEMASK(6, S_BCM1480_MC_ROW11) | |
179 | #define V_BCM1480_MC_ROW11(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW11) | |
180 | #define G_BCM1480_MC_ROW11(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW11, M_BCM1480_MC_ROW11) | |
4cbf2bea | 181 | |
70342287 RB |
182 | #define S_BCM1480_MC_ROW12 32 |
183 | #define M_BCM1480_MC_ROW12 _SB_MAKEMASK(6, S_BCM1480_MC_ROW12) | |
184 | #define V_BCM1480_MC_ROW12(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW12) | |
185 | #define G_BCM1480_MC_ROW12(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW12, M_BCM1480_MC_ROW12) | |
4cbf2bea | 186 | |
70342287 RB |
187 | #define S_BCM1480_MC_ROW13 40 |
188 | #define M_BCM1480_MC_ROW13 _SB_MAKEMASK(6, S_BCM1480_MC_ROW13) | |
189 | #define V_BCM1480_MC_ROW13(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW13) | |
190 | #define G_BCM1480_MC_ROW13(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW13, M_BCM1480_MC_ROW13) | |
4cbf2bea | 191 | |
70342287 RB |
192 | #define S_BCM1480_MC_ROW14 48 |
193 | #define M_BCM1480_MC_ROW14 _SB_MAKEMASK(6, S_BCM1480_MC_ROW14) | |
194 | #define V_BCM1480_MC_ROW14(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW14) | |
195 | #define G_BCM1480_MC_ROW14(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW14, M_BCM1480_MC_ROW14) | |
4cbf2bea | 196 | |
70342287 | 197 | #define K_BCM1480_MC_ROWX_BIT_SPACING 8 |
4cbf2bea AI |
198 | |
199 | /* | |
200 | * Column Address Bit Select Register 0 (Table 86) | |
201 | */ | |
202 | ||
70342287 RB |
203 | #define S_BCM1480_MC_COL00 0 |
204 | #define M_BCM1480_MC_COL00 _SB_MAKEMASK(6, S_BCM1480_MC_COL00) | |
205 | #define V_BCM1480_MC_COL00(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL00) | |
206 | #define G_BCM1480_MC_COL00(x) _SB_GETVALUE(x, S_BCM1480_MC_COL00, M_BCM1480_MC_COL00) | |
207 | ||
208 | #define S_BCM1480_MC_COL01 8 | |
209 | #define M_BCM1480_MC_COL01 _SB_MAKEMASK(6, S_BCM1480_MC_COL01) | |
210 | #define V_BCM1480_MC_COL01(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL01) | |
211 | #define G_BCM1480_MC_COL01(x) _SB_GETVALUE(x, S_BCM1480_MC_COL01, M_BCM1480_MC_COL01) | |
212 | ||
213 | #define S_BCM1480_MC_COL02 16 | |
214 | #define M_BCM1480_MC_COL02 _SB_MAKEMASK(6, S_BCM1480_MC_COL02) | |
215 | #define V_BCM1480_MC_COL02(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL02) | |
216 | #define G_BCM1480_MC_COL02(x) _SB_GETVALUE(x, S_BCM1480_MC_COL02, M_BCM1480_MC_COL02) | |
217 | ||
218 | #define S_BCM1480_MC_COL03 24 | |
219 | #define M_BCM1480_MC_COL03 _SB_MAKEMASK(6, S_BCM1480_MC_COL03) | |
220 | #define V_BCM1480_MC_COL03(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL03) | |
221 | #define G_BCM1480_MC_COL03(x) _SB_GETVALUE(x, S_BCM1480_MC_COL03, M_BCM1480_MC_COL03) | |
222 | ||
223 | #define S_BCM1480_MC_COL04 32 | |
224 | #define M_BCM1480_MC_COL04 _SB_MAKEMASK(6, S_BCM1480_MC_COL04) | |
225 | #define V_BCM1480_MC_COL04(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL04) | |
226 | #define G_BCM1480_MC_COL04(x) _SB_GETVALUE(x, S_BCM1480_MC_COL04, M_BCM1480_MC_COL04) | |
227 | ||
228 | #define S_BCM1480_MC_COL05 40 | |
229 | #define M_BCM1480_MC_COL05 _SB_MAKEMASK(6, S_BCM1480_MC_COL05) | |
230 | #define V_BCM1480_MC_COL05(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL05) | |
231 | #define G_BCM1480_MC_COL05(x) _SB_GETVALUE(x, S_BCM1480_MC_COL05, M_BCM1480_MC_COL05) | |
232 | ||
233 | #define S_BCM1480_MC_COL06 48 | |
234 | #define M_BCM1480_MC_COL06 _SB_MAKEMASK(6, S_BCM1480_MC_COL06) | |
235 | #define V_BCM1480_MC_COL06(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL06) | |
236 | #define G_BCM1480_MC_COL06(x) _SB_GETVALUE(x, S_BCM1480_MC_COL06, M_BCM1480_MC_COL06) | |
237 | ||
238 | #define S_BCM1480_MC_COL07 56 | |
239 | #define M_BCM1480_MC_COL07 _SB_MAKEMASK(6, S_BCM1480_MC_COL07) | |
240 | #define V_BCM1480_MC_COL07(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL07) | |
241 | #define G_BCM1480_MC_COL07(x) _SB_GETVALUE(x, S_BCM1480_MC_COL07, M_BCM1480_MC_COL07) | |
4cbf2bea AI |
242 | |
243 | /* | |
244 | * Column Address Bit Select Register 1 (Table 87) | |
245 | */ | |
246 | ||
70342287 RB |
247 | #define S_BCM1480_MC_COL08 0 |
248 | #define M_BCM1480_MC_COL08 _SB_MAKEMASK(6, S_BCM1480_MC_COL08) | |
249 | #define V_BCM1480_MC_COL08(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL08) | |
250 | #define G_BCM1480_MC_COL08(x) _SB_GETVALUE(x, S_BCM1480_MC_COL08, M_BCM1480_MC_COL08) | |
4cbf2bea | 251 | |
70342287 RB |
252 | #define S_BCM1480_MC_COL09 8 |
253 | #define M_BCM1480_MC_COL09 _SB_MAKEMASK(6, S_BCM1480_MC_COL09) | |
254 | #define V_BCM1480_MC_COL09(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL09) | |
255 | #define G_BCM1480_MC_COL09(x) _SB_GETVALUE(x, S_BCM1480_MC_COL09, M_BCM1480_MC_COL09) | |
4cbf2bea | 256 | |
70342287 | 257 | #define S_BCM1480_MC_COL10 16 /* not a valid position, must be prog as 0 */ |
4cbf2bea | 258 | |
70342287 RB |
259 | #define S_BCM1480_MC_COL11 24 |
260 | #define M_BCM1480_MC_COL11 _SB_MAKEMASK(6, S_BCM1480_MC_COL11) | |
261 | #define V_BCM1480_MC_COL11(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL11) | |
262 | #define G_BCM1480_MC_COL11(x) _SB_GETVALUE(x, S_BCM1480_MC_COL11, M_BCM1480_MC_COL11) | |
4cbf2bea | 263 | |
70342287 RB |
264 | #define S_BCM1480_MC_COL12 32 |
265 | #define M_BCM1480_MC_COL12 _SB_MAKEMASK(6, S_BCM1480_MC_COL12) | |
266 | #define V_BCM1480_MC_COL12(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL12) | |
267 | #define G_BCM1480_MC_COL12(x) _SB_GETVALUE(x, S_BCM1480_MC_COL12, M_BCM1480_MC_COL12) | |
4cbf2bea | 268 | |
70342287 RB |
269 | #define S_BCM1480_MC_COL13 40 |
270 | #define M_BCM1480_MC_COL13 _SB_MAKEMASK(6, S_BCM1480_MC_COL13) | |
271 | #define V_BCM1480_MC_COL13(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL13) | |
272 | #define G_BCM1480_MC_COL13(x) _SB_GETVALUE(x, S_BCM1480_MC_COL13, M_BCM1480_MC_COL13) | |
4cbf2bea | 273 | |
70342287 RB |
274 | #define S_BCM1480_MC_COL14 48 |
275 | #define M_BCM1480_MC_COL14 _SB_MAKEMASK(6, S_BCM1480_MC_COL14) | |
276 | #define V_BCM1480_MC_COL14(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL14) | |
277 | #define G_BCM1480_MC_COL14(x) _SB_GETVALUE(x, S_BCM1480_MC_COL14, M_BCM1480_MC_COL14) | |
4cbf2bea | 278 | |
70342287 | 279 | #define K_BCM1480_MC_COLX_BIT_SPACING 8 |
4cbf2bea AI |
280 | |
281 | /* | |
282 | * CS0 and CS1 Bank Address Bit Select Register (Table 88) | |
283 | */ | |
284 | ||
70342287 RB |
285 | #define S_BCM1480_MC_CS01_BANK0 0 |
286 | #define M_BCM1480_MC_CS01_BANK0 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK0) | |
287 | #define V_BCM1480_MC_CS01_BANK0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK0) | |
288 | #define G_BCM1480_MC_CS01_BANK0(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK0, M_BCM1480_MC_CS01_BANK0) | |
4cbf2bea | 289 | |
70342287 RB |
290 | #define S_BCM1480_MC_CS01_BANK1 8 |
291 | #define M_BCM1480_MC_CS01_BANK1 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK1) | |
292 | #define V_BCM1480_MC_CS01_BANK1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK1) | |
293 | #define G_BCM1480_MC_CS01_BANK1(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK1, M_BCM1480_MC_CS01_BANK1) | |
4cbf2bea | 294 | |
70342287 RB |
295 | #define S_BCM1480_MC_CS01_BANK2 16 |
296 | #define M_BCM1480_MC_CS01_BANK2 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK2) | |
297 | #define V_BCM1480_MC_CS01_BANK2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK2) | |
298 | #define G_BCM1480_MC_CS01_BANK2(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK2, M_BCM1480_MC_CS01_BANK2) | |
4cbf2bea AI |
299 | |
300 | /* | |
301 | * CS2 and CS3 Bank Address Bit Select Register (Table 89) | |
302 | */ | |
303 | ||
70342287 RB |
304 | #define S_BCM1480_MC_CS23_BANK0 0 |
305 | #define M_BCM1480_MC_CS23_BANK0 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK0) | |
306 | #define V_BCM1480_MC_CS23_BANK0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK0) | |
307 | #define G_BCM1480_MC_CS23_BANK0(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK0, M_BCM1480_MC_CS23_BANK0) | |
4cbf2bea | 308 | |
70342287 RB |
309 | #define S_BCM1480_MC_CS23_BANK1 8 |
310 | #define M_BCM1480_MC_CS23_BANK1 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK1) | |
311 | #define V_BCM1480_MC_CS23_BANK1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK1) | |
312 | #define G_BCM1480_MC_CS23_BANK1(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK1, M_BCM1480_MC_CS23_BANK1) | |
4cbf2bea | 313 | |
70342287 RB |
314 | #define S_BCM1480_MC_CS23_BANK2 16 |
315 | #define M_BCM1480_MC_CS23_BANK2 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK2) | |
316 | #define V_BCM1480_MC_CS23_BANK2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK2) | |
317 | #define G_BCM1480_MC_CS23_BANK2(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK2, M_BCM1480_MC_CS23_BANK2) | |
4cbf2bea AI |
318 | |
319 | #define K_BCM1480_MC_CSXX_BANKX_BIT_SPACING 8 | |
320 | ||
321 | /* | |
322 | * DRAM Command Register (Table 90) | |
323 | */ | |
324 | ||
70342287 RB |
325 | #define S_BCM1480_MC_COMMAND 0 |
326 | #define M_BCM1480_MC_COMMAND _SB_MAKEMASK(4, S_BCM1480_MC_COMMAND) | |
327 | #define V_BCM1480_MC_COMMAND(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COMMAND) | |
328 | #define G_BCM1480_MC_COMMAND(x) _SB_GETVALUE(x, S_BCM1480_MC_COMMAND, M_BCM1480_MC_COMMAND) | |
4cbf2bea | 329 | |
70342287 RB |
330 | #define K_BCM1480_MC_COMMAND_EMRS 0 |
331 | #define K_BCM1480_MC_COMMAND_MRS 1 | |
332 | #define K_BCM1480_MC_COMMAND_PRE 2 | |
333 | #define K_BCM1480_MC_COMMAND_AR 3 | |
334 | #define K_BCM1480_MC_COMMAND_SETRFSH 4 | |
335 | #define K_BCM1480_MC_COMMAND_CLRRFSH 5 | |
336 | #define K_BCM1480_MC_COMMAND_SETPWRDN 6 | |
337 | #define K_BCM1480_MC_COMMAND_CLRPWRDN 7 | |
4cbf2bea AI |
338 | |
339 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | |
340 | #define K_BCM1480_MC_COMMAND_EMRS2 8 | |
341 | #define K_BCM1480_MC_COMMAND_EMRS3 9 | |
342 | #define K_BCM1480_MC_COMMAND_ENABLE_MCLK 10 | |
343 | #define K_BCM1480_MC_COMMAND_DISABLE_MCLK 11 | |
344 | #endif | |
345 | ||
70342287 RB |
346 | #define V_BCM1480_MC_COMMAND_EMRS V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS) |
347 | #define V_BCM1480_MC_COMMAND_MRS V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_MRS) | |
348 | #define V_BCM1480_MC_COMMAND_PRE V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_PRE) | |
349 | #define V_BCM1480_MC_COMMAND_AR V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_AR) | |
350 | #define V_BCM1480_MC_COMMAND_SETRFSH V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETRFSH) | |
351 | #define V_BCM1480_MC_COMMAND_CLRRFSH V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRRFSH) | |
352 | #define V_BCM1480_MC_COMMAND_SETPWRDN V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETPWRDN) | |
353 | #define V_BCM1480_MC_COMMAND_CLRPWRDN V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRPWRDN) | |
4cbf2bea AI |
354 | |
355 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | |
70342287 RB |
356 | #define V_BCM1480_MC_COMMAND_EMRS2 V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS2) |
357 | #define V_BCM1480_MC_COMMAND_EMRS3 V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS3) | |
4cbf2bea AI |
358 | #define V_BCM1480_MC_COMMAND_ENABLE_MCLK V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_ENABLE_MCLK) |
359 | #define V_BCM1480_MC_COMMAND_DISABLE_MCLK V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_DISABLE_MCLK) | |
360 | #endif | |
361 | ||
362 | #define S_BCM1480_MC_CS0 4 | |
70342287 RB |
363 | #define M_BCM1480_MC_CS0 _SB_MAKEMASK1(4) |
364 | #define M_BCM1480_MC_CS1 _SB_MAKEMASK1(5) | |
365 | #define M_BCM1480_MC_CS2 _SB_MAKEMASK1(6) | |
366 | #define M_BCM1480_MC_CS3 _SB_MAKEMASK1(7) | |
367 | #define M_BCM1480_MC_CS4 _SB_MAKEMASK1(8) | |
368 | #define M_BCM1480_MC_CS5 _SB_MAKEMASK1(9) | |
369 | #define M_BCM1480_MC_CS6 _SB_MAKEMASK1(10) | |
370 | #define M_BCM1480_MC_CS7 _SB_MAKEMASK1(11) | |
4cbf2bea | 371 | |
70342287 RB |
372 | #define M_BCM1480_MC_CS _SB_MAKEMASK(8, S_BCM1480_MC_CS0) |
373 | #define V_BCM1480_MC_CS(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0) | |
374 | #define G_BCM1480_MC_CS(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0, M_BCM1480_MC_CS0) | |
8deab114 | 375 | |
70342287 | 376 | #define M_BCM1480_MC_CMD_ACTIVE _SB_MAKEMASK1(16) |
4cbf2bea AI |
377 | |
378 | /* | |
379 | * DRAM Mode Register (Table 91) | |
380 | */ | |
381 | ||
70342287 RB |
382 | #define S_BCM1480_MC_EMODE 0 |
383 | #define M_BCM1480_MC_EMODE _SB_MAKEMASK(15, S_BCM1480_MC_EMODE) | |
384 | #define V_BCM1480_MC_EMODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_EMODE) | |
385 | #define G_BCM1480_MC_EMODE(x) _SB_GETVALUE(x, S_BCM1480_MC_EMODE, M_BCM1480_MC_EMODE) | |
386 | #define V_BCM1480_MC_EMODE_DEFAULT V_BCM1480_MC_EMODE(0) | |
4cbf2bea | 387 | |
70342287 RB |
388 | #define S_BCM1480_MC_MODE 16 |
389 | #define M_BCM1480_MC_MODE _SB_MAKEMASK(15, S_BCM1480_MC_MODE) | |
390 | #define V_BCM1480_MC_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_MODE) | |
391 | #define G_BCM1480_MC_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_MODE, M_BCM1480_MC_MODE) | |
392 | #define V_BCM1480_MC_MODE_DEFAULT V_BCM1480_MC_MODE(0) | |
4cbf2bea | 393 | |
70342287 RB |
394 | #define S_BCM1480_MC_DRAM_TYPE 32 |
395 | #define M_BCM1480_MC_DRAM_TYPE _SB_MAKEMASK(4, S_BCM1480_MC_DRAM_TYPE) | |
396 | #define V_BCM1480_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DRAM_TYPE) | |
397 | #define G_BCM1480_MC_DRAM_TYPE(x) _SB_GETVALUE(x, S_BCM1480_MC_DRAM_TYPE, M_BCM1480_MC_DRAM_TYPE) | |
4cbf2bea | 398 | |
70342287 RB |
399 | #define K_BCM1480_MC_DRAM_TYPE_JEDEC 0 |
400 | #define K_BCM1480_MC_DRAM_TYPE_FCRAM 1 | |
4cbf2bea AI |
401 | |
402 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | |
403 | #define K_BCM1480_MC_DRAM_TYPE_DDR2 2 | |
404 | #endif | |
405 | ||
8deab114 MM |
406 | #define K_BCM1480_MC_DRAM_TYPE_DDR2_PASS1 0 |
407 | ||
70342287 RB |
408 | #define V_BCM1480_MC_DRAM_TYPE_JEDEC V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_JEDEC) |
409 | #define V_BCM1480_MC_DRAM_TYPE_FCRAM V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_FCRAM) | |
4cbf2bea AI |
410 | |
411 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | |
412 | #define V_BCM1480_MC_DRAM_TYPE_DDR2 V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_DDR2) | |
413 | #endif | |
414 | ||
70342287 RB |
415 | #define M_BCM1480_MC_GANGED _SB_MAKEMASK1(36) |
416 | #define M_BCM1480_MC_BY9_INTF _SB_MAKEMASK1(37) | |
417 | #define M_BCM1480_MC_FORCE_ECC64 _SB_MAKEMASK1(38) | |
418 | #define M_BCM1480_MC_ECC_DISABLE _SB_MAKEMASK1(39) | |
4cbf2bea | 419 | |
70342287 RB |
420 | #define S_BCM1480_MC_PG_POLICY 40 |
421 | #define M_BCM1480_MC_PG_POLICY _SB_MAKEMASK(2, S_BCM1480_MC_PG_POLICY) | |
422 | #define V_BCM1480_MC_PG_POLICY(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PG_POLICY) | |
423 | #define G_BCM1480_MC_PG_POLICY(x) _SB_GETVALUE(x, S_BCM1480_MC_PG_POLICY, M_BCM1480_MC_PG_POLICY) | |
4cbf2bea | 424 | |
70342287 | 425 | #define K_BCM1480_MC_PG_POLICY_CLOSED 0 |
4cbf2bea AI |
426 | #define K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK 1 |
427 | ||
70342287 | 428 | #define V_BCM1480_MC_PG_POLICY_CLOSED V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CLOSED) |
4cbf2bea AI |
429 | #define V_BCM1480_MC_PG_POLICY_CAS_TIME_CHK V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK) |
430 | ||
431 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | |
432 | #define M_BCM1480_MC_2T_CMD _SB_MAKEMASK1(42) | |
433 | #define M_BCM1480_MC_ECC_COR_DIS _SB_MAKEMASK1(43) | |
434 | #endif | |
435 | ||
436 | #define V_BCM1480_MC_DRAMMODE_DEFAULT V_BCM1480_MC_EMODE_DEFAULT | V_BCM1480_MC_MODE_DEFAULT | V_BCM1480_MC_DRAM_TYPE_JEDEC | \ | |
70342287 | 437 | V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK) |
4cbf2bea AI |
438 | |
439 | /* | |
440 | * Memory Clock Configuration Register (Table 92) | |
441 | */ | |
442 | ||
70342287 RB |
443 | #define S_BCM1480_MC_CLK_RATIO 0 |
444 | #define M_BCM1480_MC_CLK_RATIO _SB_MAKEMASK(6, S_BCM1480_MC_CLK_RATIO) | |
445 | #define V_BCM1480_MC_CLK_RATIO(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CLK_RATIO) | |
446 | #define G_BCM1480_MC_CLK_RATIO(x) _SB_GETVALUE(x, S_BCM1480_MC_CLK_RATIO, M_BCM1480_MC_CLK_RATIO) | |
4cbf2bea | 447 | |
70342287 | 448 | #define V_BCM1480_MC_CLK_RATIO_DEFAULT V_BCM1480_MC_CLK_RATIO(10) |
4cbf2bea | 449 | |
70342287 RB |
450 | #define S_BCM1480_MC_REF_RATE 8 |
451 | #define M_BCM1480_MC_REF_RATE _SB_MAKEMASK(8, S_BCM1480_MC_REF_RATE) | |
452 | #define V_BCM1480_MC_REF_RATE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_REF_RATE) | |
453 | #define G_BCM1480_MC_REF_RATE(x) _SB_GETVALUE(x, S_BCM1480_MC_REF_RATE, M_BCM1480_MC_REF_RATE) | |
4cbf2bea | 454 | |
70342287 RB |
455 | #define K_BCM1480_MC_REF_RATE_100MHz 0x31 |
456 | #define K_BCM1480_MC_REF_RATE_200MHz 0x62 | |
457 | #define K_BCM1480_MC_REF_RATE_400MHz 0xC4 | |
4cbf2bea | 458 | |
70342287 RB |
459 | #define V_BCM1480_MC_REF_RATE_100MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_100MHz) |
460 | #define V_BCM1480_MC_REF_RATE_200MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_200MHz) | |
461 | #define V_BCM1480_MC_REF_RATE_400MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_400MHz) | |
462 | #define V_BCM1480_MC_REF_RATE_DEFAULT V_BCM1480_MC_REF_RATE_400MHz | |
4cbf2bea AI |
463 | |
464 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | |
465 | #define M_BCM1480_MC_AUTO_REF_DIS _SB_MAKEMASK1(16) | |
466 | #endif | |
467 | ||
468 | /* | |
469 | * ODT Register (Table 99) | |
470 | */ | |
471 | ||
472 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | |
473 | #define M_BCM1480_MC_RD_ODT0_CS0 _SB_MAKEMASK1(0) | |
474 | #define M_BCM1480_MC_RD_ODT0_CS2 _SB_MAKEMASK1(1) | |
475 | #define M_BCM1480_MC_RD_ODT0_CS4 _SB_MAKEMASK1(2) | |
476 | #define M_BCM1480_MC_RD_ODT0_CS6 _SB_MAKEMASK1(3) | |
477 | #define M_BCM1480_MC_WR_ODT0_CS0 _SB_MAKEMASK1(4) | |
478 | #define M_BCM1480_MC_WR_ODT0_CS2 _SB_MAKEMASK1(5) | |
479 | #define M_BCM1480_MC_WR_ODT0_CS4 _SB_MAKEMASK1(6) | |
480 | #define M_BCM1480_MC_WR_ODT0_CS6 _SB_MAKEMASK1(7) | |
481 | #define M_BCM1480_MC_RD_ODT2_CS0 _SB_MAKEMASK1(8) | |
482 | #define M_BCM1480_MC_RD_ODT2_CS2 _SB_MAKEMASK1(9) | |
483 | #define M_BCM1480_MC_RD_ODT2_CS4 _SB_MAKEMASK1(10) | |
484 | #define M_BCM1480_MC_RD_ODT2_CS6 _SB_MAKEMASK1(11) | |
485 | #define M_BCM1480_MC_WR_ODT2_CS0 _SB_MAKEMASK1(12) | |
486 | #define M_BCM1480_MC_WR_ODT2_CS2 _SB_MAKEMASK1(13) | |
487 | #define M_BCM1480_MC_WR_ODT2_CS4 _SB_MAKEMASK1(14) | |
488 | #define M_BCM1480_MC_WR_ODT2_CS6 _SB_MAKEMASK1(15) | |
489 | #define M_BCM1480_MC_RD_ODT4_CS0 _SB_MAKEMASK1(16) | |
490 | #define M_BCM1480_MC_RD_ODT4_CS2 _SB_MAKEMASK1(17) | |
491 | #define M_BCM1480_MC_RD_ODT4_CS4 _SB_MAKEMASK1(18) | |
492 | #define M_BCM1480_MC_RD_ODT4_CS6 _SB_MAKEMASK1(19) | |
493 | #define M_BCM1480_MC_WR_ODT4_CS0 _SB_MAKEMASK1(20) | |
494 | #define M_BCM1480_MC_WR_ODT4_CS2 _SB_MAKEMASK1(21) | |
495 | #define M_BCM1480_MC_WR_ODT4_CS4 _SB_MAKEMASK1(22) | |
496 | #define M_BCM1480_MC_WR_ODT4_CS6 _SB_MAKEMASK1(23) | |
497 | #define M_BCM1480_MC_RD_ODT6_CS0 _SB_MAKEMASK1(24) | |
498 | #define M_BCM1480_MC_RD_ODT6_CS2 _SB_MAKEMASK1(25) | |
499 | #define M_BCM1480_MC_RD_ODT6_CS4 _SB_MAKEMASK1(26) | |
500 | #define M_BCM1480_MC_RD_ODT6_CS6 _SB_MAKEMASK1(27) | |
501 | #define M_BCM1480_MC_WR_ODT6_CS0 _SB_MAKEMASK1(28) | |
502 | #define M_BCM1480_MC_WR_ODT6_CS2 _SB_MAKEMASK1(29) | |
503 | #define M_BCM1480_MC_WR_ODT6_CS4 _SB_MAKEMASK1(30) | |
504 | #define M_BCM1480_MC_WR_ODT6_CS6 _SB_MAKEMASK1(31) | |
505 | ||
506 | #define M_BCM1480_MC_CS_ODD_ODT_EN _SB_MAKEMASK1(32) | |
8deab114 | 507 | |
70342287 | 508 | #define S_BCM1480_MC_ODT0 0 |
21a151d8 RB |
509 | #define M_BCM1480_MC_ODT0 _SB_MAKEMASK(8, S_BCM1480_MC_ODT0) |
510 | #define V_BCM1480_MC_ODT0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT0) | |
8deab114 | 511 | |
70342287 | 512 | #define S_BCM1480_MC_ODT2 8 |
21a151d8 RB |
513 | #define M_BCM1480_MC_ODT2 _SB_MAKEMASK(8, S_BCM1480_MC_ODT2) |
514 | #define V_BCM1480_MC_ODT2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT2) | |
8deab114 | 515 | |
70342287 | 516 | #define S_BCM1480_MC_ODT4 16 |
21a151d8 RB |
517 | #define M_BCM1480_MC_ODT4 _SB_MAKEMASK(8, S_BCM1480_MC_ODT4) |
518 | #define V_BCM1480_MC_ODT4(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT4) | |
8deab114 | 519 | |
70342287 | 520 | #define S_BCM1480_MC_ODT6 24 |
21a151d8 RB |
521 | #define M_BCM1480_MC_ODT6 _SB_MAKEMASK(8, S_BCM1480_MC_ODT6) |
522 | #define V_BCM1480_MC_ODT6(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT6) | |
4cbf2bea AI |
523 | #endif |
524 | ||
525 | /* | |
526 | * Memory DLL Configuration Register (Table 93) | |
527 | */ | |
528 | ||
70342287 RB |
529 | #define S_BCM1480_MC_ADDR_COARSE_ADJ 0 |
530 | #define M_BCM1480_MC_ADDR_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_ADDR_COARSE_ADJ) | |
531 | #define V_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_COARSE_ADJ) | |
532 | #define G_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_COARSE_ADJ, M_BCM1480_MC_ADDR_COARSE_ADJ) | |
4cbf2bea AI |
533 | #define V_BCM1480_MC_ADDR_COARSE_ADJ_DEFAULT V_BCM1480_MC_ADDR_COARSE_ADJ(0x0) |
534 | ||
535 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | |
70342287 RB |
536 | #define S_BCM1480_MC_ADDR_FREQ_RANGE 8 |
537 | #define M_BCM1480_MC_ADDR_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_ADDR_FREQ_RANGE) | |
538 | #define V_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_FREQ_RANGE) | |
539 | #define G_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_FREQ_RANGE, M_BCM1480_MC_ADDR_FREQ_RANGE) | |
540 | #define V_BCM1480_MC_ADDR_FREQ_RANGE_DEFAULT V_BCM1480_MC_ADDR_FREQ_RANGE(0x4) | |
4cbf2bea AI |
541 | #endif |
542 | ||
70342287 RB |
543 | #define S_BCM1480_MC_ADDR_FINE_ADJ 8 |
544 | #define M_BCM1480_MC_ADDR_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_ADDR_FINE_ADJ) | |
545 | #define V_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_FINE_ADJ) | |
546 | #define G_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_FINE_ADJ, M_BCM1480_MC_ADDR_FINE_ADJ) | |
4cbf2bea AI |
547 | #define V_BCM1480_MC_ADDR_FINE_ADJ_DEFAULT V_BCM1480_MC_ADDR_FINE_ADJ(0x8) |
548 | ||
70342287 RB |
549 | #define S_BCM1480_MC_DQI_COARSE_ADJ 16 |
550 | #define M_BCM1480_MC_DQI_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_DQI_COARSE_ADJ) | |
551 | #define V_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_COARSE_ADJ) | |
552 | #define G_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_COARSE_ADJ, M_BCM1480_MC_DQI_COARSE_ADJ) | |
4cbf2bea AI |
553 | #define V_BCM1480_MC_DQI_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQI_COARSE_ADJ(0x0) |
554 | ||
555 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | |
70342287 RB |
556 | #define S_BCM1480_MC_DQI_FREQ_RANGE 24 |
557 | #define M_BCM1480_MC_DQI_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DQI_FREQ_RANGE) | |
558 | #define V_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_FREQ_RANGE) | |
559 | #define G_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_FREQ_RANGE, M_BCM1480_MC_DQI_FREQ_RANGE) | |
560 | #define V_BCM1480_MC_DQI_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQI_FREQ_RANGE(0x4) | |
4cbf2bea AI |
561 | #endif |
562 | ||
70342287 RB |
563 | #define S_BCM1480_MC_DQI_FINE_ADJ 24 |
564 | #define M_BCM1480_MC_DQI_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_DQI_FINE_ADJ) | |
565 | #define V_BCM1480_MC_DQI_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_FINE_ADJ) | |
566 | #define G_BCM1480_MC_DQI_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_FINE_ADJ, M_BCM1480_MC_DQI_FINE_ADJ) | |
4cbf2bea AI |
567 | #define V_BCM1480_MC_DQI_FINE_ADJ_DEFAULT V_BCM1480_MC_DQI_FINE_ADJ(0x8) |
568 | ||
70342287 RB |
569 | #define S_BCM1480_MC_DQO_COARSE_ADJ 32 |
570 | #define M_BCM1480_MC_DQO_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_DQO_COARSE_ADJ) | |
571 | #define V_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_COARSE_ADJ) | |
572 | #define G_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_COARSE_ADJ, M_BCM1480_MC_DQO_COARSE_ADJ) | |
4cbf2bea AI |
573 | #define V_BCM1480_MC_DQO_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQO_COARSE_ADJ(0x0) |
574 | ||
575 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | |
70342287 RB |
576 | #define S_BCM1480_MC_DQO_FREQ_RANGE 40 |
577 | #define M_BCM1480_MC_DQO_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DQO_FREQ_RANGE) | |
578 | #define V_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_FREQ_RANGE) | |
579 | #define G_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_FREQ_RANGE, M_BCM1480_MC_DQO_FREQ_RANGE) | |
580 | #define V_BCM1480_MC_DQO_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQO_FREQ_RANGE(0x4) | |
4cbf2bea AI |
581 | #endif |
582 | ||
70342287 RB |
583 | #define S_BCM1480_MC_DQO_FINE_ADJ 40 |
584 | #define M_BCM1480_MC_DQO_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_DQO_FINE_ADJ) | |
585 | #define V_BCM1480_MC_DQO_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_FINE_ADJ) | |
586 | #define G_BCM1480_MC_DQO_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_FINE_ADJ, M_BCM1480_MC_DQO_FINE_ADJ) | |
4cbf2bea AI |
587 | #define V_BCM1480_MC_DQO_FINE_ADJ_DEFAULT V_BCM1480_MC_DQO_FINE_ADJ(0x8) |
588 | ||
589 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | |
70342287 RB |
590 | #define S_BCM1480_MC_DLL_PDSEL 44 |
591 | #define M_BCM1480_MC_DLL_PDSEL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_PDSEL) | |
592 | #define V_BCM1480_MC_DLL_PDSEL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_PDSEL) | |
593 | #define G_BCM1480_MC_DLL_PDSEL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_PDSEL, M_BCM1480_MC_DLL_PDSEL) | |
594 | #define V_BCM1480_MC_DLL_DEFAULT_PDSEL V_BCM1480_MC_DLL_PDSEL(0x0) | |
595 | ||
596 | #define M_BCM1480_MC_DLL_REGBYPASS _SB_MAKEMASK1(46) | |
597 | #define M_BCM1480_MC_DQO_SHIFT _SB_MAKEMASK1(47) | |
4cbf2bea AI |
598 | #endif |
599 | ||
70342287 RB |
600 | #define S_BCM1480_MC_DLL_DEFAULT 48 |
601 | #define M_BCM1480_MC_DLL_DEFAULT _SB_MAKEMASK(6, S_BCM1480_MC_DLL_DEFAULT) | |
602 | #define V_BCM1480_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_DEFAULT) | |
603 | #define G_BCM1480_MC_DLL_DEFAULT(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_DEFAULT, M_BCM1480_MC_DLL_DEFAULT) | |
8deab114 | 604 | #define V_BCM1480_MC_DLL_DEFAULT_DEFAULT V_BCM1480_MC_DLL_DEFAULT(0x10) |
4cbf2bea AI |
605 | |
606 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | |
607 | #define S_BCM1480_MC_DLL_REGCTRL 54 | |
70342287 RB |
608 | #define M_BCM1480_MC_DLL_REGCTRL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_REGCTRL) |
609 | #define V_BCM1480_MC_DLL_REGCTRL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_REGCTRL) | |
610 | #define G_BCM1480_MC_DLL_REGCTRL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_REGCTRL, M_BCM1480_MC_DLL_REGCTRL) | |
4cbf2bea AI |
611 | #define V_BCM1480_MC_DLL_DEFAULT_REGCTRL V_BCM1480_MC_DLL_REGCTRL(0x0) |
612 | #endif | |
613 | ||
614 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | |
70342287 RB |
615 | #define S_BCM1480_MC_DLL_FREQ_RANGE 56 |
616 | #define M_BCM1480_MC_DLL_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DLL_FREQ_RANGE) | |
617 | #define V_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_FREQ_RANGE) | |
618 | #define G_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_FREQ_RANGE, M_BCM1480_MC_DLL_FREQ_RANGE) | |
619 | #define V_BCM1480_MC_DLL_FREQ_RANGE_DEFAULT V_BCM1480_MC_DLL_FREQ_RANGE(0x4) | |
4cbf2bea AI |
620 | #endif |
621 | ||
70342287 RB |
622 | #define S_BCM1480_MC_DLL_STEP_SIZE 56 |
623 | #define M_BCM1480_MC_DLL_STEP_SIZE _SB_MAKEMASK(4, S_BCM1480_MC_DLL_STEP_SIZE) | |
624 | #define V_BCM1480_MC_DLL_STEP_SIZE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_STEP_SIZE) | |
625 | #define G_BCM1480_MC_DLL_STEP_SIZE(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_STEP_SIZE, M_BCM1480_MC_DLL_STEP_SIZE) | |
4cbf2bea AI |
626 | #define V_BCM1480_MC_DLL_STEP_SIZE_DEFAULT V_BCM1480_MC_DLL_STEP_SIZE(0x8) |
627 | ||
628 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | |
629 | #define S_BCM1480_MC_DLL_BGCTRL 60 | |
70342287 RB |
630 | #define M_BCM1480_MC_DLL_BGCTRL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_BGCTRL) |
631 | #define V_BCM1480_MC_DLL_BGCTRL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_BGCTRL) | |
632 | #define G_BCM1480_MC_DLL_BGCTRL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_BGCTRL, M_BCM1480_MC_DLL_BGCTRL) | |
633 | #define V_BCM1480_MC_DLL_DEFAULT_BGCTRL V_BCM1480_MC_DLL_BGCTRL(0x0) | |
4cbf2bea AI |
634 | #endif |
635 | ||
70342287 | 636 | #define M_BCM1480_MC_DLL_BYPASS _SB_MAKEMASK1(63) |
4cbf2bea AI |
637 | |
638 | /* | |
639 | * Memory Drive Configuration Register (Table 94) | |
640 | */ | |
641 | ||
70342287 RB |
642 | #define S_BCM1480_MC_RTT_BYP_PULLDOWN 0 |
643 | #define M_BCM1480_MC_RTT_BYP_PULLDOWN _SB_MAKEMASK(3, S_BCM1480_MC_RTT_BYP_PULLDOWN) | |
21a151d8 RB |
644 | #define V_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_RTT_BYP_PULLDOWN) |
645 | #define G_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_RTT_BYP_PULLDOWN, M_BCM1480_MC_RTT_BYP_PULLDOWN) | |
4cbf2bea | 646 | |
70342287 RB |
647 | #define S_BCM1480_MC_RTT_BYP_PULLUP 6 |
648 | #define M_BCM1480_MC_RTT_BYP_PULLUP _SB_MAKEMASK(3, S_BCM1480_MC_RTT_BYP_PULLUP) | |
649 | #define V_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_RTT_BYP_PULLUP) | |
650 | #define G_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_GETVALUE(x, S_BCM1480_MC_RTT_BYP_PULLUP, M_BCM1480_MC_RTT_BYP_PULLUP) | |
4cbf2bea | 651 | |
70342287 RB |
652 | #define M_BCM1480_MC_RTT_BYPASS _SB_MAKEMASK1(8) |
653 | #define M_BCM1480_MC_RTT_COMP_MOV_AVG _SB_MAKEMASK1(9) | |
4cbf2bea AI |
654 | |
655 | #define S_BCM1480_MC_PVT_BYP_C1_PULLDOWN 10 | |
21a151d8 RB |
656 | #define M_BCM1480_MC_PVT_BYP_C1_PULLDOWN _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) |
657 | #define V_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN) | |
658 | #define G_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN, M_BCM1480_MC_PVT_BYP_C1_PULLDOWN) | |
4cbf2bea | 659 | |
70342287 RB |
660 | #define S_BCM1480_MC_PVT_BYP_C1_PULLUP 15 |
661 | #define M_BCM1480_MC_PVT_BYP_C1_PULLUP _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C1_PULLUP) | |
21a151d8 RB |
662 | #define V_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLUP) |
663 | #define G_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLUP, M_BCM1480_MC_PVT_BYP_C1_PULLUP) | |
4cbf2bea AI |
664 | |
665 | #define S_BCM1480_MC_PVT_BYP_C2_PULLDOWN 20 | |
21a151d8 RB |
666 | #define M_BCM1480_MC_PVT_BYP_C2_PULLDOWN _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) |
667 | #define V_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN) | |
668 | #define G_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN, M_BCM1480_MC_PVT_BYP_C2_PULLDOWN) | |
4cbf2bea | 669 | |
70342287 RB |
670 | #define S_BCM1480_MC_PVT_BYP_C2_PULLUP 25 |
671 | #define M_BCM1480_MC_PVT_BYP_C2_PULLUP _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C2_PULLUP) | |
21a151d8 RB |
672 | #define V_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLUP) |
673 | #define G_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLUP, M_BCM1480_MC_PVT_BYP_C2_PULLUP) | |
4cbf2bea | 674 | |
70342287 RB |
675 | #define M_BCM1480_MC_PVT_BYPASS _SB_MAKEMASK1(30) |
676 | #define M_BCM1480_MC_PVT_COMP_MOV_AVG _SB_MAKEMASK1(31) | |
4cbf2bea | 677 | |
70342287 RB |
678 | #define M_BCM1480_MC_CLK_CLASS _SB_MAKEMASK1(34) |
679 | #define M_BCM1480_MC_DATA_CLASS _SB_MAKEMASK1(35) | |
680 | #define M_BCM1480_MC_ADDR_CLASS _SB_MAKEMASK1(36) | |
4cbf2bea | 681 | |
70342287 RB |
682 | #define M_BCM1480_MC_DQ_ODT_75 _SB_MAKEMASK1(37) |
683 | #define M_BCM1480_MC_DQ_ODT_150 _SB_MAKEMASK1(38) | |
684 | #define M_BCM1480_MC_DQS_ODT_75 _SB_MAKEMASK1(39) | |
685 | #define M_BCM1480_MC_DQS_ODT_150 _SB_MAKEMASK1(40) | |
686 | #define M_BCM1480_MC_DQS_DIFF _SB_MAKEMASK1(41) | |
4cbf2bea AI |
687 | |
688 | /* | |
689 | * ECC Test Data Register (Table 95) | |
690 | */ | |
691 | ||
70342287 RB |
692 | #define S_BCM1480_MC_DATA_INVERT 0 |
693 | #define M_DATA_ECC_INVERT _SB_MAKEMASK(64, S_BCM1480_MC_ECC_INVERT) | |
4cbf2bea AI |
694 | |
695 | /* | |
696 | * ECC Test ECC Register (Table 96) | |
697 | */ | |
698 | ||
70342287 RB |
699 | #define S_BCM1480_MC_ECC_INVERT 0 |
700 | #define M_BCM1480_MC_ECC_INVERT _SB_MAKEMASK(8, S_BCM1480_MC_ECC_INVERT) | |
4cbf2bea AI |
701 | |
702 | /* | |
703 | * SDRAM Timing Register (Table 97) | |
704 | */ | |
705 | ||
70342287 RB |
706 | #define S_BCM1480_MC_tRCD 0 |
707 | #define M_BCM1480_MC_tRCD _SB_MAKEMASK(4, S_BCM1480_MC_tRCD) | |
708 | #define V_BCM1480_MC_tRCD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCD) | |
709 | #define G_BCM1480_MC_tRCD(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCD, M_BCM1480_MC_tRCD) | |
710 | #define K_BCM1480_MC_tRCD_DEFAULT 3 | |
711 | #define V_BCM1480_MC_tRCD_DEFAULT V_BCM1480_MC_tRCD(K_BCM1480_MC_tRCD_DEFAULT) | |
712 | ||
713 | #define S_BCM1480_MC_tCL 4 | |
714 | #define M_BCM1480_MC_tCL _SB_MAKEMASK(4, S_BCM1480_MC_tCL) | |
715 | #define V_BCM1480_MC_tCL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tCL) | |
716 | #define G_BCM1480_MC_tCL(x) _SB_GETVALUE(x, S_BCM1480_MC_tCL, M_BCM1480_MC_tCL) | |
717 | #define K_BCM1480_MC_tCL_DEFAULT 2 | |
718 | #define V_BCM1480_MC_tCL_DEFAULT V_BCM1480_MC_tCL(K_BCM1480_MC_tCL_DEFAULT) | |
719 | ||
720 | #define M_BCM1480_MC_tCrDh _SB_MAKEMASK1(8) | |
721 | ||
722 | #define S_BCM1480_MC_tWR 9 | |
723 | #define M_BCM1480_MC_tWR _SB_MAKEMASK(3, S_BCM1480_MC_tWR) | |
724 | #define V_BCM1480_MC_tWR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tWR) | |
725 | #define G_BCM1480_MC_tWR(x) _SB_GETVALUE(x, S_BCM1480_MC_tWR, M_BCM1480_MC_tWR) | |
726 | #define K_BCM1480_MC_tWR_DEFAULT 2 | |
727 | #define V_BCM1480_MC_tWR_DEFAULT V_BCM1480_MC_tWR(K_BCM1480_MC_tWR_DEFAULT) | |
728 | ||
729 | #define S_BCM1480_MC_tCwD 12 | |
730 | #define M_BCM1480_MC_tCwD _SB_MAKEMASK(4, S_BCM1480_MC_tCwD) | |
731 | #define V_BCM1480_MC_tCwD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tCwD) | |
732 | #define G_BCM1480_MC_tCwD(x) _SB_GETVALUE(x, S_BCM1480_MC_tCwD, M_BCM1480_MC_tCwD) | |
733 | #define K_BCM1480_MC_tCwD_DEFAULT 1 | |
734 | #define V_BCM1480_MC_tCwD_DEFAULT V_BCM1480_MC_tCwD(K_BCM1480_MC_tCwD_DEFAULT) | |
735 | ||
736 | #define S_BCM1480_MC_tRP 16 | |
737 | #define M_BCM1480_MC_tRP _SB_MAKEMASK(4, S_BCM1480_MC_tRP) | |
738 | #define V_BCM1480_MC_tRP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRP) | |
739 | #define G_BCM1480_MC_tRP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRP, M_BCM1480_MC_tRP) | |
740 | #define K_BCM1480_MC_tRP_DEFAULT 4 | |
741 | #define V_BCM1480_MC_tRP_DEFAULT V_BCM1480_MC_tRP(K_BCM1480_MC_tRP_DEFAULT) | |
742 | ||
743 | #define S_BCM1480_MC_tRRD 20 | |
744 | #define M_BCM1480_MC_tRRD _SB_MAKEMASK(4, S_BCM1480_MC_tRRD) | |
745 | #define V_BCM1480_MC_tRRD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRRD) | |
746 | #define G_BCM1480_MC_tRRD(x) _SB_GETVALUE(x, S_BCM1480_MC_tRRD, M_BCM1480_MC_tRRD) | |
747 | #define K_BCM1480_MC_tRRD_DEFAULT 2 | |
748 | #define V_BCM1480_MC_tRRD_DEFAULT V_BCM1480_MC_tRRD(K_BCM1480_MC_tRRD_DEFAULT) | |
749 | ||
750 | #define S_BCM1480_MC_tRCw 24 | |
751 | #define M_BCM1480_MC_tRCw _SB_MAKEMASK(5, S_BCM1480_MC_tRCw) | |
752 | #define V_BCM1480_MC_tRCw(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCw) | |
753 | #define G_BCM1480_MC_tRCw(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCw, M_BCM1480_MC_tRCw) | |
754 | #define K_BCM1480_MC_tRCw_DEFAULT 10 | |
755 | #define V_BCM1480_MC_tRCw_DEFAULT V_BCM1480_MC_tRCw(K_BCM1480_MC_tRCw_DEFAULT) | |
756 | ||
757 | #define S_BCM1480_MC_tRCr 32 | |
758 | #define M_BCM1480_MC_tRCr _SB_MAKEMASK(5, S_BCM1480_MC_tRCr) | |
759 | #define V_BCM1480_MC_tRCr(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCr) | |
760 | #define G_BCM1480_MC_tRCr(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCr, M_BCM1480_MC_tRCr) | |
761 | #define K_BCM1480_MC_tRCr_DEFAULT 9 | |
762 | #define V_BCM1480_MC_tRCr_DEFAULT V_BCM1480_MC_tRCr(K_BCM1480_MC_tRCr_DEFAULT) | |
4cbf2bea AI |
763 | |
764 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | |
70342287 RB |
765 | #define S_BCM1480_MC_tFAW 40 |
766 | #define M_BCM1480_MC_tFAW _SB_MAKEMASK(6, S_BCM1480_MC_tFAW) | |
767 | #define V_BCM1480_MC_tFAW(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tFAW) | |
768 | #define G_BCM1480_MC_tFAW(x) _SB_GETVALUE(x, S_BCM1480_MC_tFAW, M_BCM1480_MC_tFAW) | |
769 | #define K_BCM1480_MC_tFAW_DEFAULT 0 | |
770 | #define V_BCM1480_MC_tFAW_DEFAULT V_BCM1480_MC_tFAW(K_BCM1480_MC_tFAW_DEFAULT) | |
4cbf2bea AI |
771 | #endif |
772 | ||
70342287 RB |
773 | #define S_BCM1480_MC_tRFC 48 |
774 | #define M_BCM1480_MC_tRFC _SB_MAKEMASK(7, S_BCM1480_MC_tRFC) | |
775 | #define V_BCM1480_MC_tRFC(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRFC) | |
776 | #define G_BCM1480_MC_tRFC(x) _SB_GETVALUE(x, S_BCM1480_MC_tRFC, M_BCM1480_MC_tRFC) | |
777 | #define K_BCM1480_MC_tRFC_DEFAULT 12 | |
778 | #define V_BCM1480_MC_tRFC_DEFAULT V_BCM1480_MC_tRFC(K_BCM1480_MC_tRFC_DEFAULT) | |
779 | ||
780 | #define S_BCM1480_MC_tFIFO 56 | |
781 | #define M_BCM1480_MC_tFIFO _SB_MAKEMASK(2, S_BCM1480_MC_tFIFO) | |
782 | #define V_BCM1480_MC_tFIFO(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tFIFO) | |
783 | #define G_BCM1480_MC_tFIFO(x) _SB_GETVALUE(x, S_BCM1480_MC_tFIFO, M_BCM1480_MC_tFIFO) | |
784 | #define K_BCM1480_MC_tFIFO_DEFAULT 0 | |
785 | #define V_BCM1480_MC_tFIFO_DEFAULT V_BCM1480_MC_tFIFO(K_BCM1480_MC_tFIFO_DEFAULT) | |
786 | ||
787 | #define S_BCM1480_MC_tW2R 58 | |
788 | #define M_BCM1480_MC_tW2R _SB_MAKEMASK(2, S_BCM1480_MC_tW2R) | |
789 | #define V_BCM1480_MC_tW2R(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tW2R) | |
790 | #define G_BCM1480_MC_tW2R(x) _SB_GETVALUE(x, S_BCM1480_MC_tW2R, M_BCM1480_MC_tW2R) | |
791 | #define K_BCM1480_MC_tW2R_DEFAULT 1 | |
792 | #define V_BCM1480_MC_tW2R_DEFAULT V_BCM1480_MC_tW2R(K_BCM1480_MC_tW2R_DEFAULT) | |
793 | ||
794 | #define S_BCM1480_MC_tR2W 60 | |
795 | #define M_BCM1480_MC_tR2W _SB_MAKEMASK(2, S_BCM1480_MC_tR2W) | |
796 | #define V_BCM1480_MC_tR2W(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tR2W) | |
797 | #define G_BCM1480_MC_tR2W(x) _SB_GETVALUE(x, S_BCM1480_MC_tR2W, M_BCM1480_MC_tR2W) | |
798 | #define K_BCM1480_MC_tR2W_DEFAULT 0 | |
799 | #define V_BCM1480_MC_tR2W_DEFAULT V_BCM1480_MC_tR2W(K_BCM1480_MC_tR2W_DEFAULT) | |
4cbf2bea AI |
800 | |
801 | #define M_BCM1480_MC_tR2R _SB_MAKEMASK1(62) | |
802 | ||
70342287 RB |
803 | #define V_BCM1480_MC_TIMING_DEFAULT (M_BCM1480_MC_tR2R | \ |
804 | V_BCM1480_MC_tFIFO_DEFAULT | \ | |
805 | V_BCM1480_MC_tR2W_DEFAULT | \ | |
806 | V_BCM1480_MC_tW2R_DEFAULT | \ | |
807 | V_BCM1480_MC_tRFC_DEFAULT | \ | |
808 | V_BCM1480_MC_tRCr_DEFAULT | \ | |
809 | V_BCM1480_MC_tRCw_DEFAULT | \ | |
810 | V_BCM1480_MC_tRRD_DEFAULT | \ | |
811 | V_BCM1480_MC_tRP_DEFAULT | \ | |
812 | V_BCM1480_MC_tCwD_DEFAULT | \ | |
813 | V_BCM1480_MC_tWR_DEFAULT | \ | |
814 | M_BCM1480_MC_tCrDh | \ | |
815 | V_BCM1480_MC_tCL_DEFAULT | \ | |
816 | V_BCM1480_MC_tRCD_DEFAULT) | |
4cbf2bea AI |
817 | |
818 | /* | |
819 | * SDRAM Timing Register 2 | |
820 | */ | |
821 | ||
822 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | |
823 | ||
70342287 RB |
824 | #define S_BCM1480_MC_tAL 0 |
825 | #define M_BCM1480_MC_tAL _SB_MAKEMASK(4, S_BCM1480_MC_tAL) | |
826 | #define V_BCM1480_MC_tAL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tAL) | |
827 | #define G_BCM1480_MC_tAL(x) _SB_GETVALUE(x, S_BCM1480_MC_tAL, M_BCM1480_MC_tAL) | |
828 | #define K_BCM1480_MC_tAL_DEFAULT 0 | |
829 | #define V_BCM1480_MC_tAL_DEFAULT V_BCM1480_MC_tAL(K_BCM1480_MC_tAL_DEFAULT) | |
830 | ||
831 | #define S_BCM1480_MC_tRTP 4 | |
832 | #define M_BCM1480_MC_tRTP _SB_MAKEMASK(3, S_BCM1480_MC_tRTP) | |
833 | #define V_BCM1480_MC_tRTP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRTP) | |
834 | #define G_BCM1480_MC_tRTP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRTP, M_BCM1480_MC_tRTP) | |
835 | #define K_BCM1480_MC_tRTP_DEFAULT 2 | |
836 | #define V_BCM1480_MC_tRTP_DEFAULT V_BCM1480_MC_tRTP(K_BCM1480_MC_tRTP_DEFAULT) | |
837 | ||
838 | #define S_BCM1480_MC_tW2W 8 | |
839 | #define M_BCM1480_MC_tW2W _SB_MAKEMASK(2, S_BCM1480_MC_tW2W) | |
840 | #define V_BCM1480_MC_tW2W(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tW2W) | |
841 | #define G_BCM1480_MC_tW2W(x) _SB_GETVALUE(x, S_BCM1480_MC_tW2W, M_BCM1480_MC_tW2W) | |
842 | #define K_BCM1480_MC_tW2W_DEFAULT 0 | |
843 | #define V_BCM1480_MC_tW2W_DEFAULT V_BCM1480_MC_tW2W(K_BCM1480_MC_tW2W_DEFAULT) | |
844 | ||
845 | #define S_BCM1480_MC_tRAP 12 | |
846 | #define M_BCM1480_MC_tRAP _SB_MAKEMASK(4, S_BCM1480_MC_tRAP) | |
847 | #define V_BCM1480_MC_tRAP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRAP) | |
848 | #define G_BCM1480_MC_tRAP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRAP, M_BCM1480_MC_tRAP) | |
849 | #define K_BCM1480_MC_tRAP_DEFAULT 0 | |
850 | #define V_BCM1480_MC_tRAP_DEFAULT V_BCM1480_MC_tRAP(K_BCM1480_MC_tRAP_DEFAULT) | |
4cbf2bea AI |
851 | |
852 | #endif | |
853 | ||
854 | ||
855 | ||
856 | /* | |
857 | * Global Registers: single instances per BCM1480 | |
858 | */ | |
859 | ||
860 | /* | |
861 | * Global Configuration Register (Table 99) | |
862 | */ | |
863 | ||
70342287 RB |
864 | #define S_BCM1480_MC_BLK_SET_MARK 8 |
865 | #define M_BCM1480_MC_BLK_SET_MARK _SB_MAKEMASK(4, S_BCM1480_MC_BLK_SET_MARK) | |
866 | #define V_BCM1480_MC_BLK_SET_MARK(x) _SB_MAKEVALUE(x, S_BCM1480_MC_BLK_SET_MARK) | |
867 | #define G_BCM1480_MC_BLK_SET_MARK(x) _SB_GETVALUE(x, S_BCM1480_MC_BLK_SET_MARK, M_BCM1480_MC_BLK_SET_MARK) | |
4cbf2bea | 868 | |
70342287 RB |
869 | #define S_BCM1480_MC_BLK_CLR_MARK 12 |
870 | #define M_BCM1480_MC_BLK_CLR_MARK _SB_MAKEMASK(4, S_BCM1480_MC_BLK_CLR_MARK) | |
871 | #define V_BCM1480_MC_BLK_CLR_MARK(x) _SB_MAKEVALUE(x, S_BCM1480_MC_BLK_CLR_MARK) | |
872 | #define G_BCM1480_MC_BLK_CLR_MARK(x) _SB_GETVALUE(x, S_BCM1480_MC_BLK_CLR_MARK, M_BCM1480_MC_BLK_CLR_MARK) | |
4cbf2bea | 873 | |
70342287 | 874 | #define M_BCM1480_MC_PKT_PRIORITY _SB_MAKEMASK1(16) |
4cbf2bea | 875 | |
70342287 RB |
876 | #define S_BCM1480_MC_MAX_AGE 20 |
877 | #define M_BCM1480_MC_MAX_AGE _SB_MAKEMASK(4, S_BCM1480_MC_MAX_AGE) | |
878 | #define V_BCM1480_MC_MAX_AGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_MAX_AGE) | |
879 | #define G_BCM1480_MC_MAX_AGE(x) _SB_GETVALUE(x, S_BCM1480_MC_MAX_AGE, M_BCM1480_MC_MAX_AGE) | |
4cbf2bea | 880 | |
70342287 RB |
881 | #define M_BCM1480_MC_BERR_DISABLE _SB_MAKEMASK1(29) |
882 | #define M_BCM1480_MC_FORCE_SEQ _SB_MAKEMASK1(30) | |
883 | #define M_BCM1480_MC_VGEN _SB_MAKEMASK1(32) | |
4cbf2bea | 884 | |
70342287 RB |
885 | #define S_BCM1480_MC_SLEW 33 |
886 | #define M_BCM1480_MC_SLEW _SB_MAKEMASK(2, S_BCM1480_MC_SLEW) | |
887 | #define V_BCM1480_MC_SLEW(x) _SB_MAKEVALUE(x, S_BCM1480_MC_SLEW) | |
888 | #define G_BCM1480_MC_SLEW(x) _SB_GETVALUE(x, S_BCM1480_MC_SLEW, M_BCM1480_MC_SLEW) | |
4cbf2bea | 889 | |
70342287 | 890 | #define M_BCM1480_MC_SSTL_VOLTAGE _SB_MAKEMASK1(35) |
4cbf2bea AI |
891 | |
892 | /* | |
893 | * Global Channel Interleave Register (Table 100) | |
894 | */ | |
895 | ||
70342287 RB |
896 | #define S_BCM1480_MC_INTLV0 0 |
897 | #define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0) | |
898 | #define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0) | |
899 | #define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0) | |
900 | ||
901 | #define S_BCM1480_MC_INTLV1 8 | |
902 | #define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1) | |
903 | #define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1) | |
904 | #define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1) | |
905 | ||
906 | #define S_BCM1480_MC_INTLV_MODE 16 | |
907 | #define M_BCM1480_MC_INTLV_MODE _SB_MAKEMASK(3, S_BCM1480_MC_INTLV_MODE) | |
908 | #define V_BCM1480_MC_INTLV_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV_MODE) | |
909 | #define G_BCM1480_MC_INTLV_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV_MODE, M_BCM1480_MC_INTLV_MODE) | |
910 | ||
911 | #define K_BCM1480_MC_INTLV_MODE_NONE 0x0 | |
912 | #define K_BCM1480_MC_INTLV_MODE_01 0x1 | |
913 | #define K_BCM1480_MC_INTLV_MODE_23 0x2 | |
914 | #define K_BCM1480_MC_INTLV_MODE_01_23 0x3 | |
915 | #define K_BCM1480_MC_INTLV_MODE_0123 0x4 | |
916 | ||
917 | #define V_BCM1480_MC_INTLV_MODE_NONE V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_NONE) | |
918 | #define V_BCM1480_MC_INTLV_MODE_01 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01) | |
919 | #define V_BCM1480_MC_INTLV_MODE_23 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_23) | |
920 | #define V_BCM1480_MC_INTLV_MODE_01_23 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01_23) | |
921 | #define V_BCM1480_MC_INTLV_MODE_0123 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_0123) | |
4cbf2bea AI |
922 | |
923 | /* | |
924 | * ECC Status Register | |
925 | */ | |
926 | ||
70342287 RB |
927 | #define S_BCM1480_MC_ECC_ERR_ADDR 0 |
928 | #define M_BCM1480_MC_ECC_ERR_ADDR _SB_MAKEMASK(37, S_BCM1480_MC_ECC_ERR_ADDR) | |
929 | #define V_BCM1480_MC_ECC_ERR_ADDR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_ERR_ADDR) | |
930 | #define G_BCM1480_MC_ECC_ERR_ADDR(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_ERR_ADDR, M_BCM1480_MC_ECC_ERR_ADDR) | |
4cbf2bea AI |
931 | |
932 | #if SIBYTE_HDR_FEATURE(1480, PASS2) | |
70342287 | 933 | #define M_BCM1480_MC_ECC_ERR_RMW _SB_MAKEMASK1(60) |
4cbf2bea AI |
934 | #endif |
935 | ||
70342287 RB |
936 | #define M_BCM1480_MC_ECC_MULT_ERR_DET _SB_MAKEMASK1(61) |
937 | #define M_BCM1480_MC_ECC_UERR_DET _SB_MAKEMASK1(62) | |
938 | #define M_BCM1480_MC_ECC_CERR_DET _SB_MAKEMASK1(63) | |
4cbf2bea AI |
939 | |
940 | /* | |
941 | * Global ECC Address Register (Table 102) | |
942 | */ | |
943 | ||
70342287 RB |
944 | #define S_BCM1480_MC_ECC_CORR_ADDR 0 |
945 | #define M_BCM1480_MC_ECC_CORR_ADDR _SB_MAKEMASK(37, S_BCM1480_MC_ECC_CORR_ADDR) | |
946 | #define V_BCM1480_MC_ECC_CORR_ADDR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_CORR_ADDR) | |
947 | #define G_BCM1480_MC_ECC_CORR_ADDR(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_CORR_ADDR, M_BCM1480_MC_ECC_CORR_ADDR) | |
4cbf2bea AI |
948 | |
949 | /* | |
950 | * Global ECC Correction Register (Table 103) | |
951 | */ | |
952 | ||
70342287 RB |
953 | #define S_BCM1480_MC_ECC_CORRECT 0 |
954 | #define M_BCM1480_MC_ECC_CORRECT _SB_MAKEMASK(64, S_BCM1480_MC_ECC_CORRECT) | |
955 | #define V_BCM1480_MC_ECC_CORRECT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_CORRECT) | |
956 | #define G_BCM1480_MC_ECC_CORRECT(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_CORRECT, M_BCM1480_MC_ECC_CORRECT) | |
4cbf2bea AI |
957 | |
958 | /* | |
959 | * Global ECC Performance Counters Control Register (Table 104) | |
960 | */ | |
961 | ||
70342287 RB |
962 | #define S_BCM1480_MC_CHANNEL_SELECT 0 |
963 | #define M_BCM1480_MC_CHANNEL_SELECT _SB_MAKEMASK(4, S_BCM1480_MC_CHANNEL_SELECT) | |
964 | #define V_BCM1480_MC_CHANNEL_SELECT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CHANNEL_SELECT) | |
965 | #define G_BCM1480_MC_CHANNEL_SELECT(x) _SB_GETVALUE(x, S_BCM1480_MC_CHANNEL_SELECT, M_BCM1480_MC_CHANNEL_SELECT) | |
966 | #define K_BCM1480_MC_CHANNEL_SELECT_0 0x1 | |
967 | #define K_BCM1480_MC_CHANNEL_SELECT_1 0x2 | |
968 | #define K_BCM1480_MC_CHANNEL_SELECT_2 0x4 | |
969 | #define K_BCM1480_MC_CHANNEL_SELECT_3 0x8 | |
4cbf2bea AI |
970 | |
971 | #endif /* _BCM1480_MC_H */ |