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1da177e4 LT |
1 | /* ********************************************************************* |
2 | * SB1250 Board Support Package | |
42a3b4f2 | 3 | * |
1da177e4 | 4 | * Interrupt Mapper definitions File: sb1250_int.h |
42a3b4f2 | 5 | * |
1da177e4 LT |
6 | * This module contains constants for manipulating the SB1250's |
7 | * interrupt mapper and definitions for the interrupt sources. | |
42a3b4f2 | 8 | * |
1da177e4 | 9 | * SB1250 specification level: User's manual 1/02/02 |
42a3b4f2 | 10 | * |
42a3b4f2 | 11 | ********************************************************************* |
1da177e4 | 12 | * |
21a151d8 | 13 | * Copyright 2000, 2001, 2002, 2003 |
1da177e4 | 14 | * Broadcom Corporation. All rights reserved. |
42a3b4f2 RB |
15 | * |
16 | * This program is free software; you can redistribute it and/or | |
17 | * modify it under the terms of the GNU General Public License as | |
18 | * published by the Free Software Foundation; either version 2 of | |
1da177e4 LT |
19 | * the License, or (at your option) any later version. |
20 | * | |
21 | * This program is distributed in the hope that it will be useful, | |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | * GNU General Public License for more details. | |
25 | * | |
26 | * You should have received a copy of the GNU General Public License | |
27 | * along with this program; if not, write to the Free Software | |
42a3b4f2 | 28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
1da177e4 LT |
29 | * MA 02111-1307 USA |
30 | ********************************************************************* */ | |
31 | ||
32 | ||
33 | #ifndef _SB1250_INT_H | |
34 | #define _SB1250_INT_H | |
35 | ||
a1ce3928 | 36 | #include <asm/sibyte/sb1250_defs.h> |
1da177e4 LT |
37 | |
38 | /* ********************************************************************* | |
39 | * Interrupt Mapper Constants | |
40 | ********************************************************************* */ | |
41 | ||
42 | /* | |
43 | * Interrupt sources (Table 4-8, UM 0.2) | |
42a3b4f2 | 44 | * |
1da177e4 LT |
45 | * First, the interrupt numbers. |
46 | */ | |
47 | ||
70342287 RB |
48 | #define K_INT_SOURCES 64 |
49 | ||
50 | #define K_INT_WATCHDOG_TIMER_0 0 | |
51 | #define K_INT_WATCHDOG_TIMER_1 1 | |
52 | #define K_INT_TIMER_0 2 | |
53 | #define K_INT_TIMER_1 3 | |
54 | #define K_INT_TIMER_2 4 | |
55 | #define K_INT_TIMER_3 5 | |
56 | #define K_INT_SMB_0 6 | |
57 | #define K_INT_SMB_1 7 | |
58 | #define K_INT_UART_0 8 | |
59 | #define K_INT_UART_1 9 | |
60 | #define K_INT_SER_0 10 | |
61 | #define K_INT_SER_1 11 | |
62 | #define K_INT_PCMCIA 12 | |
63 | #define K_INT_ADDR_TRAP 13 | |
64 | #define K_INT_PERF_CNT 14 | |
65 | #define K_INT_TRACE_FREEZE 15 | |
66 | #define K_INT_BAD_ECC 16 | |
67 | #define K_INT_COR_ECC 17 | |
68 | #define K_INT_IO_BUS 18 | |
69 | #define K_INT_MAC_0 19 | |
70 | #define K_INT_MAC_1 20 | |
71 | #define K_INT_MAC_2 21 | |
72 | #define K_INT_DM_CH_0 22 | |
73 | #define K_INT_DM_CH_1 23 | |
74 | #define K_INT_DM_CH_2 24 | |
75 | #define K_INT_DM_CH_3 25 | |
76 | #define K_INT_MBOX_0 26 | |
77 | #define K_INT_MBOX_1 27 | |
78 | #define K_INT_MBOX_2 28 | |
79 | #define K_INT_MBOX_3 29 | |
1da177e4 LT |
80 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) |
81 | #define K_INT_CYCLE_CP0_INT 30 | |
82 | #define K_INT_CYCLE_CP1_INT 31 | |
83 | #endif /* 1250 PASS2 || 112x PASS1 */ | |
70342287 RB |
84 | #define K_INT_GPIO_0 32 |
85 | #define K_INT_GPIO_1 33 | |
86 | #define K_INT_GPIO_2 34 | |
87 | #define K_INT_GPIO_3 35 | |
88 | #define K_INT_GPIO_4 36 | |
89 | #define K_INT_GPIO_5 37 | |
90 | #define K_INT_GPIO_6 38 | |
91 | #define K_INT_GPIO_7 39 | |
92 | #define K_INT_GPIO_8 40 | |
93 | #define K_INT_GPIO_9 41 | |
94 | #define K_INT_GPIO_10 42 | |
95 | #define K_INT_GPIO_11 43 | |
96 | #define K_INT_GPIO_12 44 | |
97 | #define K_INT_GPIO_13 45 | |
98 | #define K_INT_GPIO_14 46 | |
99 | #define K_INT_GPIO_15 47 | |
100 | #define K_INT_LDT_FATAL 48 | |
101 | #define K_INT_LDT_NONFATAL 49 | |
102 | #define K_INT_LDT_SMI 50 | |
103 | #define K_INT_LDT_NMI 51 | |
104 | #define K_INT_LDT_INIT 52 | |
105 | #define K_INT_LDT_STARTUP 53 | |
106 | #define K_INT_LDT_EXT 54 | |
107 | #define K_INT_PCI_ERROR 55 | |
108 | #define K_INT_PCI_INTA 56 | |
109 | #define K_INT_PCI_INTB 57 | |
110 | #define K_INT_PCI_INTC 58 | |
111 | #define K_INT_PCI_INTD 59 | |
112 | #define K_INT_SPARE_2 60 | |
1da177e4 LT |
113 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) |
114 | #define K_INT_MAC_0_CH1 61 | |
115 | #define K_INT_MAC_1_CH1 62 | |
116 | #define K_INT_MAC_2_CH1 63 | |
117 | #endif /* 1250 PASS2 || 112x PASS1 */ | |
118 | ||
119 | /* | |
120 | * Mask values for each interrupt | |
121 | */ | |
122 | ||
70342287 RB |
123 | #define M_INT_WATCHDOG_TIMER_0 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_0) |
124 | #define M_INT_WATCHDOG_TIMER_1 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_1) | |
125 | #define M_INT_TIMER_0 _SB_MAKEMASK1(K_INT_TIMER_0) | |
126 | #define M_INT_TIMER_1 _SB_MAKEMASK1(K_INT_TIMER_1) | |
127 | #define M_INT_TIMER_2 _SB_MAKEMASK1(K_INT_TIMER_2) | |
128 | #define M_INT_TIMER_3 _SB_MAKEMASK1(K_INT_TIMER_3) | |
129 | #define M_INT_SMB_0 _SB_MAKEMASK1(K_INT_SMB_0) | |
130 | #define M_INT_SMB_1 _SB_MAKEMASK1(K_INT_SMB_1) | |
131 | #define M_INT_UART_0 _SB_MAKEMASK1(K_INT_UART_0) | |
132 | #define M_INT_UART_1 _SB_MAKEMASK1(K_INT_UART_1) | |
133 | #define M_INT_SER_0 _SB_MAKEMASK1(K_INT_SER_0) | |
134 | #define M_INT_SER_1 _SB_MAKEMASK1(K_INT_SER_1) | |
135 | #define M_INT_PCMCIA _SB_MAKEMASK1(K_INT_PCMCIA) | |
136 | #define M_INT_ADDR_TRAP _SB_MAKEMASK1(K_INT_ADDR_TRAP) | |
137 | #define M_INT_PERF_CNT _SB_MAKEMASK1(K_INT_PERF_CNT) | |
138 | #define M_INT_TRACE_FREEZE _SB_MAKEMASK1(K_INT_TRACE_FREEZE) | |
139 | #define M_INT_BAD_ECC _SB_MAKEMASK1(K_INT_BAD_ECC) | |
140 | #define M_INT_COR_ECC _SB_MAKEMASK1(K_INT_COR_ECC) | |
141 | #define M_INT_IO_BUS _SB_MAKEMASK1(K_INT_IO_BUS) | |
142 | #define M_INT_MAC_0 _SB_MAKEMASK1(K_INT_MAC_0) | |
143 | #define M_INT_MAC_1 _SB_MAKEMASK1(K_INT_MAC_1) | |
144 | #define M_INT_MAC_2 _SB_MAKEMASK1(K_INT_MAC_2) | |
145 | #define M_INT_DM_CH_0 _SB_MAKEMASK1(K_INT_DM_CH_0) | |
146 | #define M_INT_DM_CH_1 _SB_MAKEMASK1(K_INT_DM_CH_1) | |
147 | #define M_INT_DM_CH_2 _SB_MAKEMASK1(K_INT_DM_CH_2) | |
148 | #define M_INT_DM_CH_3 _SB_MAKEMASK1(K_INT_DM_CH_3) | |
149 | #define M_INT_MBOX_0 _SB_MAKEMASK1(K_INT_MBOX_0) | |
150 | #define M_INT_MBOX_1 _SB_MAKEMASK1(K_INT_MBOX_1) | |
151 | #define M_INT_MBOX_2 _SB_MAKEMASK1(K_INT_MBOX_2) | |
152 | #define M_INT_MBOX_3 _SB_MAKEMASK1(K_INT_MBOX_3) | |
153 | #define M_INT_MBOX_ALL _SB_MAKEMASK(4, K_INT_MBOX_0) | |
1da177e4 LT |
154 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) |
155 | #define M_INT_CYCLE_CP0_INT _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT) | |
156 | #define M_INT_CYCLE_CP1_INT _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT) | |
157 | #endif /* 1250 PASS2 || 112x PASS1 */ | |
70342287 RB |
158 | #define M_INT_GPIO_0 _SB_MAKEMASK1(K_INT_GPIO_0) |
159 | #define M_INT_GPIO_1 _SB_MAKEMASK1(K_INT_GPIO_1) | |
160 | #define M_INT_GPIO_2 _SB_MAKEMASK1(K_INT_GPIO_2) | |
161 | #define M_INT_GPIO_3 _SB_MAKEMASK1(K_INT_GPIO_3) | |
162 | #define M_INT_GPIO_4 _SB_MAKEMASK1(K_INT_GPIO_4) | |
163 | #define M_INT_GPIO_5 _SB_MAKEMASK1(K_INT_GPIO_5) | |
164 | #define M_INT_GPIO_6 _SB_MAKEMASK1(K_INT_GPIO_6) | |
165 | #define M_INT_GPIO_7 _SB_MAKEMASK1(K_INT_GPIO_7) | |
166 | #define M_INT_GPIO_8 _SB_MAKEMASK1(K_INT_GPIO_8) | |
167 | #define M_INT_GPIO_9 _SB_MAKEMASK1(K_INT_GPIO_9) | |
168 | #define M_INT_GPIO_10 _SB_MAKEMASK1(K_INT_GPIO_10) | |
169 | #define M_INT_GPIO_11 _SB_MAKEMASK1(K_INT_GPIO_11) | |
170 | #define M_INT_GPIO_12 _SB_MAKEMASK1(K_INT_GPIO_12) | |
171 | #define M_INT_GPIO_13 _SB_MAKEMASK1(K_INT_GPIO_13) | |
172 | #define M_INT_GPIO_14 _SB_MAKEMASK1(K_INT_GPIO_14) | |
173 | #define M_INT_GPIO_15 _SB_MAKEMASK1(K_INT_GPIO_15) | |
174 | #define M_INT_LDT_FATAL _SB_MAKEMASK1(K_INT_LDT_FATAL) | |
175 | #define M_INT_LDT_NONFATAL _SB_MAKEMASK1(K_INT_LDT_NONFATAL) | |
176 | #define M_INT_LDT_SMI _SB_MAKEMASK1(K_INT_LDT_SMI) | |
177 | #define M_INT_LDT_NMI _SB_MAKEMASK1(K_INT_LDT_NMI) | |
178 | #define M_INT_LDT_INIT _SB_MAKEMASK1(K_INT_LDT_INIT) | |
179 | #define M_INT_LDT_STARTUP _SB_MAKEMASK1(K_INT_LDT_STARTUP) | |
180 | #define M_INT_LDT_EXT _SB_MAKEMASK1(K_INT_LDT_EXT) | |
181 | #define M_INT_PCI_ERROR _SB_MAKEMASK1(K_INT_PCI_ERROR) | |
182 | #define M_INT_PCI_INTA _SB_MAKEMASK1(K_INT_PCI_INTA) | |
183 | #define M_INT_PCI_INTB _SB_MAKEMASK1(K_INT_PCI_INTB) | |
184 | #define M_INT_PCI_INTC _SB_MAKEMASK1(K_INT_PCI_INTC) | |
185 | #define M_INT_PCI_INTD _SB_MAKEMASK1(K_INT_PCI_INTD) | |
186 | #define M_INT_SPARE_2 _SB_MAKEMASK1(K_INT_SPARE_2) | |
1da177e4 LT |
187 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) |
188 | #define M_INT_MAC_0_CH1 _SB_MAKEMASK1(K_INT_MAC_0_CH1) | |
189 | #define M_INT_MAC_1_CH1 _SB_MAKEMASK1(K_INT_MAC_1_CH1) | |
190 | #define M_INT_MAC_2_CH1 _SB_MAKEMASK1(K_INT_MAC_2_CH1) | |
191 | #endif /* 1250 PASS2 || 112x PASS1 */ | |
192 | ||
193 | /* | |
194 | * Interrupt mappings | |
195 | */ | |
196 | ||
197 | #define K_INT_MAP_I0 0 /* interrupt pins on processor */ | |
198 | #define K_INT_MAP_I1 1 | |
199 | #define K_INT_MAP_I2 2 | |
200 | #define K_INT_MAP_I3 3 | |
201 | #define K_INT_MAP_I4 4 | |
202 | #define K_INT_MAP_I5 5 | |
203 | #define K_INT_MAP_NMI 6 /* nonmaskable */ | |
204 | #define K_INT_MAP_DINT 7 /* debug interrupt */ | |
205 | ||
206 | /* | |
207 | * LDT Interrupt Set Register (table 4-5) | |
208 | */ | |
209 | ||
210 | #define S_INT_LDT_INTMSG 0 | |
70342287 RB |
211 | #define M_INT_LDT_INTMSG _SB_MAKEMASK(3, S_INT_LDT_INTMSG) |
212 | #define V_INT_LDT_INTMSG(x) _SB_MAKEVALUE(x, S_INT_LDT_INTMSG) | |
213 | #define G_INT_LDT_INTMSG(x) _SB_GETVALUE(x, S_INT_LDT_INTMSG, M_INT_LDT_INTMSG) | |
1da177e4 LT |
214 | |
215 | #define K_INT_LDT_INTMSG_FIXED 0 | |
216 | #define K_INT_LDT_INTMSG_ARBITRATED 1 | |
217 | #define K_INT_LDT_INTMSG_SMI 2 | |
218 | #define K_INT_LDT_INTMSG_NMI 3 | |
219 | #define K_INT_LDT_INTMSG_INIT 4 | |
220 | #define K_INT_LDT_INTMSG_STARTUP 5 | |
221 | #define K_INT_LDT_INTMSG_EXTINT 6 | |
222 | #define K_INT_LDT_INTMSG_RESERVED 7 | |
223 | ||
70342287 RB |
224 | #define M_INT_LDT_EDGETRIGGER 0 |
225 | #define M_INT_LDT_LEVELTRIGGER _SB_MAKEMASK1(3) | |
1da177e4 | 226 | |
70342287 RB |
227 | #define M_INT_LDT_PHYSICALDEST 0 |
228 | #define M_INT_LDT_LOGICALDEST _SB_MAKEMASK1(4) | |
1da177e4 | 229 | |
70342287 RB |
230 | #define S_INT_LDT_INTDEST 5 |
231 | #define M_INT_LDT_INTDEST _SB_MAKEMASK(10, S_INT_LDT_INTDEST) | |
232 | #define V_INT_LDT_INTDEST(x) _SB_MAKEVALUE(x, S_INT_LDT_INTDEST) | |
233 | #define G_INT_LDT_INTDEST(x) _SB_GETVALUE(x, S_INT_LDT_INTDEST, M_INT_LDT_INTDEST) | |
1da177e4 | 234 | |
70342287 RB |
235 | #define S_INT_LDT_VECTOR 13 |
236 | #define M_INT_LDT_VECTOR _SB_MAKEMASK(8, S_INT_LDT_VECTOR) | |
237 | #define V_INT_LDT_VECTOR(x) _SB_MAKEVALUE(x, S_INT_LDT_VECTOR) | |
238 | #define G_INT_LDT_VECTOR(x) _SB_GETVALUE(x, S_INT_LDT_VECTOR, M_INT_LDT_VECTOR) | |
1da177e4 LT |
239 | |
240 | /* | |
241 | * Vector format (Table 4-6) | |
242 | */ | |
243 | ||
244 | #define M_LDTVECT_RAISEINT 0x00 | |
70342287 | 245 | #define M_LDTVECT_RAISEMBOX 0x40 |
1da177e4 LT |
246 | |
247 | ||
4cbf2bea | 248 | #endif /* 1250/112x */ |