[mirror_ubuntu-focal-kernel.git] / arch / mips / include / asm / sibyte / sb1250_int.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*  *********************************************************************
    *  SB1250 Board Support Package
    *
    *  Interrupt Mapper definitions		File: sb1250_int.h
    *
    *  This module contains constants for manipulating the SB1250's
    *  interrupt mapper and definitions for the interrupt sources.
    *
    *  SB1250 specification level:  User's manual 1/02/02
    *
    *********************************************************************
    *
    *  Copyright 2000, 2001, 2002, 2003
    *  Broadcom Corporation. All rights reserved.
    *
    ********************************************************************* */


#ifndef _SB1250_INT_H
#define _SB1250_INT_H

#include <asm/sibyte/sb1250_defs.h>

/*  *********************************************************************
    *  Interrupt Mapper Constants
    ********************************************************************* */

/*
 * Interrupt sources (Table 4-8, UM 0.2)
 *
 * First, the interrupt numbers.
 */

#define K_INT_SOURCES		    64

#define K_INT_WATCHDOG_TIMER_0	    0
#define K_INT_WATCHDOG_TIMER_1	    1
#define K_INT_TIMER_0		    2
#define K_INT_TIMER_1		    3
#define K_INT_TIMER_2		    4
#define K_INT_TIMER_3		    5
#define K_INT_SMB_0		    6
#define K_INT_SMB_1		    7
#define K_INT_UART_0		    8
#define K_INT_UART_1		    9
#define K_INT_SER_0		    10
#define K_INT_SER_1		    11
#define K_INT_PCMCIA		    12
#define K_INT_ADDR_TRAP		    13
#define K_INT_PERF_CNT		    14
#define K_INT_TRACE_FREEZE	    15
#define K_INT_BAD_ECC		    16
#define K_INT_COR_ECC		    17
#define K_INT_IO_BUS		    18
#define K_INT_MAC_0		    19
#define K_INT_MAC_1		    20
#define K_INT_MAC_2		    21
#define K_INT_DM_CH_0		    22
#define K_INT_DM_CH_1		    23
#define K_INT_DM_CH_2		    24
#define K_INT_DM_CH_3		    25
#define K_INT_MBOX_0		    26
#define K_INT_MBOX_1		    27
#define K_INT_MBOX_2		    28
#define K_INT_MBOX_3		    29
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define K_INT_CYCLE_CP0_INT	    30
#define K_INT_CYCLE_CP1_INT	    31
#endif /* 1250 PASS2 || 112x PASS1 */
#define K_INT_GPIO_0		    32
#define K_INT_GPIO_1		    33
#define K_INT_GPIO_2		    34
#define K_INT_GPIO_3		    35
#define K_INT_GPIO_4		    36
#define K_INT_GPIO_5		    37
#define K_INT_GPIO_6		    38
#define K_INT_GPIO_7		    39
#define K_INT_GPIO_8		    40
#define K_INT_GPIO_9		    41
#define K_INT_GPIO_10		    42
#define K_INT_GPIO_11		    43
#define K_INT_GPIO_12		    44
#define K_INT_GPIO_13		    45
#define K_INT_GPIO_14		    46
#define K_INT_GPIO_15		    47
#define K_INT_LDT_FATAL		    48
#define K_INT_LDT_NONFATAL	    49
#define K_INT_LDT_SMI		    50
#define K_INT_LDT_NMI		    51
#define K_INT_LDT_INIT		    52
#define K_INT_LDT_STARTUP	    53
#define K_INT_LDT_EXT		    54
#define K_INT_PCI_ERROR		    55
#define K_INT_PCI_INTA		    56
#define K_INT_PCI_INTB		    57
#define K_INT_PCI_INTC		    58
#define K_INT_PCI_INTD		    59
#define K_INT_SPARE_2		    60
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define K_INT_MAC_0_CH1		    61
#define K_INT_MAC_1_CH1		    62
#define K_INT_MAC_2_CH1		    63
#endif /* 1250 PASS2 || 112x PASS1 */

/*
 * Mask values for each interrupt
 */

#define M_INT_WATCHDOG_TIMER_0	    _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_0)
#define M_INT_WATCHDOG_TIMER_1	    _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_1)
#define M_INT_TIMER_0		    _SB_MAKEMASK1(K_INT_TIMER_0)
#define M_INT_TIMER_1		    _SB_MAKEMASK1(K_INT_TIMER_1)
#define M_INT_TIMER_2		    _SB_MAKEMASK1(K_INT_TIMER_2)
#define M_INT_TIMER_3		    _SB_MAKEMASK1(K_INT_TIMER_3)
#define M_INT_SMB_0		    _SB_MAKEMASK1(K_INT_SMB_0)
#define M_INT_SMB_1		    _SB_MAKEMASK1(K_INT_SMB_1)
#define M_INT_UART_0		    _SB_MAKEMASK1(K_INT_UART_0)
#define M_INT_UART_1		    _SB_MAKEMASK1(K_INT_UART_1)
#define M_INT_SER_0		    _SB_MAKEMASK1(K_INT_SER_0)
#define M_INT_SER_1		    _SB_MAKEMASK1(K_INT_SER_1)
#define M_INT_PCMCIA		    _SB_MAKEMASK1(K_INT_PCMCIA)
#define M_INT_ADDR_TRAP		    _SB_MAKEMASK1(K_INT_ADDR_TRAP)
#define M_INT_PERF_CNT		    _SB_MAKEMASK1(K_INT_PERF_CNT)
#define M_INT_TRACE_FREEZE	    _SB_MAKEMASK1(K_INT_TRACE_FREEZE)
#define M_INT_BAD_ECC		    _SB_MAKEMASK1(K_INT_BAD_ECC)
#define M_INT_COR_ECC		    _SB_MAKEMASK1(K_INT_COR_ECC)
#define M_INT_IO_BUS		    _SB_MAKEMASK1(K_INT_IO_BUS)
#define M_INT_MAC_0		    _SB_MAKEMASK1(K_INT_MAC_0)
#define M_INT_MAC_1		    _SB_MAKEMASK1(K_INT_MAC_1)
#define M_INT_MAC_2		    _SB_MAKEMASK1(K_INT_MAC_2)
#define M_INT_DM_CH_0		    _SB_MAKEMASK1(K_INT_DM_CH_0)
#define M_INT_DM_CH_1		    _SB_MAKEMASK1(K_INT_DM_CH_1)
#define M_INT_DM_CH_2		    _SB_MAKEMASK1(K_INT_DM_CH_2)
#define M_INT_DM_CH_3		    _SB_MAKEMASK1(K_INT_DM_CH_3)
#define M_INT_MBOX_0		    _SB_MAKEMASK1(K_INT_MBOX_0)
#define M_INT_MBOX_1		    _SB_MAKEMASK1(K_INT_MBOX_1)
#define M_INT_MBOX_2		    _SB_MAKEMASK1(K_INT_MBOX_2)
#define M_INT_MBOX_3		    _SB_MAKEMASK1(K_INT_MBOX_3)
#define M_INT_MBOX_ALL		    _SB_MAKEMASK(4, K_INT_MBOX_0)
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_INT_CYCLE_CP0_INT	    _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT)
#define M_INT_CYCLE_CP1_INT	    _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT)
#endif /* 1250 PASS2 || 112x PASS1 */
#define M_INT_GPIO_0		    _SB_MAKEMASK1(K_INT_GPIO_0)
#define M_INT_GPIO_1		    _SB_MAKEMASK1(K_INT_GPIO_1)
#define M_INT_GPIO_2		    _SB_MAKEMASK1(K_INT_GPIO_2)
#define M_INT_GPIO_3		    _SB_MAKEMASK1(K_INT_GPIO_3)
#define M_INT_GPIO_4		    _SB_MAKEMASK1(K_INT_GPIO_4)
#define M_INT_GPIO_5		    _SB_MAKEMASK1(K_INT_GPIO_5)
#define M_INT_GPIO_6		    _SB_MAKEMASK1(K_INT_GPIO_6)
#define M_INT_GPIO_7		    _SB_MAKEMASK1(K_INT_GPIO_7)
#define M_INT_GPIO_8		    _SB_MAKEMASK1(K_INT_GPIO_8)
#define M_INT_GPIO_9		    _SB_MAKEMASK1(K_INT_GPIO_9)
#define M_INT_GPIO_10		    _SB_MAKEMASK1(K_INT_GPIO_10)
#define M_INT_GPIO_11		    _SB_MAKEMASK1(K_INT_GPIO_11)
#define M_INT_GPIO_12		    _SB_MAKEMASK1(K_INT_GPIO_12)
#define M_INT_GPIO_13		    _SB_MAKEMASK1(K_INT_GPIO_13)
#define M_INT_GPIO_14		    _SB_MAKEMASK1(K_INT_GPIO_14)
#define M_INT_GPIO_15		    _SB_MAKEMASK1(K_INT_GPIO_15)
#define M_INT_LDT_FATAL		    _SB_MAKEMASK1(K_INT_LDT_FATAL)
#define M_INT_LDT_NONFATAL	    _SB_MAKEMASK1(K_INT_LDT_NONFATAL)
#define M_INT_LDT_SMI		    _SB_MAKEMASK1(K_INT_LDT_SMI)
#define M_INT_LDT_NMI		    _SB_MAKEMASK1(K_INT_LDT_NMI)
#define M_INT_LDT_INIT		    _SB_MAKEMASK1(K_INT_LDT_INIT)
#define M_INT_LDT_STARTUP	    _SB_MAKEMASK1(K_INT_LDT_STARTUP)
#define M_INT_LDT_EXT		    _SB_MAKEMASK1(K_INT_LDT_EXT)
#define M_INT_PCI_ERROR		    _SB_MAKEMASK1(K_INT_PCI_ERROR)
#define M_INT_PCI_INTA		    _SB_MAKEMASK1(K_INT_PCI_INTA)
#define M_INT_PCI_INTB		    _SB_MAKEMASK1(K_INT_PCI_INTB)
#define M_INT_PCI_INTC		    _SB_MAKEMASK1(K_INT_PCI_INTC)
#define M_INT_PCI_INTD		    _SB_MAKEMASK1(K_INT_PCI_INTD)
#define M_INT_SPARE_2		    _SB_MAKEMASK1(K_INT_SPARE_2)
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_INT_MAC_0_CH1		    _SB_MAKEMASK1(K_INT_MAC_0_CH1)
#define M_INT_MAC_1_CH1		    _SB_MAKEMASK1(K_INT_MAC_1_CH1)
#define M_INT_MAC_2_CH1		    _SB_MAKEMASK1(K_INT_MAC_2_CH1)
#endif /* 1250 PASS2 || 112x PASS1 */

/*
 * Interrupt mappings
 */

#define K_INT_MAP_I0	0		/* interrupt pins on processor */
#define K_INT_MAP_I1	1
#define K_INT_MAP_I2	2
#define K_INT_MAP_I3	3
#define K_INT_MAP_I4	4
#define K_INT_MAP_I5	5
#define K_INT_MAP_NMI	6		/* nonmaskable */
#define K_INT_MAP_DINT	7		/* debug interrupt */

/*
 * LDT Interrupt Set Register (table 4-5)
 */

#define S_INT_LDT_INTMSG	      0
#define M_INT_LDT_INTMSG	      _SB_MAKEMASK(3, S_INT_LDT_INTMSG)
#define V_INT_LDT_INTMSG(x)	      _SB_MAKEVALUE(x, S_INT_LDT_INTMSG)
#define G_INT_LDT_INTMSG(x)	      _SB_GETVALUE(x, S_INT_LDT_INTMSG, M_INT_LDT_INTMSG)

#define K_INT_LDT_INTMSG_FIXED	      0
#define K_INT_LDT_INTMSG_ARBITRATED   1
#define K_INT_LDT_INTMSG_SMI	      2
#define K_INT_LDT_INTMSG_NMI	      3
#define K_INT_LDT_INTMSG_INIT	      4
#define K_INT_LDT_INTMSG_STARTUP      5
#define K_INT_LDT_INTMSG_EXTINT	      6
#define K_INT_LDT_INTMSG_RESERVED     7

#define M_INT_LDT_EDGETRIGGER	      0
#define M_INT_LDT_LEVELTRIGGER	      _SB_MAKEMASK1(3)

#define M_INT_LDT_PHYSICALDEST	      0
#define M_INT_LDT_LOGICALDEST	      _SB_MAKEMASK1(4)

#define S_INT_LDT_INTDEST	      5
#define M_INT_LDT_INTDEST	      _SB_MAKEMASK(10, S_INT_LDT_INTDEST)
#define V_INT_LDT_INTDEST(x)	      _SB_MAKEVALUE(x, S_INT_LDT_INTDEST)
#define G_INT_LDT_INTDEST(x)	      _SB_GETVALUE(x, S_INT_LDT_INTDEST, M_INT_LDT_INTDEST)

#define S_INT_LDT_VECTOR	      13
#define M_INT_LDT_VECTOR	      _SB_MAKEMASK(8, S_INT_LDT_VECTOR)
#define V_INT_LDT_VECTOR(x)	      _SB_MAKEVALUE(x, S_INT_LDT_VECTOR)
#define G_INT_LDT_VECTOR(x)	      _SB_GETVALUE(x, S_INT_LDT_VECTOR, M_INT_LDT_VECTOR)

/*
 * Vector format (Table 4-6)
 */

#define M_LDTVECT_RAISEINT		0x00
#define M_LDTVECT_RAISEMBOX		0x40


#endif	/* 1250/112x */
Commit	Line	Data
1a59d1b8	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
1da177e4 LT	2	/* *********************************************************************
1da177e4 LT	3	* SB1250 Board Support Package
42a3b4f2	4	*
1da177e4	5	* Interrupt Mapper definitions File: sb1250_int.h
42a3b4f2	6	*
1da177e4 LT	7	* This module contains constants for manipulating the SB1250's
1da177e4 LT	8	* interrupt mapper and definitions for the interrupt sources.
42a3b4f2	9	*
1da177e4	10	* SB1250 specification level: User's manual 1/02/02
42a3b4f2	11	*
42a3b4f2	12	*********************************************************************
1da177e4	13	*
21a151d8	14	* Copyright 2000, 2001, 2002, 2003
1da177e4	15	* Broadcom Corporation. All rights reserved.
42a3b4f2	16	*
1da177e4 LT	17	********************************************************************* */
	18
	19
	20	#ifndef _SB1250_INT_H
	21	#define _SB1250_INT_H
	22
a1ce3928	23	#include <asm/sibyte/sb1250_defs.h>
1da177e4 LT	24
	25	/* *********************************************************************
	26	* Interrupt Mapper Constants
	27	********************************************************************* */
	28
	29	/*
	30	* Interrupt sources (Table 4-8, UM 0.2)
42a3b4f2	31	*
1da177e4 LT	32	* First, the interrupt numbers.
	33	*/
	34
70342287 RB	35	#define K_INT_SOURCES 64
	36
	37	#define K_INT_WATCHDOG_TIMER_0 0
	38	#define K_INT_WATCHDOG_TIMER_1 1
	39	#define K_INT_TIMER_0 2
	40	#define K_INT_TIMER_1 3
	41	#define K_INT_TIMER_2 4
	42	#define K_INT_TIMER_3 5
	43	#define K_INT_SMB_0 6
	44	#define K_INT_SMB_1 7
	45	#define K_INT_UART_0 8
	46	#define K_INT_UART_1 9
	47	#define K_INT_SER_0 10
	48	#define K_INT_SER_1 11
	49	#define K_INT_PCMCIA 12
	50	#define K_INT_ADDR_TRAP 13
	51	#define K_INT_PERF_CNT 14
	52	#define K_INT_TRACE_FREEZE 15
	53	#define K_INT_BAD_ECC 16
	54	#define K_INT_COR_ECC 17
	55	#define K_INT_IO_BUS 18
	56	#define K_INT_MAC_0 19
	57	#define K_INT_MAC_1 20
	58	#define K_INT_MAC_2 21
	59	#define K_INT_DM_CH_0 22
	60	#define K_INT_DM_CH_1 23
	61	#define K_INT_DM_CH_2 24
	62	#define K_INT_DM_CH_3 25
	63	#define K_INT_MBOX_0 26
	64	#define K_INT_MBOX_1 27
	65	#define K_INT_MBOX_2 28
	66	#define K_INT_MBOX_3 29
1da177e4 LT	67	#if SIBYTE_HDR_FEATURE(1250, PASS2) \|\| SIBYTE_HDR_FEATURE(112x, PASS1)
	68	#define K_INT_CYCLE_CP0_INT 30
	69	#define K_INT_CYCLE_CP1_INT 31
	70	#endif /* 1250 PASS2 \|\| 112x PASS1 */
70342287 RB	71	#define K_INT_GPIO_0 32
	72	#define K_INT_GPIO_1 33
	73	#define K_INT_GPIO_2 34
	74	#define K_INT_GPIO_3 35
	75	#define K_INT_GPIO_4 36
	76	#define K_INT_GPIO_5 37
	77	#define K_INT_GPIO_6 38
	78	#define K_INT_GPIO_7 39
	79	#define K_INT_GPIO_8 40
	80	#define K_INT_GPIO_9 41
	81	#define K_INT_GPIO_10 42
	82	#define K_INT_GPIO_11 43
	83	#define K_INT_GPIO_12 44
	84	#define K_INT_GPIO_13 45
	85	#define K_INT_GPIO_14 46
	86	#define K_INT_GPIO_15 47
	87	#define K_INT_LDT_FATAL 48
	88	#define K_INT_LDT_NONFATAL 49
	89	#define K_INT_LDT_SMI 50
	90	#define K_INT_LDT_NMI 51
	91	#define K_INT_LDT_INIT 52
	92	#define K_INT_LDT_STARTUP 53
	93	#define K_INT_LDT_EXT 54
	94	#define K_INT_PCI_ERROR 55
	95	#define K_INT_PCI_INTA 56
	96	#define K_INT_PCI_INTB 57
	97	#define K_INT_PCI_INTC 58
	98	#define K_INT_PCI_INTD 59
	99	#define K_INT_SPARE_2 60
1da177e4 LT	100	#if SIBYTE_HDR_FEATURE(1250, PASS2) \|\| SIBYTE_HDR_FEATURE(112x, PASS1)
	101	#define K_INT_MAC_0_CH1 61
	102	#define K_INT_MAC_1_CH1 62
	103	#define K_INT_MAC_2_CH1 63
	104	#endif /* 1250 PASS2 \|\| 112x PASS1 */
	105
	106	/*
	107	* Mask values for each interrupt
	108	*/
	109
70342287 RB	110	#define M_INT_WATCHDOG_TIMER_0 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_0)
	111	#define M_INT_WATCHDOG_TIMER_1 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_1)
	112	#define M_INT_TIMER_0 _SB_MAKEMASK1(K_INT_TIMER_0)
	113	#define M_INT_TIMER_1 _SB_MAKEMASK1(K_INT_TIMER_1)
	114	#define M_INT_TIMER_2 _SB_MAKEMASK1(K_INT_TIMER_2)
	115	#define M_INT_TIMER_3 _SB_MAKEMASK1(K_INT_TIMER_3)
	116	#define M_INT_SMB_0 _SB_MAKEMASK1(K_INT_SMB_0)
	117	#define M_INT_SMB_1 _SB_MAKEMASK1(K_INT_SMB_1)
	118	#define M_INT_UART_0 _SB_MAKEMASK1(K_INT_UART_0)
	119	#define M_INT_UART_1 _SB_MAKEMASK1(K_INT_UART_1)
	120	#define M_INT_SER_0 _SB_MAKEMASK1(K_INT_SER_0)
	121	#define M_INT_SER_1 _SB_MAKEMASK1(K_INT_SER_1)
	122	#define M_INT_PCMCIA _SB_MAKEMASK1(K_INT_PCMCIA)
	123	#define M_INT_ADDR_TRAP _SB_MAKEMASK1(K_INT_ADDR_TRAP)
	124	#define M_INT_PERF_CNT _SB_MAKEMASK1(K_INT_PERF_CNT)
	125	#define M_INT_TRACE_FREEZE _SB_MAKEMASK1(K_INT_TRACE_FREEZE)
	126	#define M_INT_BAD_ECC _SB_MAKEMASK1(K_INT_BAD_ECC)
	127	#define M_INT_COR_ECC _SB_MAKEMASK1(K_INT_COR_ECC)
	128	#define M_INT_IO_BUS _SB_MAKEMASK1(K_INT_IO_BUS)
	129	#define M_INT_MAC_0 _SB_MAKEMASK1(K_INT_MAC_0)
	130	#define M_INT_MAC_1 _SB_MAKEMASK1(K_INT_MAC_1)
	131	#define M_INT_MAC_2 _SB_MAKEMASK1(K_INT_MAC_2)
	132	#define M_INT_DM_CH_0 _SB_MAKEMASK1(K_INT_DM_CH_0)
	133	#define M_INT_DM_CH_1 _SB_MAKEMASK1(K_INT_DM_CH_1)
	134	#define M_INT_DM_CH_2 _SB_MAKEMASK1(K_INT_DM_CH_2)
	135	#define M_INT_DM_CH_3 _SB_MAKEMASK1(K_INT_DM_CH_3)
	136	#define M_INT_MBOX_0 _SB_MAKEMASK1(K_INT_MBOX_0)
	137	#define M_INT_MBOX_1 _SB_MAKEMASK1(K_INT_MBOX_1)
	138	#define M_INT_MBOX_2 _SB_MAKEMASK1(K_INT_MBOX_2)
	139	#define M_INT_MBOX_3 _SB_MAKEMASK1(K_INT_MBOX_3)
	140	#define M_INT_MBOX_ALL _SB_MAKEMASK(4, K_INT_MBOX_0)
1da177e4 LT	141	#if SIBYTE_HDR_FEATURE(1250, PASS2) \|\| SIBYTE_HDR_FEATURE(112x, PASS1)
	142	#define M_INT_CYCLE_CP0_INT _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT)
	143	#define M_INT_CYCLE_CP1_INT _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT)
	144	#endif /* 1250 PASS2 \|\| 112x PASS1 */
70342287 RB	145	#define M_INT_GPIO_0 _SB_MAKEMASK1(K_INT_GPIO_0)
	146	#define M_INT_GPIO_1 _SB_MAKEMASK1(K_INT_GPIO_1)
	147	#define M_INT_GPIO_2 _SB_MAKEMASK1(K_INT_GPIO_2)
	148	#define M_INT_GPIO_3 _SB_MAKEMASK1(K_INT_GPIO_3)
	149	#define M_INT_GPIO_4 _SB_MAKEMASK1(K_INT_GPIO_4)
	150	#define M_INT_GPIO_5 _SB_MAKEMASK1(K_INT_GPIO_5)
	151	#define M_INT_GPIO_6 _SB_MAKEMASK1(K_INT_GPIO_6)
	152	#define M_INT_GPIO_7 _SB_MAKEMASK1(K_INT_GPIO_7)
	153	#define M_INT_GPIO_8 _SB_MAKEMASK1(K_INT_GPIO_8)
	154	#define M_INT_GPIO_9 _SB_MAKEMASK1(K_INT_GPIO_9)
	155	#define M_INT_GPIO_10 _SB_MAKEMASK1(K_INT_GPIO_10)
	156	#define M_INT_GPIO_11 _SB_MAKEMASK1(K_INT_GPIO_11)
	157	#define M_INT_GPIO_12 _SB_MAKEMASK1(K_INT_GPIO_12)
	158	#define M_INT_GPIO_13 _SB_MAKEMASK1(K_INT_GPIO_13)
	159	#define M_INT_GPIO_14 _SB_MAKEMASK1(K_INT_GPIO_14)
	160	#define M_INT_GPIO_15 _SB_MAKEMASK1(K_INT_GPIO_15)
	161	#define M_INT_LDT_FATAL _SB_MAKEMASK1(K_INT_LDT_FATAL)
	162	#define M_INT_LDT_NONFATAL _SB_MAKEMASK1(K_INT_LDT_NONFATAL)
	163	#define M_INT_LDT_SMI _SB_MAKEMASK1(K_INT_LDT_SMI)
	164	#define M_INT_LDT_NMI _SB_MAKEMASK1(K_INT_LDT_NMI)
	165	#define M_INT_LDT_INIT _SB_MAKEMASK1(K_INT_LDT_INIT)
	166	#define M_INT_LDT_STARTUP _SB_MAKEMASK1(K_INT_LDT_STARTUP)
	167	#define M_INT_LDT_EXT _SB_MAKEMASK1(K_INT_LDT_EXT)
	168	#define M_INT_PCI_ERROR _SB_MAKEMASK1(K_INT_PCI_ERROR)
	169	#define M_INT_PCI_INTA _SB_MAKEMASK1(K_INT_PCI_INTA)
	170	#define M_INT_PCI_INTB _SB_MAKEMASK1(K_INT_PCI_INTB)
	171	#define M_INT_PCI_INTC _SB_MAKEMASK1(K_INT_PCI_INTC)
	172	#define M_INT_PCI_INTD _SB_MAKEMASK1(K_INT_PCI_INTD)
	173	#define M_INT_SPARE_2 _SB_MAKEMASK1(K_INT_SPARE_2)
1da177e4 LT	174	#if SIBYTE_HDR_FEATURE(1250, PASS2) \|\| SIBYTE_HDR_FEATURE(112x, PASS1)
	175	#define M_INT_MAC_0_CH1 _SB_MAKEMASK1(K_INT_MAC_0_CH1)
	176	#define M_INT_MAC_1_CH1 _SB_MAKEMASK1(K_INT_MAC_1_CH1)
	177	#define M_INT_MAC_2_CH1 _SB_MAKEMASK1(K_INT_MAC_2_CH1)
	178	#endif /* 1250 PASS2 \|\| 112x PASS1 */
	179
	180	/*
	181	* Interrupt mappings
	182	*/
	183
	184	#define K_INT_MAP_I0 0 /* interrupt pins on processor */
	185	#define K_INT_MAP_I1 1
	186	#define K_INT_MAP_I2 2
	187	#define K_INT_MAP_I3 3
	188	#define K_INT_MAP_I4 4
	189	#define K_INT_MAP_I5 5
	190	#define K_INT_MAP_NMI 6 /* nonmaskable */
	191	#define K_INT_MAP_DINT 7 /* debug interrupt */
	192
	193	/*
	194	* LDT Interrupt Set Register (table 4-5)
	195	*/
	196
	197	#define S_INT_LDT_INTMSG 0
70342287 RB	198	#define M_INT_LDT_INTMSG _SB_MAKEMASK(3, S_INT_LDT_INTMSG)
	199	#define V_INT_LDT_INTMSG(x) _SB_MAKEVALUE(x, S_INT_LDT_INTMSG)
	200	#define G_INT_LDT_INTMSG(x) _SB_GETVALUE(x, S_INT_LDT_INTMSG, M_INT_LDT_INTMSG)
1da177e4 LT	201
	202	#define K_INT_LDT_INTMSG_FIXED 0
	203	#define K_INT_LDT_INTMSG_ARBITRATED 1
	204	#define K_INT_LDT_INTMSG_SMI 2
	205	#define K_INT_LDT_INTMSG_NMI 3
	206	#define K_INT_LDT_INTMSG_INIT 4
	207	#define K_INT_LDT_INTMSG_STARTUP 5
	208	#define K_INT_LDT_INTMSG_EXTINT 6
	209	#define K_INT_LDT_INTMSG_RESERVED 7
	210
70342287 RB	211	#define M_INT_LDT_EDGETRIGGER 0
70342287 RB	212	#define M_INT_LDT_LEVELTRIGGER _SB_MAKEMASK1(3)
1da177e4	213
70342287 RB	214	#define M_INT_LDT_PHYSICALDEST 0
70342287 RB	215	#define M_INT_LDT_LOGICALDEST _SB_MAKEMASK1(4)
1da177e4	216
70342287 RB	217	#define S_INT_LDT_INTDEST 5
	218	#define M_INT_LDT_INTDEST _SB_MAKEMASK(10, S_INT_LDT_INTDEST)
	219	#define V_INT_LDT_INTDEST(x) _SB_MAKEVALUE(x, S_INT_LDT_INTDEST)
	220	#define G_INT_LDT_INTDEST(x) _SB_GETVALUE(x, S_INT_LDT_INTDEST, M_INT_LDT_INTDEST)
1da177e4	221
70342287 RB	222	#define S_INT_LDT_VECTOR 13
	223	#define M_INT_LDT_VECTOR _SB_MAKEMASK(8, S_INT_LDT_VECTOR)
	224	#define V_INT_LDT_VECTOR(x) _SB_MAKEVALUE(x, S_INT_LDT_VECTOR)
	225	#define G_INT_LDT_VECTOR(x) _SB_GETVALUE(x, S_INT_LDT_VECTOR, M_INT_LDT_VECTOR)
1da177e4 LT	226
	227	/*
	228	* Vector format (Table 4-6)
	229	*/
	230
	231	#define M_LDTVECT_RAISEINT 0x00
70342287	232	#define M_LDTVECT_RAISEMBOX 0x40
1da177e4 LT	233
1da177e4 LT	234
4cbf2bea	235	#endif /* 1250/112x */