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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
1da177e4 LT |
2 | /* thread_info.h: MIPS low-level thread information |
3 | * | |
4 | * Copyright (C) 2002 David Howells (dhowells@redhat.com) | |
5 | * - Incorporating suggestions made by Linus Torvalds and Dave Miller | |
6 | */ | |
7 | ||
8 | #ifndef _ASM_THREAD_INFO_H | |
9 | #define _ASM_THREAD_INFO_H | |
10 | ||
11 | #ifdef __KERNEL__ | |
12 | ||
1da177e4 LT |
13 | |
14 | #ifndef __ASSEMBLY__ | |
15 | ||
16 | #include <asm/processor.h> | |
17 | ||
18 | /* | |
19 | * low level task data that entry.S needs immediate access to | |
20 | * - this struct should fit entirely inside of one cache line | |
21 | * - this struct shares the supervisor stack pages | |
22 | * - if the contents of this structure are changed, the assembly constants | |
23 | * must also be changed | |
24 | */ | |
25 | struct thread_info { | |
26 | struct task_struct *task; /* main task structure */ | |
1da177e4 | 27 | unsigned long flags; /* low level flags */ |
3c37026d | 28 | unsigned long tp_value; /* thread pointer */ |
1da177e4 | 29 | __u32 cpu; /* current CPU */ |
dcd497f9 | 30 | int preempt_count; /* 0 => preemptable, <0 => BUG */ |
937a8015 | 31 | struct pt_regs *regs; |
c2d9f177 | 32 | long syscall; /* syscall number */ |
1da177e4 LT |
33 | }; |
34 | ||
35 | /* | |
36 | * macros/functions for gaining access to the thread information structure | |
1da177e4 LT |
37 | */ |
38 | #define INIT_THREAD_INFO(tsk) \ | |
39 | { \ | |
40 | .task = &tsk, \ | |
293c5bd1 | 41 | .flags = _TIF_FIXADE, \ |
1da177e4 | 42 | .cpu = 0, \ |
c99e6efe | 43 | .preempt_count = INIT_PREEMPT_COUNT, \ |
1da177e4 LT |
44 | } |
45 | ||
bbcc5672 PB |
46 | /* |
47 | * A pointer to the struct thread_info for the currently executing thread is | |
48 | * held in register $28/$gp. | |
49 | * | |
50 | * We declare __current_thread_info as a global register variable rather than a | |
51 | * local register variable within current_thread_info() because clang doesn't | |
52 | * support explicit local register variables. | |
53 | * | |
54 | * When building the VDSO we take care not to declare the global register | |
55 | * variable because this causes GCC to not preserve the value of $28/$gp in | |
56 | * functions that change its value (which is common in the PIC VDSO when | |
57 | * accessing the GOT). Since the VDSO shouldn't be accessing | |
58 | * __current_thread_info anyway we declare it extern in order to cause a link | |
59 | * failure if it's referenced. | |
60 | */ | |
61 | #ifdef __VDSO__ | |
62 | extern struct thread_info *__current_thread_info; | |
63 | #else | |
fe92da0f | 64 | register struct thread_info *__current_thread_info __asm__("$28"); |
bbcc5672 | 65 | #endif |
fe92da0f | 66 | |
ad04c2e9 RB |
67 | static inline struct thread_info *current_thread_info(void) |
68 | { | |
ad04c2e9 RB |
69 | return __current_thread_info; |
70 | } | |
1da177e4 | 71 | |
7b1c0d26 DD |
72 | #endif /* !__ASSEMBLY__ */ |
73 | ||
1da177e4 | 74 | /* thread information allocation */ |
875d43e7 | 75 | #if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_32BIT) |
1da177e4 LT |
76 | #define THREAD_SIZE_ORDER (1) |
77 | #endif | |
875d43e7 | 78 | #if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_64BIT) |
1da177e4 LT |
79 | #define THREAD_SIZE_ORDER (2) |
80 | #endif | |
81 | #ifdef CONFIG_PAGE_SIZE_8KB | |
82 | #define THREAD_SIZE_ORDER (1) | |
83 | #endif | |
84 | #ifdef CONFIG_PAGE_SIZE_16KB | |
85 | #define THREAD_SIZE_ORDER (0) | |
86 | #endif | |
c52399be RB |
87 | #ifdef CONFIG_PAGE_SIZE_32KB |
88 | #define THREAD_SIZE_ORDER (0) | |
89 | #endif | |
1da177e4 LT |
90 | #ifdef CONFIG_PAGE_SIZE_64KB |
91 | #define THREAD_SIZE_ORDER (0) | |
92 | #endif | |
93 | ||
94 | #define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER) | |
95 | #define THREAD_MASK (THREAD_SIZE - 1UL) | |
96 | ||
334c86c4 F |
97 | #define STACK_WARN (THREAD_SIZE / 8) |
98 | ||
1da177e4 LT |
99 | /* |
100 | * thread information flags | |
101 | * - these are process state flags that various assembly files may need to | |
102 | * access | |
103 | * - pending work-to-be-done flags are in LSW | |
104 | * - other flags in MSW | |
105 | */ | |
a583f1b5 SE |
106 | #define TIF_SIGPENDING 1 /* signal pending */ |
107 | #define TIF_NEED_RESCHED 2 /* rescheduling necessary */ | |
108 | #define TIF_SYSCALL_AUDIT 3 /* syscall auditing active */ | |
109 | #define TIF_SECCOMP 4 /* secure computing */ | |
d0420c83 | 110 | #define TIF_NOTIFY_RESUME 5 /* callback before returning to user */ |
40e084a5 | 111 | #define TIF_UPROBE 6 /* breakpointed or singlestepping */ |
f45c184b | 112 | #define TIF_NOTIFY_SIGNAL 7 /* signal notifications exist */ |
7b3e2fc8 | 113 | #define TIF_RESTORE_SIGMASK 9 /* restore signal mask in do_signal() */ |
1da177e4 | 114 | #define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */ |
0ddc9324 | 115 | #define TIF_MEMDIE 18 /* is terminating due to OOM killer */ |
c3fc5cd5 | 116 | #define TIF_NOHZ 19 /* in adaptive nohz mode */ |
293c5bd1 RB |
117 | #define TIF_FIXADE 20 /* Fix address errors in software */ |
118 | #define TIF_LOGADE 21 /* Log address errors to syslog */ | |
597ce172 | 119 | #define TIF_32BIT_REGS 22 /* 32-bit general purpose registers */ |
293c5bd1 RB |
120 | #define TIF_32BIT_ADDR 23 /* 32-bit address space (o32/n32) */ |
121 | #define TIF_FPUBOUND 24 /* thread bound to FPU-full CPU set */ | |
6aa3524c | 122 | #define TIF_LOAD_WATCH 25 /* If set, load watch registers */ |
1d7bf993 | 123 | #define TIF_SYSCALL_TRACEPOINT 26 /* syscall tracepoint instrumentation */ |
597ce172 | 124 | #define TIF_32BIT_FPREGS 27 /* 32-bit floating point registers */ |
4227a2d4 | 125 | #define TIF_HYBRID_FPREGS 28 /* 64b FP registers, odd singles in bits 63:32 of even doubles */ |
1db1af84 PB |
126 | #define TIF_USEDMSA 29 /* MSA has been used this quantum */ |
127 | #define TIF_MSA_CTX_LIVE 30 /* MSA context must be preserved */ | |
1da177e4 LT |
128 | #define TIF_SYSCALL_TRACE 31 /* syscall trace active */ |
129 | ||
130 | #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) | |
1da177e4 LT |
131 | #define _TIF_SIGPENDING (1<<TIF_SIGPENDING) |
132 | #define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) | |
133 | #define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT) | |
127c6f66 | 134 | #define _TIF_SECCOMP (1<<TIF_SECCOMP) |
d0420c83 | 135 | #define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) |
40e084a5 | 136 | #define _TIF_UPROBE (1<<TIF_UPROBE) |
f45c184b | 137 | #define _TIF_NOTIFY_SIGNAL (1<<TIF_NOTIFY_SIGNAL) |
1da177e4 | 138 | #define _TIF_USEDFPU (1<<TIF_USEDFPU) |
c3fc5cd5 | 139 | #define _TIF_NOHZ (1<<TIF_NOHZ) |
293c5bd1 RB |
140 | #define _TIF_FIXADE (1<<TIF_FIXADE) |
141 | #define _TIF_LOGADE (1<<TIF_LOGADE) | |
142 | #define _TIF_32BIT_REGS (1<<TIF_32BIT_REGS) | |
143 | #define _TIF_32BIT_ADDR (1<<TIF_32BIT_ADDR) | |
144 | #define _TIF_FPUBOUND (1<<TIF_FPUBOUND) | |
6aa3524c | 145 | #define _TIF_LOAD_WATCH (1<<TIF_LOAD_WATCH) |
597ce172 | 146 | #define _TIF_32BIT_FPREGS (1<<TIF_32BIT_FPREGS) |
4227a2d4 | 147 | #define _TIF_HYBRID_FPREGS (1<<TIF_HYBRID_FPREGS) |
1db1af84 PB |
148 | #define _TIF_USEDMSA (1<<TIF_USEDMSA) |
149 | #define _TIF_MSA_CTX_LIVE (1<<TIF_MSA_CTX_LIVE) | |
1d7bf993 | 150 | #define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT) |
1da177e4 | 151 | |
c3fc5cd5 | 152 | #define _TIF_WORK_SYSCALL_ENTRY (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \ |
137f7df8 MC |
153 | _TIF_SYSCALL_AUDIT | \ |
154 | _TIF_SYSCALL_TRACEPOINT | _TIF_SECCOMP) | |
e7f3b48a | 155 | |
c19c20ac | 156 | /* work to do in syscall_trace_leave() */ |
c3fc5cd5 | 157 | #define _TIF_WORK_SYSCALL_EXIT (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \ |
1d7bf993 | 158 | _TIF_SYSCALL_AUDIT | _TIF_SYSCALL_TRACEPOINT) |
c19c20ac | 159 | |
127c6f66 | 160 | /* work to do on interrupt/exception return */ |
f925725d | 161 | #define _TIF_WORK_MASK \ |
40e084a5 | 162 | (_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_NOTIFY_RESUME | \ |
f45c184b | 163 | _TIF_UPROBE | _TIF_NOTIFY_SIGNAL) |
127c6f66 | 164 | /* work to do on any return to u-space */ |
c3fc5cd5 | 165 | #define _TIF_ALLWORK_MASK (_TIF_NOHZ | _TIF_WORK_MASK | \ |
1d7bf993 RB |
166 | _TIF_WORK_SYSCALL_EXIT | \ |
167 | _TIF_SYSCALL_TRACEPOINT) | |
1da177e4 | 168 | |
c2377a42 J |
169 | /* |
170 | * We stash processor id into a COP0 register to retrieve it fast | |
171 | * at kernel exception entry. | |
172 | */ | |
b633648c | 173 | #if defined(CONFIG_MIPS_PGD_C0_CONTEXT) |
c2377a42 J |
174 | #define SMP_CPUID_REG 20, 0 /* XCONTEXT */ |
175 | #define ASM_SMP_CPUID_REG $20 | |
176 | #define SMP_CPUID_PTRSHIFT 48 | |
177 | #else | |
178 | #define SMP_CPUID_REG 4, 0 /* CONTEXT */ | |
179 | #define ASM_SMP_CPUID_REG $4 | |
180 | #define SMP_CPUID_PTRSHIFT 23 | |
181 | #endif | |
1da177e4 | 182 | |
c2377a42 J |
183 | #ifdef CONFIG_64BIT |
184 | #define SMP_CPUID_REGSHIFT (SMP_CPUID_PTRSHIFT + 3) | |
185 | #else | |
186 | #define SMP_CPUID_REGSHIFT (SMP_CPUID_PTRSHIFT + 2) | |
187 | #endif | |
188 | ||
c2377a42 J |
189 | #define ASM_CPUID_MFC0 MFC0 |
190 | #define UASM_i_CPUID_MFC0 UASM_i_MFC0 | |
c2377a42 J |
191 | |
192 | #endif /* __KERNEL__ */ | |
1da177e4 | 193 | #endif /* _ASM_THREAD_INFO_H */ |