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License cleanup: add SPDX license identifier to uapi header files with a license
[mirror_ubuntu-eoan-kernel.git] / arch / mips / include / uapi / asm / inst.h
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e2be04c7 1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
90e8cacd
RB		 2/*
3 * Format of an instruction in memory.
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 *
9 * Copyright (C) 1996, 2000 by Ralf Baechle
10 * Copyright (C) 2006 by Thiemo Seufer
2aa9fd06 11 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
aa1af47f 12 * Copyright (C) 2014 Imagination Technologies Ltd.
90e8cacd
RB		 13 */
14#ifndef _UAPI_ASM_INST_H
15#define _UAPI_ASM_INST_H
16
64a17a0f
RB		 17#include <asm/bitfield.h>
18
90e8cacd
RB		 19/*
20 * Major opcodes; before MIPS IV cop1x was called cop3.
21 */
22enum major_op {
23 spec_op, bcond_op, j_op, jal_op,
24 beq_op, bne_op, blez_op, bgtz_op,
1b492600 25 addi_op, pop10_op = addi_op, addiu_op, slti_op, sltiu_op,
90e8cacd
RB		 26 andi_op, ori_op, xori_op, lui_op,
27 cop0_op, cop1_op, cop2_op, cop1x_op,
28 beql_op, bnel_op, blezl_op, bgtzl_op,
1b492600 29 daddi_op, pop30_op = daddi_op, daddiu_op, ldl_op, ldr_op,
6701ca2d 30 spec2_op, jalx_op, mdmx_op, msa_op = mdmx_op, spec3_op,
90e8cacd
RB		 31 lb_op, lh_op, lwl_op, lw_op,
32 lbu_op, lhu_op, lwr_op, lwu_op,
33 sb_op, sh_op, swl_op, sw_op,
34 sdl_op, sdr_op, swr_op, cache_op,
8467ca01 35 ll_op, lwc1_op, lwc2_op, bc6_op = lwc2_op, pref_op,
1c66b79b 36 lld_op, ldc1_op, ldc2_op, pop66_op = ldc2_op, ld_op,
84fef630 37 sc_op, swc1_op, swc2_op, balc6_op = swc2_op, major_3b_op,
1c66b79b 38 scd_op, sdc1_op, sdc2_op, pop76_op = sdc2_op, sd_op
90e8cacd
RB		 39};
40
41/*
42 * func field of spec opcode.
43 */
44enum spec_op {
45 sll_op, movc_op, srl_op, sra_op,
46 sllv_op, pmon_op, srlv_op, srav_op,
47 jr_op, jalr_op, movz_op, movn_op,
48 syscall_op, break_op, spim_op, sync_op,
49 mfhi_op, mthi_op, mflo_op, mtlo_op,
50 dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
51 mult_op, multu_op, div_op, divu_op,
52 dmult_op, dmultu_op, ddiv_op, ddivu_op,
53 add_op, addu_op, sub_op, subu_op,
54 and_op, or_op, xor_op, nor_op,
55 spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
56 dadd_op, daddu_op, dsub_op, dsubu_op,
57 tge_op, tgeu_op, tlt_op, tltu_op,
58 teq_op, spec5_unused_op, tne_op, spec6_unused_op,
59 dsll_op, spec7_unused_op, dsrl_op, dsra_op,
60 dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
61};
62
63/*
64 * func field of spec2 opcode.
65 */
66enum spec2_op {
67 madd_op, maddu_op, mul_op, spec2_3_unused_op,
68 msub_op, msubu_op, /* more unused ops */
69 clz_op = 0x20, clo_op,
70 dclz_op = 0x24, dclo_op,
71 sdbpp_op = 0x3f
72};
73
74/*
75 * func field of spec3 opcode.
76 */
77enum spec3_op {
78 ext_op, dextm_op, dextu_op, dext_op,
79 ins_op, dinsm_op, dinsu_op, dins_op,
6f5bb424
PB		 80 yield_op = 0x09, lx_op = 0x0a,
81 lwle_op = 0x19, lwre_op = 0x1a,
82 cachee_op = 0x1b, sbe_op = 0x1c,
83 she_op = 0x1d, sce_op = 0x1e,
84 swe_op = 0x1f, bshfl_op = 0x20,
85 swle_op = 0x21, swre_op = 0x22,
86 prefe_op = 0x23, dbshfl_op = 0x24,
a168b8f1
LY		 87 cache6_op = 0x25, sc6_op = 0x26,
88 scd6_op = 0x27, lbue_op = 0x28,
89 lhue_op = 0x29, lbe_op = 0x2c,
90 lhe_op = 0x2d, lle_op = 0x2e,
91 lwe_op = 0x2f, pref6_op = 0x35,
92 ll6_op = 0x36, lld6_op = 0x37,
6f5bb424 93 rdhwr_op = 0x3b
90e8cacd
RB		 94};
95
6f63405c
JH		 96/*
97 * Bits 10-6 minor opcode for r6 spec mult/div encodings
98 */
99enum mult_op {
100 mult_mult_op = 0x0,
101 mult_mul_op = 0x2,
102 mult_muh_op = 0x3,
103};
104enum multu_op {
105 multu_multu_op = 0x0,
106 multu_mulu_op = 0x2,
107 multu_muhu_op = 0x3,
108};
109enum div_op {
110 div_div_op = 0x0,
111 div_div6_op = 0x2,
112 div_mod_op = 0x3,
113};
114enum divu_op {
115 divu_divu_op = 0x0,
116 divu_divu6_op = 0x2,
117 divu_modu_op = 0x3,
118};
119enum dmult_op {
120 dmult_dmult_op = 0x0,
121 dmult_dmul_op = 0x2,
122 dmult_dmuh_op = 0x3,
123};
124enum dmultu_op {
125 dmultu_dmultu_op = 0x0,
126 dmultu_dmulu_op = 0x2,
127 dmultu_dmuhu_op = 0x3,
128};
129enum ddiv_op {
130 ddiv_ddiv_op = 0x0,
131 ddiv_ddiv6_op = 0x2,
132 ddiv_dmod_op = 0x3,
133};
134enum ddivu_op {
135 ddivu_ddivu_op = 0x0,
136 ddivu_ddivu6_op = 0x2,
137 ddivu_dmodu_op = 0x3,
138};
139
90e8cacd
RB		 140/*
141 * rt field of bcond opcodes.
142 */
143enum rt_op {
144 bltz_op, bgez_op, bltzl_op, bgezl_op,
145 spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
146 tgei_op, tgeiu_op, tlti_op, tltiu_op,
147 teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
148 bltzal_op, bgezal_op, bltzall_op, bgezall_op,
149 rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
150 rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
258f3a2e 151 bposge32_op, rt_op_0x1d, rt_op_0x1e, synci_op
90e8cacd
RB		 152};
153
154/*
155 * rs field of cop opcodes.
156 */
157enum cop_op {
70342287 158 mfc_op = 0x00, dmfc_op = 0x01,
e2965cd0
SH		 159 cfc_op = 0x02, mfhc0_op = 0x02,
160 mfhc_op = 0x03, mtc_op = 0x04,
161 dmtc_op = 0x05, ctc_op = 0x06,
162 mthc0_op = 0x06, mthc_op = 0x07,
c8a34581 163 bc_op = 0x08, bc1eqz_op = 0x09,
b2c59635
JH		 164 mfmc0_op = 0x0b, bc1nez_op = 0x0d,
165 wrpgpr_op = 0x0e, cop_op = 0x10,
70342287 166 copm_op = 0x18
90e8cacd
RB		 167};
168
169/*
170 * rt field of cop.bc_op opcodes
171 */
172enum bcop_op {
173 bcf_op, bct_op, bcfl_op, bctl_op
174};
175
176/*
177 * func field of cop0 coi opcodes.
178 */
179enum cop0_coi_func {
70342287
RB		 180 tlbr_op = 0x01, tlbwi_op = 0x02,
181 tlbwr_op = 0x06, tlbp_op = 0x08,
b0a3eae2 182 rfe_op = 0x10, eret_op = 0x18,
955d8dc3 183 wait_op = 0x20, hypcall_op = 0x28
90e8cacd
RB		 184};
185
186/*
187 * func field of cop0 com opcodes.
188 */
189enum cop0_com_func {
70342287
RB		 190 tlbr1_op = 0x01, tlbw_op = 0x02,
191 tlbp1_op = 0x08, dctr_op = 0x09,
192 dctw_op = 0x0a
90e8cacd
RB		 193};
194
195/*
196 * fmt field of cop1 opcodes.
197 */
198enum cop1_fmt {
199 s_fmt, d_fmt, e_fmt, q_fmt,
200 w_fmt, l_fmt
201};
202
203/*
204 * func field of cop1 instructions using d, s or w format.
205 */
206enum cop1_sdw_func {
70342287
RB		 207 fadd_op = 0x00, fsub_op = 0x01,
208 fmul_op = 0x02, fdiv_op = 0x03,
209 fsqrt_op = 0x04, fabs_op = 0x05,
210 fmov_op = 0x06, fneg_op = 0x07,
211 froundl_op = 0x08, ftruncl_op = 0x09,
212 fceill_op = 0x0a, ffloorl_op = 0x0b,
213 fround_op = 0x0c, ftrunc_op = 0x0d,
214 fceil_op = 0x0e, ffloor_op = 0x0f,
b6d5c4ed 215 fsel_op = 0x10,
70342287 216 fmovc_op = 0x11, fmovz_op = 0x12,
107d3400
MC		 217 fmovn_op = 0x13, fseleqz_op = 0x14,
218 frecip_op = 0x15, frsqrt_op = 0x16,
219 fselnez_op = 0x17, fmaddf_op = 0x18,
220 fmsubf_op = 0x19, frint_op = 0x1a,
221 fclass_op = 0x1b, fmin_op = 0x1c,
222 fmina_op = 0x1d, fmax_op = 0x1e,
223 fmaxa_op = 0x1f, fcvts_op = 0x20,
70342287
RB		 224 fcvtd_op = 0x21, fcvte_op = 0x22,
225 fcvtw_op = 0x24, fcvtl_op = 0x25,
226 fcmp_op = 0x30
90e8cacd
RB		 227};
228
229/*
230 * func field of cop1x opcodes (MIPS IV).
231 */
232enum cop1x_func {
70342287 233 lwxc1_op = 0x00, ldxc1_op = 0x01,
51061b88
DZ		 234 swxc1_op = 0x08, sdxc1_op = 0x09,
235 pfetch_op = 0x0f, madd_s_op = 0x20,
70342287
RB		 236 madd_d_op = 0x21, madd_e_op = 0x22,
237 msub_s_op = 0x28, msub_d_op = 0x29,
238 msub_e_op = 0x2a, nmadd_s_op = 0x30,
239 nmadd_d_op = 0x31, nmadd_e_op = 0x32,
240 nmsub_s_op = 0x38, nmsub_d_op = 0x39,
241 nmsub_e_op = 0x3a
90e8cacd
RB		 242};
243
244/*
245 * func field for mad opcodes (MIPS IV).
246 */
247enum mad_func {
70342287
RB		 248 madd_fp_op = 0x08, msub_fp_op = 0x0a,
249 nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e
90e8cacd
RB		 250};
251
380cd582
HC		 252/*
253 * func field for page table walker (Loongson-3).
254 */
255enum ptw_func {
256 lwdir_op = 0x00,
257 lwpte_op = 0x01,
258 lddir_op = 0x02,
259 ldpte_op = 0x03,
260};
261
90e8cacd
RB		 262/*
263 * func field for special3 lx opcodes (Cavium Octeon).
264 */
265enum lx_func {
266 lwx_op = 0x00,
267 lhx_op = 0x04,
70342287 268 lbux_op = 0x06,
90e8cacd 269 ldx_op = 0x08,
70342287
RB		 270 lwux_op = 0x10,
271 lhux_op = 0x14,
90e8cacd
RB		 272 lbx_op = 0x16,
273};
274
ab9e4fa0
MC		 275/*
276 * BSHFL opcodes
277 */
278enum bshfl_func {
279 wsbh_op = 0x2,
ab9e4fa0
MC		 280 seb_op = 0x10,
281 seh_op = 0x18,
282};
283
1f22d599
DD		 284/*
285 * DBSHFL opcodes
286 */
287enum dbshfl_func {
288 dsbh_op = 0x2,
289 dshd_op = 0x5,
290};
291
59e3559f
JH		 292/*
293 * MSA minor opcodes.
294 */
295enum msa_func {
296 msa_elm_op = 0x19,
297};
298
299/*
300 * MSA ELM opcodes.
301 */
302enum msa_elm {
303 msa_ctc_op = 0x3e,
304 msa_cfc_op = 0x7e,
305};
306
6701ca2d
LY		 307/*
308 * func field for MSA MI10 format.
309 */
310enum msa_mi10_func {
311 msa_ld_op = 8,
312 msa_st_op = 9,
313};
314
315/*
316 * MSA 2 bit format fields.
317 */
318enum msa_2b_fmt {
319 msa_fmt_b = 0,
320 msa_fmt_h = 1,
321 msa_fmt_w = 2,
322 msa_fmt_d = 3,
323};
324
2aa9fd06
SH		 325/*
326 * (microMIPS) Major opcodes.
327 */
328enum mm_major_op {
329 mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op,
330 mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op,
331 mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op,
332 mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op,
333 mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op,
59e3559f 334 mm_ori32_op, mm_pool32f_op, mm_pool32s_op, mm_reserved2_op,
2aa9fd06
SH		 335 mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op,
336 mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op,
337 mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op,
338 mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op,
339 mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op,
340 mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op,
341 mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op,
342 mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op,
343 mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op,
344 mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op,
345};
346
347/*
348 * (microMIPS) POOL32I minor opcodes.
349 */
350enum mm_32i_minor_op {
351 mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op,
352 mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op,
353 mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op,
354 mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op,
355 mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op,
356 mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op,
357 mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op,
358 mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op,
359 mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op,
360};
361
362/*
363 * (microMIPS) POOL32A minor opcodes.
364 */
365enum mm_32a_minor_op {
366 mm_sll32_op = 0x000,
367 mm_ins_op = 0x00c,
bef581ba 368 mm_sllv32_op = 0x010,
2aa9fd06
SH		 369 mm_ext_op = 0x02c,
370 mm_pool32axf_op = 0x03c,
371 mm_srl32_op = 0x040,
372 mm_sra_op = 0x080,
f31318fd 373 mm_srlv32_op = 0x090,
2aa9fd06
SH		 374 mm_rotr_op = 0x0c0,
375 mm_lwxs_op = 0x118,
376 mm_addu32_op = 0x150,
377 mm_subu32_op = 0x1d0,
ab9e4fa0 378 mm_wsbh_op = 0x1ec,
a8e897ad 379 mm_mul_op = 0x210,
2aa9fd06
SH		 380 mm_and_op = 0x250,
381 mm_or32_op = 0x290,
382 mm_xor32_op = 0x310,
7682f9e8 383 mm_slt_op = 0x350,
e8ef868b 384 mm_sltu_op = 0x390,
2aa9fd06
SH		 385};
386
387/*
388 * (microMIPS) POOL32B functions.
389 */
390enum mm_32b_func {
391 mm_lwc2_func = 0x0,
392 mm_lwp_func = 0x1,
393 mm_ldc2_func = 0x2,
394 mm_ldp_func = 0x4,
395 mm_lwm32_func = 0x5,
396 mm_cache_func = 0x6,
397 mm_ldm_func = 0x7,
398 mm_swc2_func = 0x8,
399 mm_swp_func = 0x9,
400 mm_sdc2_func = 0xa,
401 mm_sdp_func = 0xc,
402 mm_swm32_func = 0xd,
403 mm_sdm_func = 0xf,
404};
405
406/*
407 * (microMIPS) POOL32C functions.
408 */
409enum mm_32c_func {
410 mm_pref_func = 0x2,
411 mm_ll_func = 0x3,
412 mm_swr_func = 0x9,
413 mm_sc_func = 0xb,
414 mm_lwu_func = 0xe,
415};
416
417/*
418 * (microMIPS) POOL32AXF minor opcodes.
419 */
420enum mm_32axf_minor_op {
421 mm_mfc0_op = 0x003,
422 mm_mtc0_op = 0x00b,
423 mm_tlbp_op = 0x00d,
f3ec7a23 424 mm_mfhi32_op = 0x035,
2aa9fd06
SH		 425 mm_jalr_op = 0x03c,
426 mm_tlbr_op = 0x04d,
16d21a81 427 mm_mflo32_op = 0x075,
2aa9fd06
SH		 428 mm_jalrhb_op = 0x07c,
429 mm_tlbwi_op = 0x08d,
9f730a60 430 mm_mthi32_op = 0x0b5,
2aa9fd06 431 mm_tlbwr_op = 0x0cd,
9f730a60 432 mm_mtlo32_op = 0x0f5,
61c64cf9 433 mm_di_op = 0x11d,
2aa9fd06
SH		 434 mm_jalrs_op = 0x13c,
435 mm_jalrshb_op = 0x17c,
7ed82ad1 436 mm_sync_op = 0x1ad,
2aa9fd06 437 mm_syscall_op = 0x22d,
f263839a 438 mm_wait_op = 0x24d,
2aa9fd06 439 mm_eret_op = 0x3cd,
4c12a854 440 mm_divu_op = 0x5dc,
2aa9fd06
SH		 441};
442
443/*
444 * (microMIPS) POOL32F minor opcodes.
445 */
446enum mm_32f_minor_op {
447 mm_32f_00_op = 0x00,
448 mm_32f_01_op = 0x01,
449 mm_32f_02_op = 0x02,
450 mm_32f_10_op = 0x08,
451 mm_32f_11_op = 0x09,
452 mm_32f_12_op = 0x0a,
453 mm_32f_20_op = 0x10,
454 mm_32f_30_op = 0x18,
455 mm_32f_40_op = 0x20,
456 mm_32f_41_op = 0x21,
457 mm_32f_42_op = 0x22,
458 mm_32f_50_op = 0x28,
459 mm_32f_51_op = 0x29,
460 mm_32f_52_op = 0x2a,
461 mm_32f_60_op = 0x30,
462 mm_32f_70_op = 0x38,
463 mm_32f_73_op = 0x3b,
464 mm_32f_74_op = 0x3c,
465};
466
467/*
468 * (microMIPS) POOL32F secondary minor opcodes.
469 */
470enum mm_32f_10_minor_op {
471 mm_lwxc1_op = 0x1,
472 mm_swxc1_op,
473 mm_ldxc1_op,
474 mm_sdxc1_op,
475 mm_luxc1_op,
476 mm_suxc1_op,
477};
478
479enum mm_32f_func {
480 mm_lwxc1_func = 0x048,
481 mm_swxc1_func = 0x088,
482 mm_ldxc1_func = 0x0c8,
483 mm_sdxc1_func = 0x108,
484};
485
486/*
487 * (microMIPS) POOL32F secondary minor opcodes.
488 */
489enum mm_32f_40_minor_op {
490 mm_fmovf_op,
491 mm_fmovt_op,
492};
493
494/*
495 * (microMIPS) POOL32F secondary minor opcodes.
496 */
497enum mm_32f_60_minor_op {
498 mm_fadd_op,
499 mm_fsub_op,
500 mm_fmul_op,
501 mm_fdiv_op,
502};
503
504/*
505 * (microMIPS) POOL32F secondary minor opcodes.
506 */
507enum mm_32f_70_minor_op {
508 mm_fmovn_op,
509 mm_fmovz_op,
510};
511
512/*
513 * (microMIPS) POOL32FXF secondary minor opcodes for POOL32F.
514 */
515enum mm_32f_73_minor_op {
516 mm_fmov0_op = 0x01,
517 mm_fcvtl_op = 0x04,
518 mm_movf0_op = 0x05,
519 mm_frsqrt_op = 0x08,
520 mm_ffloorl_op = 0x0c,
521 mm_fabs0_op = 0x0d,
522 mm_fcvtw_op = 0x24,
523 mm_movt0_op = 0x25,
524 mm_fsqrt_op = 0x28,
525 mm_ffloorw_op = 0x2c,
526 mm_fneg0_op = 0x2d,
527 mm_cfc1_op = 0x40,
528 mm_frecip_op = 0x48,
529 mm_fceill_op = 0x4c,
530 mm_fcvtd0_op = 0x4d,
531 mm_ctc1_op = 0x60,
532 mm_fceilw_op = 0x6c,
533 mm_fcvts0_op = 0x6d,
534 mm_mfc1_op = 0x80,
535 mm_fmov1_op = 0x81,
536 mm_movf1_op = 0x85,
537 mm_ftruncl_op = 0x8c,
538 mm_fabs1_op = 0x8d,
539 mm_mtc1_op = 0xa0,
540 mm_movt1_op = 0xa5,
541 mm_ftruncw_op = 0xac,
542 mm_fneg1_op = 0xad,
9355e59c 543 mm_mfhc1_op = 0xc0,
2aa9fd06
SH		 544 mm_froundl_op = 0xcc,
545 mm_fcvtd1_op = 0xcd,
9355e59c 546 mm_mthc1_op = 0xe0,
2aa9fd06
SH		 547 mm_froundw_op = 0xec,
548 mm_fcvts1_op = 0xed,
549};
550
59e3559f
JH		 551/*
552 * (microMIPS) POOL32S minor opcodes.
553 */
554enum mm_32s_minor_op {
555 mm_32s_elm_op = 0x16,
556};
557
2aa9fd06
SH		 558/*
559 * (microMIPS) POOL16C minor opcodes.
560 */
561enum mm_16c_minor_op {
562 mm_lwm16_op = 0x04,
563 mm_swm16_op = 0x05,
dfb033f0
TW		 564 mm_jr16_op = 0x0c,
565 mm_jrc_op = 0x0d,
566 mm_jalr16_op = 0x0e,
567 mm_jalrs16_op = 0x0f,
568 mm_jraddiusp_op = 0x18,
2aa9fd06
SH		 569};
570
571/*
572 * (microMIPS) POOL16D minor opcodes.
573 */
574enum mm_16d_minor_op {
575 mm_addius5_func,
576 mm_addiusp_func,
577};
578
cd574704
SH		 579/*
580 * (MIPS16e) opcodes.
581 */
582enum MIPS16e_ops {
583 MIPS16e_jal_op = 003,
584 MIPS16e_ld_op = 007,
585 MIPS16e_i8_op = 014,
586 MIPS16e_sd_op = 017,
587 MIPS16e_lb_op = 020,
588 MIPS16e_lh_op = 021,
589 MIPS16e_lwsp_op = 022,
590 MIPS16e_lw_op = 023,
591 MIPS16e_lbu_op = 024,
592 MIPS16e_lhu_op = 025,
593 MIPS16e_lwpc_op = 026,
594 MIPS16e_lwu_op = 027,
595 MIPS16e_sb_op = 030,
596 MIPS16e_sh_op = 031,
597 MIPS16e_swsp_op = 032,
598 MIPS16e_sw_op = 033,
599 MIPS16e_rr_op = 035,
600 MIPS16e_extend_op = 036,
601 MIPS16e_i64_op = 037,
602};
603
604enum MIPS16e_i64_func {
605 MIPS16e_ldsp_func,
606 MIPS16e_sdsp_func,
607 MIPS16e_sdrasp_func,
608 MIPS16e_dadjsp_func,
609 MIPS16e_ldpc_func,
610};
611
612enum MIPS16e_rr_func {
613 MIPS16e_jr_func,
614};
615
616enum MIPS6e_i8_func {
617 MIPS16e_swrasp_func = 02,
618};
619
102cedc3 620/*
29e28003 621 * (microMIPS) NOP instruction.
102cedc3
LY		 622 */
623#define MM_NOP16 0x0c00
624
85dfaf08 625struct j_format {
8471ac1b
RB		 626 __BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */
627 __BITFIELD_FIELD(unsigned int target : 26,
85dfaf08
RB		 628 ;))
629};
630
631struct i_format { /* signed immediate format */
8471ac1b
RB		 632 __BITFIELD_FIELD(unsigned int opcode : 6,
633 __BITFIELD_FIELD(unsigned int rs : 5,
634 __BITFIELD_FIELD(unsigned int rt : 5,
635 __BITFIELD_FIELD(signed int simmediate : 16,
85dfaf08
RB		 636 ;))))
637};
638
639struct u_format { /* unsigned immediate format */
8471ac1b
RB		 640 __BITFIELD_FIELD(unsigned int opcode : 6,
641 __BITFIELD_FIELD(unsigned int rs : 5,
642 __BITFIELD_FIELD(unsigned int rt : 5,
643 __BITFIELD_FIELD(unsigned int uimmediate : 16,
85dfaf08
RB		 644 ;))))
645};
646
647struct c_format { /* Cache (>= R6000) format */
8471ac1b
RB		 648 __BITFIELD_FIELD(unsigned int opcode : 6,
649 __BITFIELD_FIELD(unsigned int rs : 5,
650 __BITFIELD_FIELD(unsigned int c_op : 3,
651 __BITFIELD_FIELD(unsigned int cache : 2,
652 __BITFIELD_FIELD(unsigned int simmediate : 16,
85dfaf08
RB		 653 ;)))))
654};
655
656struct r_format { /* Register format */
8471ac1b
RB		 657 __BITFIELD_FIELD(unsigned int opcode : 6,
658 __BITFIELD_FIELD(unsigned int rs : 5,
659 __BITFIELD_FIELD(unsigned int rt : 5,
660 __BITFIELD_FIELD(unsigned int rd : 5,
661 __BITFIELD_FIELD(unsigned int re : 5,
662 __BITFIELD_FIELD(unsigned int func : 6,
85dfaf08
RB		 663 ;))))))
664};
665
258f3a2e
JH		 666struct c0r_format { /* C0 register format */
667 __BITFIELD_FIELD(unsigned int opcode : 6,
668 __BITFIELD_FIELD(unsigned int rs : 5,
669 __BITFIELD_FIELD(unsigned int rt : 5,
670 __BITFIELD_FIELD(unsigned int rd : 5,
671 __BITFIELD_FIELD(unsigned int z: 8,
672 __BITFIELD_FIELD(unsigned int sel : 3,
673 ;))))))
674};
675
676struct mfmc0_format { /* MFMC0 register format */
677 __BITFIELD_FIELD(unsigned int opcode : 6,
678 __BITFIELD_FIELD(unsigned int rs : 5,
679 __BITFIELD_FIELD(unsigned int rt : 5,
680 __BITFIELD_FIELD(unsigned int rd : 5,
681 __BITFIELD_FIELD(unsigned int re : 5,
682 __BITFIELD_FIELD(unsigned int sc : 1,
683 __BITFIELD_FIELD(unsigned int : 2,
684 __BITFIELD_FIELD(unsigned int sel : 3,
685 ;))))))))
686};
687
688struct co_format { /* C0 CO format */
689 __BITFIELD_FIELD(unsigned int opcode : 6,
690 __BITFIELD_FIELD(unsigned int co : 1,
691 __BITFIELD_FIELD(unsigned int code : 19,
692 __BITFIELD_FIELD(unsigned int func : 6,
693 ;))))
694};
695
85dfaf08 696struct p_format { /* Performance counter format (R10000) */
8471ac1b
RB		 697 __BITFIELD_FIELD(unsigned int opcode : 6,
698 __BITFIELD_FIELD(unsigned int rs : 5,
699 __BITFIELD_FIELD(unsigned int rt : 5,
700 __BITFIELD_FIELD(unsigned int rd : 5,
701 __BITFIELD_FIELD(unsigned int re : 5,
702 __BITFIELD_FIELD(unsigned int func : 6,
85dfaf08
RB		 703 ;))))))
704};
705
70342287 706struct f_format { /* FPU register format */
8471ac1b
RB		 707 __BITFIELD_FIELD(unsigned int opcode : 6,
708 __BITFIELD_FIELD(unsigned int : 1,
709 __BITFIELD_FIELD(unsigned int fmt : 4,
710 __BITFIELD_FIELD(unsigned int rt : 5,
711 __BITFIELD_FIELD(unsigned int rd : 5,
712 __BITFIELD_FIELD(unsigned int re : 5,
713 __BITFIELD_FIELD(unsigned int func : 6,
85dfaf08
RB		 714 ;)))))))
715};
716
717struct ma_format { /* FPU multiply and add format (MIPS IV) */
8471ac1b
RB		 718 __BITFIELD_FIELD(unsigned int opcode : 6,
719 __BITFIELD_FIELD(unsigned int fr : 5,
720 __BITFIELD_FIELD(unsigned int ft : 5,
721 __BITFIELD_FIELD(unsigned int fs : 5,
722 __BITFIELD_FIELD(unsigned int fd : 5,
723 __BITFIELD_FIELD(unsigned int func : 4,
724 __BITFIELD_FIELD(unsigned int fmt : 2,
85dfaf08
RB		 725 ;)))))))
726};
727
728struct b_format { /* BREAK and SYSCALL */
8471ac1b
RB		 729 __BITFIELD_FIELD(unsigned int opcode : 6,
730 __BITFIELD_FIELD(unsigned int code : 20,
731 __BITFIELD_FIELD(unsigned int func : 6,
85dfaf08
RB		 732 ;)))
733};
734
8fba1e58 735struct ps_format { /* MIPS-3D / paired single format */
8471ac1b
RB		 736 __BITFIELD_FIELD(unsigned int opcode : 6,
737 __BITFIELD_FIELD(unsigned int rs : 5,
738 __BITFIELD_FIELD(unsigned int ft : 5,
739 __BITFIELD_FIELD(unsigned int fs : 5,
740 __BITFIELD_FIELD(unsigned int fd : 5,
741 __BITFIELD_FIELD(unsigned int func : 6,
8fba1e58
RB		 742 ;))))))
743};
744
745struct v_format { /* MDMX vector format */
8471ac1b
RB		 746 __BITFIELD_FIELD(unsigned int opcode : 6,
747 __BITFIELD_FIELD(unsigned int sel : 4,
748 __BITFIELD_FIELD(unsigned int fmt : 1,
749 __BITFIELD_FIELD(unsigned int vt : 5,
750 __BITFIELD_FIELD(unsigned int vs : 5,
751 __BITFIELD_FIELD(unsigned int vd : 5,
752 __BITFIELD_FIELD(unsigned int func : 6,
8fba1e58
RB		 753 ;)))))))
754};
755
6701ca2d
LY		 756struct msa_mi10_format { /* MSA MI10 */
757 __BITFIELD_FIELD(unsigned int opcode : 6,
758 __BITFIELD_FIELD(signed int s10 : 10,
759 __BITFIELD_FIELD(unsigned int rs : 5,
760 __BITFIELD_FIELD(unsigned int wd : 5,
761 __BITFIELD_FIELD(unsigned int func : 4,
762 __BITFIELD_FIELD(unsigned int df : 2,
763 ;))))))
764};
765
3f88ec63
MD		 766struct dsp_format { /* SPEC3 DSP format instructions */
767 __BITFIELD_FIELD(unsigned int opcode : 6,
768 __BITFIELD_FIELD(unsigned int base : 5,
769 __BITFIELD_FIELD(unsigned int index : 5,
770 __BITFIELD_FIELD(unsigned int rd : 5,
771 __BITFIELD_FIELD(unsigned int op : 5,
772 __BITFIELD_FIELD(unsigned int func : 6,
773 ;))))))
774};
775
aa1af47f 776struct spec3_format { /* SPEC3 */
8471ac1b
RB		 777 __BITFIELD_FIELD(unsigned int opcode:6,
778 __BITFIELD_FIELD(unsigned int rs:5,
779 __BITFIELD_FIELD(unsigned int rt:5,
780 __BITFIELD_FIELD(signed int simmediate:9,
781 __BITFIELD_FIELD(unsigned int func:7,
aa1af47f
LY		 782 ;)))))
783};
784
2aa9fd06
SH		 785/*
786 * microMIPS instruction formats (32-bit length)
787 *
788 * NOTE:
789 * Parenthesis denote whether the format is a microMIPS instruction or
790 * if it is MIPS32 instruction re-encoded for use in the microMIPS ASE.
791 */
792struct fb_format { /* FPU branch format (MIPS32) */
8471ac1b
RB		 793 __BITFIELD_FIELD(unsigned int opcode : 6,
794 __BITFIELD_FIELD(unsigned int bc : 5,
795 __BITFIELD_FIELD(unsigned int cc : 3,
796 __BITFIELD_FIELD(unsigned int flag : 2,
797 __BITFIELD_FIELD(signed int simmediate : 16,
2aa9fd06
SH		 798 ;)))))
799};
800
801struct fp0_format { /* FPU multiply and add format (MIPS32) */
8471ac1b
RB		 802 __BITFIELD_FIELD(unsigned int opcode : 6,
803 __BITFIELD_FIELD(unsigned int fmt : 5,
804 __BITFIELD_FIELD(unsigned int ft : 5,
805 __BITFIELD_FIELD(unsigned int fs : 5,
806 __BITFIELD_FIELD(unsigned int fd : 5,
807 __BITFIELD_FIELD(unsigned int func : 6,
2aa9fd06
SH		 808 ;))))))
809};
810
29e28003 811struct mm_fp0_format { /* FPU multiply and add format (microMIPS) */
8471ac1b
RB		 812 __BITFIELD_FIELD(unsigned int opcode : 6,
813 __BITFIELD_FIELD(unsigned int ft : 5,
814 __BITFIELD_FIELD(unsigned int fs : 5,
815 __BITFIELD_FIELD(unsigned int fd : 5,
816 __BITFIELD_FIELD(unsigned int fmt : 3,
817 __BITFIELD_FIELD(unsigned int op : 2,
818 __BITFIELD_FIELD(unsigned int func : 6,
2aa9fd06
SH		 819 ;)))))))
820};
821
822struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */
8471ac1b
RB		 823 __BITFIELD_FIELD(unsigned int opcode : 6,
824 __BITFIELD_FIELD(unsigned int op : 5,
825 __BITFIELD_FIELD(unsigned int rt : 5,
826 __BITFIELD_FIELD(unsigned int fs : 5,
827 __BITFIELD_FIELD(unsigned int fd : 5,
828 __BITFIELD_FIELD(unsigned int func : 6,
2aa9fd06
SH		 829 ;))))))
830};
831
832struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */
8471ac1b
RB		 833 __BITFIELD_FIELD(unsigned int opcode : 6,
834 __BITFIELD_FIELD(unsigned int rt : 5,
835 __BITFIELD_FIELD(unsigned int fs : 5,
836 __BITFIELD_FIELD(unsigned int fmt : 2,
837 __BITFIELD_FIELD(unsigned int op : 8,
838 __BITFIELD_FIELD(unsigned int func : 6,
2aa9fd06
SH		 839 ;))))))
840};
841
842struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */
8471ac1b
RB		 843 __BITFIELD_FIELD(unsigned int opcode : 6,
844 __BITFIELD_FIELD(unsigned int fd : 5,
845 __BITFIELD_FIELD(unsigned int fs : 5,
846 __BITFIELD_FIELD(unsigned int cc : 3,
847 __BITFIELD_FIELD(unsigned int zero : 2,
848 __BITFIELD_FIELD(unsigned int fmt : 2,
849 __BITFIELD_FIELD(unsigned int op : 3,
850 __BITFIELD_FIELD(unsigned int func : 6,
2aa9fd06
SH		 851 ;))))))))
852};
853
854struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */
8471ac1b
RB		 855 __BITFIELD_FIELD(unsigned int opcode : 6,
856 __BITFIELD_FIELD(unsigned int rt : 5,
857 __BITFIELD_FIELD(unsigned int fs : 5,
858 __BITFIELD_FIELD(unsigned int fmt : 3,
859 __BITFIELD_FIELD(unsigned int op : 7,
860 __BITFIELD_FIELD(unsigned int func : 6,
2aa9fd06
SH		 861 ;))))))
862};
863
864struct mm_fp4_format { /* FPU c.cond format (microMIPS) */
8471ac1b
RB		 865 __BITFIELD_FIELD(unsigned int opcode : 6,
866 __BITFIELD_FIELD(unsigned int rt : 5,
867 __BITFIELD_FIELD(unsigned int fs : 5,
868 __BITFIELD_FIELD(unsigned int cc : 3,
869 __BITFIELD_FIELD(unsigned int fmt : 3,
870 __BITFIELD_FIELD(unsigned int cond : 4,
871 __BITFIELD_FIELD(unsigned int func : 6,
2aa9fd06
SH		 872 ;)))))))
873};
874
875struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */
8471ac1b
RB		 876 __BITFIELD_FIELD(unsigned int opcode : 6,
877 __BITFIELD_FIELD(unsigned int index : 5,
878 __BITFIELD_FIELD(unsigned int base : 5,
879 __BITFIELD_FIELD(unsigned int fd : 5,
880 __BITFIELD_FIELD(unsigned int op : 5,
881 __BITFIELD_FIELD(unsigned int func : 6,
2aa9fd06
SH		 882 ;))))))
883};
884
885struct fp6_format { /* FPU madd and msub format (MIPS IV) */
8471ac1b
RB		 886 __BITFIELD_FIELD(unsigned int opcode : 6,
887 __BITFIELD_FIELD(unsigned int fr : 5,
888 __BITFIELD_FIELD(unsigned int ft : 5,
889 __BITFIELD_FIELD(unsigned int fs : 5,
890 __BITFIELD_FIELD(unsigned int fd : 5,
891 __BITFIELD_FIELD(unsigned int func : 6,
2aa9fd06
SH		 892 ;))))))
893};
894
895struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */
8471ac1b
RB		 896 __BITFIELD_FIELD(unsigned int opcode : 6,
897 __BITFIELD_FIELD(unsigned int ft : 5,
898 __BITFIELD_FIELD(unsigned int fs : 5,
899 __BITFIELD_FIELD(unsigned int fd : 5,
900 __BITFIELD_FIELD(unsigned int fr : 5,
901 __BITFIELD_FIELD(unsigned int func : 6,
2aa9fd06
SH		 902 ;))))))
903};
904
905struct mm_i_format { /* Immediate format (microMIPS) */
8471ac1b
RB		 906 __BITFIELD_FIELD(unsigned int opcode : 6,
907 __BITFIELD_FIELD(unsigned int rt : 5,
908 __BITFIELD_FIELD(unsigned int rs : 5,
909 __BITFIELD_FIELD(signed int simmediate : 16,
2aa9fd06
SH		 910 ;))))
911};
912
913struct mm_m_format { /* Multi-word load/store format (microMIPS) */
8471ac1b
RB		 914 __BITFIELD_FIELD(unsigned int opcode : 6,
915 __BITFIELD_FIELD(unsigned int rd : 5,
916 __BITFIELD_FIELD(unsigned int base : 5,
917 __BITFIELD_FIELD(unsigned int func : 4,
918 __BITFIELD_FIELD(signed int simmediate : 12,
2aa9fd06
SH		 919 ;)))))
920};
921
922struct mm_x_format { /* Scaled indexed load format (microMIPS) */
8471ac1b
RB		 923 __BITFIELD_FIELD(unsigned int opcode : 6,
924 __BITFIELD_FIELD(unsigned int index : 5,
925 __BITFIELD_FIELD(unsigned int base : 5,
926 __BITFIELD_FIELD(unsigned int rd : 5,
927 __BITFIELD_FIELD(unsigned int func : 11,
2aa9fd06
SH		 928 ;)))))
929};
930
69a1e6cb
MR		 931struct mm_a_format { /* ADDIUPC format (microMIPS) */
932 __BITFIELD_FIELD(unsigned int opcode : 6,
933 __BITFIELD_FIELD(unsigned int rs : 3,
934 __BITFIELD_FIELD(signed int simmediate : 23,
935 ;)))
936};
937
2aa9fd06
SH		 938/*
939 * microMIPS instruction formats (16-bit length)
940 */
941struct mm_b0_format { /* Unconditional branch format (microMIPS) */
8471ac1b
RB		 942 __BITFIELD_FIELD(unsigned int opcode : 6,
943 __BITFIELD_FIELD(signed int simmediate : 10,
944 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
2aa9fd06
SH		 945 ;)))
946};
947
948struct mm_b1_format { /* Conditional branch format (microMIPS) */
8471ac1b
RB		 949 __BITFIELD_FIELD(unsigned int opcode : 6,
950 __BITFIELD_FIELD(unsigned int rs : 3,
951 __BITFIELD_FIELD(signed int simmediate : 7,
952 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
2aa9fd06
SH		 953 ;))))
954};
955
956struct mm16_m_format { /* Multi-word load/store format */
8471ac1b
RB		 957 __BITFIELD_FIELD(unsigned int opcode : 6,
958 __BITFIELD_FIELD(unsigned int func : 4,
959 __BITFIELD_FIELD(unsigned int rlist : 2,
960 __BITFIELD_FIELD(unsigned int imm : 4,
961 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
2aa9fd06
SH		 962 ;)))))
963};
964
965struct mm16_rb_format { /* Signed immediate format */
8471ac1b
RB		 966 __BITFIELD_FIELD(unsigned int opcode : 6,
967 __BITFIELD_FIELD(unsigned int rt : 3,
968 __BITFIELD_FIELD(unsigned int base : 3,
969 __BITFIELD_FIELD(signed int simmediate : 4,
970 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
2aa9fd06
SH		 971 ;)))))
972};
973
974struct mm16_r3_format { /* Load from global pointer format */
8471ac1b
RB		 975 __BITFIELD_FIELD(unsigned int opcode : 6,
976 __BITFIELD_FIELD(unsigned int rt : 3,
977 __BITFIELD_FIELD(signed int simmediate : 7,
978 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
2aa9fd06
SH		 979 ;))))
980};
981
982struct mm16_r5_format { /* Load/store from stack pointer format */
8471ac1b
RB		 983 __BITFIELD_FIELD(unsigned int opcode : 6,
984 __BITFIELD_FIELD(unsigned int rt : 5,
cea8cd49 985 __BITFIELD_FIELD(unsigned int imm : 5,
8471ac1b 986 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
2aa9fd06
SH		 987 ;))))
988};
989
cd574704
SH		 990/*
991 * MIPS16e instruction formats (16-bit length)
992 */
993struct m16e_rr {
8471ac1b
RB		 994 __BITFIELD_FIELD(unsigned int opcode : 5,
995 __BITFIELD_FIELD(unsigned int rx : 3,
996 __BITFIELD_FIELD(unsigned int nd : 1,
997 __BITFIELD_FIELD(unsigned int l : 1,
998 __BITFIELD_FIELD(unsigned int ra : 1,
999 __BITFIELD_FIELD(unsigned int func : 5,
cd574704
SH		 1000 ;))))))
1001};
1002
1003struct m16e_jal {
8471ac1b
RB		 1004 __BITFIELD_FIELD(unsigned int opcode : 5,
1005 __BITFIELD_FIELD(unsigned int x : 1,
1006 __BITFIELD_FIELD(unsigned int imm20_16 : 5,
1007 __BITFIELD_FIELD(signed int imm25_21 : 5,
cd574704
SH		 1008 ;))))
1009};
1010
1011struct m16e_i64 {
8471ac1b
RB		 1012 __BITFIELD_FIELD(unsigned int opcode : 5,
1013 __BITFIELD_FIELD(unsigned int func : 3,
1014 __BITFIELD_FIELD(unsigned int imm : 8,
cd574704
SH		 1015 ;)))
1016};
1017
1018struct m16e_ri64 {
8471ac1b
RB		 1019 __BITFIELD_FIELD(unsigned int opcode : 5,
1020 __BITFIELD_FIELD(unsigned int func : 3,
1021 __BITFIELD_FIELD(unsigned int ry : 3,
1022 __BITFIELD_FIELD(unsigned int imm : 5,
cd574704
SH		 1023 ;))))
1024};
1025
1026struct m16e_ri {
8471ac1b
RB		 1027 __BITFIELD_FIELD(unsigned int opcode : 5,
1028 __BITFIELD_FIELD(unsigned int rx : 3,
1029 __BITFIELD_FIELD(unsigned int imm : 8,
cd574704
SH		 1030 ;)))
1031};
1032
1033struct m16e_rri {
8471ac1b
RB		 1034 __BITFIELD_FIELD(unsigned int opcode : 5,
1035 __BITFIELD_FIELD(unsigned int rx : 3,
1036 __BITFIELD_FIELD(unsigned int ry : 3,
1037 __BITFIELD_FIELD(unsigned int imm : 5,
cd574704
SH		 1038 ;))))
1039};
1040
1041struct m16e_i8 {
8471ac1b
RB		 1042 __BITFIELD_FIELD(unsigned int opcode : 5,
1043 __BITFIELD_FIELD(unsigned int func : 3,
1044 __BITFIELD_FIELD(unsigned int imm : 8,
cd574704
SH		 1045 ;)))
1046};
1047
90e8cacd
RB		 1048union mips_instruction {
1049 unsigned int word;
1050 unsigned short halfword[2];
1051 unsigned char byte[4];
1052 struct j_format j_format;
1053 struct i_format i_format;
1054 struct u_format u_format;
1055 struct c_format c_format;
1056 struct r_format r_format;
258f3a2e
JH		 1057 struct c0r_format c0r_format;
1058 struct mfmc0_format mfmc0_format;
1059 struct co_format co_format;
90e8cacd
RB		 1060 struct p_format p_format;
1061 struct f_format f_format;
1062 struct ma_format ma_format;
6701ca2d 1063 struct msa_mi10_format msa_mi10_format;
90e8cacd 1064 struct b_format b_format;
8fba1e58
RB		 1065 struct ps_format ps_format;
1066 struct v_format v_format;
3f88ec63 1067 struct dsp_format dsp_format;
aa1af47f 1068 struct spec3_format spec3_format;
2aa9fd06
SH		 1069 struct fb_format fb_format;
1070 struct fp0_format fp0_format;
1071 struct mm_fp0_format mm_fp0_format;
1072 struct fp1_format fp1_format;
1073 struct mm_fp1_format mm_fp1_format;
1074 struct mm_fp2_format mm_fp2_format;
1075 struct mm_fp3_format mm_fp3_format;
1076 struct mm_fp4_format mm_fp4_format;
1077 struct mm_fp5_format mm_fp5_format;
1078 struct fp6_format fp6_format;
1079 struct mm_fp6_format mm_fp6_format;
1080 struct mm_i_format mm_i_format;
1081 struct mm_m_format mm_m_format;
1082 struct mm_x_format mm_x_format;
69a1e6cb 1083 struct mm_a_format mm_a_format;
2aa9fd06
SH		 1084 struct mm_b0_format mm_b0_format;
1085 struct mm_b1_format mm_b1_format;
1086 struct mm16_m_format mm16_m_format ;
1087 struct mm16_rb_format mm16_rb_format;
1088 struct mm16_r3_format mm16_r3_format;
1089 struct mm16_r5_format mm16_r5_format;
90e8cacd
RB		 1090};
1091
cd574704
SH		 1092union mips16e_instruction {
1093 unsigned int full : 16;
1094 struct m16e_rr rr;
1095 struct m16e_jal jal;
1096 struct m16e_i64 i64;
1097 struct m16e_ri64 ri64;
1098 struct m16e_ri ri;
1099 struct m16e_rri rri;
1100 struct m16e_i8 i8;
1101};
1102
90e8cacd 1103#endif /* _UAPI_ASM_INST_H */
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